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L.-H. Hsu

dblp:52/3990 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 91% Integrated circuit design · 9%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › VLSI layout
gate matrix layout		 0.011987
Automated Layout Generation Using Gate Matrix Approach · DAC 1987
Electronic design automation › physical design
layout synthesis		 0.011987
Automated Layout Generation Using Gate Matrix Approach · DAC 1987
Electronic design automation
physical design		 0.011987
Automated Layout Generation Using Gate Matrix Approach · DAC 1987

Methods — techniques the papers use, named apart from their topics

net-list and realization matrix models · 0.0gate matrix approach · 0.0folding technique · 0.0
YearPublicationVenuePosition
1987 Automated Layout Generation Using Gate Matrix Approach
abstract
This paper presents a software system ALSUGMA for automated gate matrix layout generation. Its structured Net-List and Realization Matrix models which are different from previous interval graph approach are introduced. Algorithms to minimize and realize the gate matrix layout are also presented with examples. Empirical results showed good performance in terms of both speed and layout quality. Folding technique for such layout style is also introduced.
L.-H. Hsu
 DAC3