Real-time object detection is important for surveillance applications. This paper describes a high-performance object detector using a commercially available FPGA. Major bottlenecks in the real AdaBoost classifier are resolved. A new FIR-filter-like hardware architecture takes advantage of an FPGA's hardware parallelism and block-RAM structure. The resulting design uses Xilinx Virtex 5 and achieves the real-time processing performance of 220 f/s at 201 MHz and adjustable recognition performance with a variable number of weak classifiers. This is the first demonstration of a histogram of oriented gradients and Real AdaBoost detector on an FPGA.

Network-on-chip (NoC) architectures are emerged as a promising solution to the lack of scalability in multiprocessor systems-on-chips (MPSoCs). In this paper, we propose a novel BMNoC configuration algorithm together with simulation results. Our BMNoC configuration algorithm analyses the data traffic of the target application and determines which core is the right one to put into the certain cluster with its communication volume and locality. Furthermore, the simulation results illustrate the better latency than earlier studies and feasibility of BMNoC.

We introduce a heuristic that generates as few a number of test vectors as possible with high branch coverage for the functional verification of digital design. The challenge is how to save time and effort for sufficient verification at system-level. We focus on generating test vectors from the circuit specification written in C. We reuse them to SystemC description by removing their redundancies while maintaining the branch coverage as is. Experimental results of our practical design show that over 90% on average of the redundant test vectors were reduced with 100% branch coverage maintained. The reused test vectors for SystemC Bus Cycle Accurate models scored 80% branch coverage on average. These results are significant for saving verification cost and beneficial for simplifying debugging works.

We propose a real-world-oriented interface called the "mirror metaphor interaction system". The display shows a mirror image from a camera facing a user, and the user can "touch" objects without making direct contact with the display. The "touched" object displays a menu or works directly. Objects can be placed in a remote room as well as in the user's room, and can also be moved around in a room. The user can therefore control equipment or interact with objects anywhere through the display of the system by combining images from local and remote places translucently. Our demonstration shows how the interface makes it easy to establish contact with movable objects in a remote room by "touching" them in the display.

We have succeeded in developing a quick and fully automated system that can generate photo-realistic 3D CG data based on a real object. A major factor in this success comes from our findings through psychophysical experiments that human observers do not have an accurate idea of what should be actually reflected as inter-reflections on the surface of an object. Taking advantage of this characteristic of human vision, we propose a new inter-reflection representation technique in which inter-reflections are simulated by allowing the same quantity of reflection components as there are in the background to pass through the object. Since inter-reflection and transparency are calculated by the same algorithm, our system can capture 3D CG data from various real objects having a strong inter-reflection, such as plastic and porcelain items or translucent glass and acrylic resin objects. The synthetic images from the 3D CG data generated with this pseudo inter-reflection and transparency look very natural. In addition, the 3D CG data and synthetic images are produced quickly at a lower cost.

This paper proposes an efficient paired-net routing algorithm. A paired net consists of two nets assigned to adjacent tracks and columns. The paired-net routing approach is applied for differential drive nets in a bipolar ECL LSI to decrease signal skew and enhance signal integrity. Paired nets can cause a new type of cyclic constraint, which does not appear in the conventional vertical constraint graph. To wire these paired nets, the new type of cyclic constraint must be detected and resolved. We applied our approach to two actual bipolar ECL circuits: a 4.0-k-gate circuit, which operated at 3 Gbit/s, and a 5.6-k-gate circuit, which operated at 2.5 Gbit/s. The experimental results verify the effectiveness of our paired-net routing approach.

This paper proposes one-dimensional spacing algorithms that minimize [maximize] the degree of separation [proximity] among the specified elements of a given integrated circuit layout. Number of problems on chip and MCM systems such as poor performance, higher crosstalk, lower yield etc. are related to the degree of separation [proximity]. The proposed algorithms utilize the attractive [repulsive] constraints to shrink [expand] the distances among the specified elements while keeping the layout free of any design rule errors. The spacing problem is reduced to a parametric linear programming problem and a network simplex algorithm is proposed for solving it. The proposed algorithms are implemented into a system called PERFECT for performance enhancement and crosstalk reduction. Given a routed design, PERFECT minimizes delay due to the coupled capacitance, which could contribute as much as 50-75% to the interconnect delay in near future. PERFECT utilizes the repulsive constraints between interconnect segments for the purpose. The experimental results show a significant delay improvement and the crosstalk reduction for submicron technologies.>

With the shrinking of feature size on silicon, the coupled capacitance between adjacent wires is contributing a significant factor to the interconnect delay, which already dominates the circuit performance. In the near future coupled capacitance could contribute as much as 50-75% to the interconnect delay which has been largely ignored by performance-oriented layout tools. Given a routed design, this work minimizes the delay and the peak cross-talk by re-adjusting the space between interconnects. It can reduce the circuit delay significantly and, in addition, reduce the peak cross-talk problem. An efficient technique based on the network simplex algorithm is used to solve the problem in the paradigm of compaction.

A one-dimensional compaction algorithm with attractive and repulsive constraints is proposed. Depending on these constraints, the proposed algorithm shrinks[expands] the spaces among the specified layout elements without causing any design rule violations, as if some force were affecting them. It implies that the resultant layout has less cross talk and delay. The proposed network simplex algorithm experimentally proves to be efficient in both time and space.