This work proposes a broadband transition from tapered microstrip line-to-substrate-integrated waveguide (SIW) using parallel half-mode SIW (HMSIW) for C/X-band applications. The proposed transition comprises four sections: a microstrip feed, tapered microstrip line, tapered parallel HMSIWs, and a waveguide section (SIW). Placing the parallel HMSIWs section between the tapered microstrip line section and the SIW part improves the S-parameters characteristics of the near-cut-off frequency. The HMSIWs section has a lower cut-off frequency than the SIW part, about 4.6 GHz. The lower cut-off- frequency is obtained by gradually altering the electromagnetic field mode to reduce reflection. Which helps convert from TEM mode to TM conversion. The proposed transition is designed, simulated, fabricated, and experimentally verified in order to compare between simulated and experimental results. For the back-to-back laboratory prototype of the transition, the experimental return loss results are less than 20 dB in the 4.6 to 11 GHz frequency range. At the same time, the measured minimum insertion loss is lower than 0.37 dB (maximum: 1.51 dB).

The concept of the corrugated via-wall substrate-integrated waveguide (CV-WSIW) reported by the same authors earlier has now been extended to the mm-wave frequency range, and the transitions for this category of SIWs from microstrip line (ML) are presented in this work. A new design of enhanced CV-WSIW for 18-40 GHz frequency range is proposed. The design includes a tapered section of the microstrip line and two rows of metallic vias with the gap between them. They are providing a better impedance match and reduced overall loss. The proposed design offers improved performance in terms of broadband, return loss (RL), insertion loss (IL), and total loss (TL). The laboratory prototypes are developed, and the obtained simulation results show a close agreement with the measured results. The experimental results show the minimum RL of 22dB, IL of 0.22-0.42dB, a fractional bandwidth of 75.80%, a figure-of-merit of 967.9, and the TL below 20% for ML/CV-WSIW transition within 18-40GHz range. Three additional ML/CV-WSIW transitions were also designed and tested, so that four tested transitions cover 8-60GHz range; an additional fifth transition was simulated only in 60-140GHz range.

This article presents a clockless nonuniform sampling scheme to enhance the energy efficiency of Internet of Things (IoT) applications. The proposed scheme employs a derivative-dependent mechanism that provides enhanced accuracy compared to other nonuniform sampling schemes while minimizing power consumption. By continuously monitoring the change in the derivative of the input signal, the proposed scheme identifies the most significant points of the signal, valuable for retention and conversion for effective signal reconstruction. In this scheme, the change in the derivative of the signal is compared to tunable threshold references, enabling adjustability to obtain the desired level of accuracy and adaptability to a variety of IoT applications. The proposed scheme is implemented in low- and high-speed systems that target low- and high-frequency applications, respectively. Fabricated using TSMC’s 0.13-$\mu $m CMOS technology, the performance is evaluated through experimental results in real-world scenarios. The proposed clockless derivative dependent sampling (CL-DDS) system can be integrated into the data acquisition system of an IoT device/sensor to save its critical power budget, while the threshold references are tuned to achieve the desired accuracy. The maximum power consumption of the proposed low- and high-speed CL-DDS designs is$1.15~\mu $W (@1 MHz) and$8.81~\mu $W (@20 MHz), respectively.

This paper presents and demonstrates a voltage feedback-based technique to implement a power management integrated circuit (PMIC) for piezoelectric energy harvesting. It is analytically shown that the conducting time interval of a rectifying diode at the maximum power point is a fixed ratio of the vibration period. Thus, it can be used as a feedback to track the maximum power without measuring the output current/power. The technique can be tailored to various interface circuits, including full-bridge, voltage doubler, and synchronized switch harvesting on an inductor. The micro-fabricated PMIC includes a full-bridge rectifier, a digital MPPT controller, and a zero-current-switching (ZCS) integrated buck converter that uses two off-chip inductor and rectifying capacitor. The proposed technique enables the implementation of robust and power-efficient PMICs for maximum power point tracking of piezoelectric energy harvesters. To evaluate the performance of the technique, a PMIC using 130 nm CMOS technology is implemented and tested with a low power (<0.5 mW) piezoelectric energy harvester. The results show that the PMIC effectively tracks the maximum power point at different vibration frequencies and amplitudes while the power consumption of its control circuitry is less than 0.001 mW.

This paper proposes a non-iterative method for the design of Radio Frequency Energy Harvesters (RFEHs) with maximum power conversion efficiency (PCE) at any given input power level. Because of the non-linear interdependency of the rectifier’s input impedance and its input voltage to matching network’s and rectifier’s parameters, the design of an RFEH with maximum efficiency requires numerous lengthy transient simulations of the entire energy harvester. Splitting the design space into two separate spaces which only interact with each other through the input voltage of the rectifier, the design goal can now be redefined to finding an optimum input voltage amplitude that maximizes the efficiency of the rectifier while enabling maximum power transfer from antenna to the input of the rectifier at the same time. Using the proposed method, the number of the required simulations to find optimum design values is significantly reduced compared to all previous methods reported in the literature, which also has been experimentally verified by designing three battery-loaded RFEHs at different input power levels in TSMC’s 130nm CMOS process. To further accelerate the design process, closed-form equations to calculate the efficiency and the input resistance of the rectifier are derived for the battery-loaded Dickson charge pump rectifiers.

This paper proposes the Corrugated Via-Wall Substrate Integrated Waveguide (CVWSIW) (with enhanced performance compared to the traditional SIW) and the transitions to this newly proposed CVWSIW from a conductor-backed coplanar waveguide (CB-CPW). The CB-CPW slot lines and the gap between two metallic via rows play a prominent role in widening the bandwidth and reducing the loss. The CB-CPW-CVWSIW transition is initially designed in the 4–8 GHz (C-band) range. Following the same design procedure, the transitions are made for other five different bands to cover the frequencies from 2 to 40 GHz. Improved performance in terms of bandwidth, insertion loss, and total loss is the benefit of the designed transitions with the proposed CVWSIW. Laboratory prototypes of the transitions are fabricated and experimentally measured to cross verify the simulation results. The measured results show, for example, the minimum return loss of 15 dB, maximum insertion loss of 0.36 dB, and fractional bandwidth of 62.16% for C-band.

This paper presents an ultra-low-power non-uniform sampling scheme using a derivative-based algorithm that can maintain a comparable accuracy to other non-uniform sampling schemes but with less complexity and lower power consumption. In this method, the change in the derivative of the signal above certain threshold values is used to identify high signal activity for retention of the significant points of the signal. The scheme is implemented using simple building blocks that calculate and compare the change in approximate real-time derivative to a tunable threshed value that can be adjusted to obtain the desired Compression Factor (CF) and Post-Reconstruction Signal-to-Noise plus Distortion Ratio (PR-SNDR) for different signal types. Fabricated in TSMC’s$0.13 \mu \text{m}$CMOS technology and tested with real-world biomedical signals, the proposed Derivative Dependent Sampling (DDS) system consumes a maximum power of 155 nW while achieving a CF of more than 6 for an Electrocardiography (ECG) signal. By adding the proposed DDS block to a data acquisition and processing system, the non-uniform sampling can reduce the power dissipation of the entire system.

This paper presents a Tapered Tunable Transmission Line (Tapered TTL) phase shifter that achieves a higher area efficiency than conventional Tunable Transmission Line (TTL) phase shifters while maintaining the same phase shift range with similar insertion losses. A systematic methodology is provided for the optimum design of the proposed phase shifter to maximize its area efficiency while providing the desired phase shift range and satisfying the maximum allowed input/output return and insertion losses. To verify the efficacy of the proposed solution, an eleven-cell phase shifter is fabricated in a standard 65-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology and the measurement results are reported. The fabricated circuit provides a 180-degree phase shift over the frequency range of 16.5 to 31 GHz with an average insertion loss of 7.2 dB. The proposed design presents a 25 percent reduction in the chip area per unit delay in comparison to the conventional design with the same average insertion loss.

This article presents a fully RF-powered wireless transceiver integrating an efficient RF energy harvester (RFEH), a Wake-up Receiver (WuRx), and a Wake-up Transmitter (WuTx) on a single CMOS chip. The WuRx is designed to operate with supply voltages as low as 300 mV allowing to be entirely powered up by the RF energy at power levels as low as −26 dBm. The capability of the WuRx to operate without using a power management unit (PMU) enhances the sensitivity and overall conversion efficiency of the RFEH system. By utilizing an ultralow-power ultralow-voltage envelope detector to obtain the required signal levels, using passive amplification instead of an active low-noise amplifier, and eliminating the voltage regulator removing its power overhead, the transceiver’s input sensitivity has been improved at least by a factor 2 (3 dB) compared to the other previously reported RF-powered transceivers. The proposed transmitter consists of a fast start-up oscillator and an efficient class E power amplifier, which can be externally tuned for different output powers. Fabricated in the TSMC’s 130-nm CMOS process, the measurement results show that the proposed WuRx consuming only 5.7 nW works with input powers as low as −26 dBm, and the proposed transmitter can work with input powers as low as −23 dBm. The WuTx outputs −11 dBm with 51% efficiency at 2.45 GHz using high-Q off-chip components.

This paper presents a low-power constant subthreshold transconductance reference circuit that produces a constant transconductance by subtracting the output currents of two independent transconductance references. By taking the difference between the output currents of the two independent transconductance references, process, voltage and temperature variations are reduced by minimizing the effects of channel length modulation and drain-induced barrier lowering without relying on feedback to regulate the drain voltage. The proposed reference, fabricated in TSMC’s 130 nm process and testing with off-chip temperature-insensitive resistors, can provide a constant transconductance over a temperature range of −30 to 120°C, and a supply voltage range of 0.5 to 1.7 V. The experimental result of the proposed transconductance reference shows an average variation of ±0.8% over temperature for the entire operating voltage range and an average variation of ±1.97% over voltage for the entire operating temperature range. Through the subtraction, the proposed circuit also shows less variation across process corners compared to the conventional constant transconductance reference. The proposed constant transconductance reference exhibits the highest power efficiency (transconductance over power consumption) amongst the reported constant transconductance references. At 0.5 V, the proposed transconductance reference produces a transconductance of 21.46$\mu \text{S}$, while consuming 1.95$\mu \text{W}$.

This article presents a highly-efficient radio frequency energy harvester that utilizes an extra matching network to produce a passively-amplified adaptive compensation voltage. The compensation voltage produced on the gate of the transistors reduces the transistors’ conduction loss by increasing the gate-source voltage when transistors are on and reduces the leakage current by producing a negative gate-source voltage when the transistors are off. This is the first work that produces an adaptive compensation voltage without using active components, resulting in a significantly higher conversion efficiency if passive components of high quality are utilized. The mathematical derivations show that the forward conduction loss and the leakage current of the transistors are minimized by utilizing the proposed technique, increasing the overall efficiency. The proposed rectifier is fabricated in a TSMC 130 nm standard CMOS process, and measurement results and simulation results are in good agreement. Measurement results show that the rectifier achieves the maximum efficiency of 61% and 63.4% for battery load of 1.2 V and 1.5 V, respectively, which is at least 20 % larger than the efficiency of the conventional Dickson’s rectifiers.

In this paper, a wide input range, 4-stage threshold voltage compensated RF-DC power converter is introduced. A novel threshold voltage compensation scheme is proposed that can be applied to a rectifier chain with a relatively low number of stages. This proposed structure is shown to provide a high power conversion efficiency (PCE) over a wide input power range that increases the coverage area of wireless powering. Designed and simulated in IBM 130-nm CMOS technology, the proposed 915-MHz rectifier exhibits a PCE of above 20% over the 20-dB input power range while driving a load resistor. For the same load, utilizing a minimal number of compensated rectifier stages, the proposed circuit exhibits a record maximum PCE of 52% at -10 dBm for single-ended Dickson-based CMOS rectifiers. The proposed circuit demonstrates a -22.3 dBm sensitivity for 1 V output across a 1-MΩ resistive load.

This paper presents a 60-GHz power amplifier (PA) fabricated in a 65-nm CMOS technology. The proposed PA utilizes a dual-mode amplification circuit topology to achieve a high level of output power and efficiency in a small die area. High-output power is achieved by combining class AB cascode stage with a conventional class A common source (CS) stage in a compact four-way differential distributed active transformer to increase the amplifier's power density. Driver stages consist of an enhanced cascode stage followed by a CS stage to achieve a high power (HP) gain. Fabricated in a 65-nm CMOS process, the maximum measured gain of the 60-GHz PA is 22 dB within a wide 3-dB bandwidth of 14 GHz. A maximum saturated output power of 19.7 dBm is measured in HP mode while consuming 430 mW over a 1.2 V core supply. In low-power (LP) mode of operation, the power gain of 20 dB and 19.7 dBm saturated power is measured at 60 GHz. The proposed dual-mode topology achieves an HP added efficiency of 25% and 19% in HP and LP modes, respectively.

A compact 2.0-11.0GHz CMOS ultra-wideband (UWB) low-noise amplifier (LNA) using tunable active inductors for suppressing in-band (over 4.8-6.0 GHz) WLAN interference signals is presented. In the proposed LNA, the active inductor in series with a small capacitor forms an active LC resonator which rejects or notches the undesired signals at the resonance frequency. Employing multiple resonators in the LNA increases the rejection depth. Moreover, the tunability of the active inductors allows for notching the signals over a wide frequency range. Designed and simulated in a 90 nm digital CMOS process, the proposed LNA with such active inductors used in notch filters occupies a core chip-area of only 0.0182 mm2. The LNA exhibits an average power gain of 16.5 dB over 2.0-11.0 GHz bandwidth while the rejection of unwanted WLAN interference signals is -44.8 dB at 5.81 GHz. The notch-frequency can be tuned in excess of 4.5-6.6 GHz, and the rejection depth can be increased to -87.5 dB, the highest rejection among the reported notch-filter UWB LNAs.

A novel loss-reduced distributed amplifier (DA), branched distributed amplifier (BDA), is presented. Unlike conventional DAs, in this structure the source/load is connected at the middle of input/output transmission lines. This technique effectively reduces the length of transmission lines and in turn lowers signal attenuation. Moreover, the optimal number of stages can be increased in the proposed structure. The final amplifier is implemented in 0.13 mum IBM's CMRF8SF CMOS as two cascaded DAs with different number of stages. Post-layout simulation results show a 3-dB bandwidth of 38.5 GHz and an average pass-band gain of 20.5 dB, resulting in a gainbandwidth (GBW) product of 408 GHz. Input matching is less than -20 dB and output matching is well below -10 dB over the entire bandwidth. The chip area is 1.2 mm by 0.6 mm and power consumption is 154 mW.

A fully-active low-noise amplifier (LNA) for ultra-wideband application is presented. Passive on-chip inductor of conventional LNA design is replaced by low-noise active inductor, significantly reducing the total chip area of the proposed CMOS LNA. The core LNA circuit is a cascoded common-source amplifier loaded with an active inductor. Two buffer stages are used to provide the required input and output impedance matching. The amplifier is designed and simulated in 0.13-mum RF CMOS process. It exhibits a forward gain (S21) of 11.2 dB, a noise figure (NF) of 2.2-4.0 dB, and return losses (S11 and S22) of less than -10 dB over the frequency range of 2.0 to 11.2 GHz while consuming only 13.5 mW from a power supply of 1.5 V. The proposed amplifier occupies 0.09 mm of chip area.

This paper presents a four-stage CMOS distributed amplifier (DA) design implemented in standard 0.18 mum CMOS technology. The proposed design eliminates the need for transmission line capacitors and, consequently, uses significantly smaller spiral inductors compared with the previous designs. Using the minimum size inductor, the bandwidth of the amplifiers is extended, and the quality factors of the on-chip inductor are improved. Proposed DA occupies the smallest die area (0.3mum*0.8mum) amongst the DAs reported with the same performance. A unity gain bandwidth of 10 GHz and a gain of 15 dB are measured. DC power dissipation is 56 mW

This paper presents a novel loss compensation technique, an active negative resistor produced by a capacitively source degenerated configuration, to improve the gain flatness and bandwidth of CMOS distributed amplifiers (DAs). This configuration provides the desired isolation from the transmission line at lower frequencies, and a frequency-increasing negative conductance that can fully compensate for the loss of the on-chip inductor over a broad frequency band. A 40 GHZ three-stage 0.13 mum CMOS DA is devised that outperforms previously published CMOS DAs by providing a large gain-bandwidth product of 200 GHz-dB with an improved gain-flatness of plusmn0.2 dB. The proposed loss compensated DA dissipates 24 mW from a 1.2 VDC supply