Level shifter and floating power supply for high-side channel are major challenges in high-voltage high-frequency DC-DC converters. This paper presents an up to 10 MHz GaN driver suitable for high-power-density automotive electronics. An adaptive short-pulse (ASP) high d$V_{\text {sw}}$/d$t$noise immunity level shifter (LS) with efficient analog noise blanker (ANB) is proposed, achieving 6.8 ns minimum on-time at 10 MHz$f_{\text {sw}}$. A dual-MOS-switches bootstrap (DMSB) circuit is proposed to ensure that the bootstrap (BST) rail achieves saturation (>80%) at 10 MHz frequency by sensing$V_{\text {sw}}$and the low-side gate drive signal. To validate this work, a half-bridge GaN driver has been fabricated in a$0.5~\mu $m 80 V HV CMOS process and the active area is$1.44\times 1.42$mm2. The d$V$/d$t$immunity has been verified both in Buck converter and double pulse conditions, which is up to 46 V/ns at 60V Buck converter and 56 V/ns at 48 V double pulse topology. The proposed DMSB technique achieves a peak efficiency of 86.7% at 10 MHz for 12-to-5V conversion, representing a 6.7% improvement over the conventional approach.

A current-efficient and fast-transient p-type low-dropout regulator (LDO) for high-current load transient in mobile phone applications is presented in this article. A low-power Auxiliary-Path Push-Pull (AP3) buffer is employed to provide both high charging and discharging current for gate-capacitance (CgP) of power MOS, hence the undershoot and overshoot performance are optimized simultaneously; Meanwhile the auxiliary path of the buffer further accelerates the transient response. Moreover, the shaped-hybrid-bias circuit accurately control the upper and lower limits of EA’s bias current, by this, maximum LDO’s bandwidth is well controlled and keeps proper margin to the self-resonant frequency of off-chip capacitor, which guarantees good loop stability over wide load range. This circuit has been implemented in a 0.18-µm standard 5V CMOS process and occupies a silicon area of 400 × 250 µm2, where 5V devices with a 500-nm minimum channel length are used. With a 1-µF output cap and load steps between 0 A and 270 mA, with 300ns edge time, experimental results show that it features 19/14 mV of undershoot/overshoot at load transient

In this paper, a high-noise-immunity capacitive-coupled level shifter with digital noise blanker (DNB) is presented for GaN drivers. During and after$\text{d}V$/dt transitions, the DNB blanks the common mode noise induced by$\text{d}V$/dt and converts the differential mode noise due to mismatch effect to common mode noise. This enables high$\text{d}V$/dt immunity of 200V/ns and high mismatch tolerance not less than 15%. Moreover, a dynamic discharge control (DDC) circuit prevents coupling capacitor from charging the floating power rail within a wide negative$\text{d}V$/dt transition range and achieves fast reset for high frequency operation. High speed, low power consumption and down to −5V negative floating power rail tolerance are also achieved. The proposed level shifter is fabricated in a 0.5-$\mu \text{m}$BCD process and occupies an active chip area of 0.051mm2. Experimental results confirm that the proposed level shifter works at 50V 50MHz, achieving power consumption of 27.3pJ/transition and 1.26ns average delay with a small figure of merit (5.5(pJ$\cdot $ns)/($\mu \text{m}^{3}\cdot \text{V}$)). The effect of the DDC is confirmed within negative$\text{d}V$/dt transition range of −5V/ns$\sim -50\text{V}$/ns.

This paper presents an anti-overcharged high-dV/dt-immunity capacitive level shifter with dynamic discharge control (DDC) for half-bridge GaN driver. The DDC prevents overcharge of the floating power supply capacitor during high negative dV/dt transitions and is suitable for a wide variation range of negative dV/dt transitions of floating power supply. Moreover, a fault-logic blanking block is introduced to guarantee the robust of output logic during ultra-high dV/dt transitions. The proposed Level shifter is fabricated in a 0.18μm BCD process and occupies an active chip area of 0.034mm2. Simulation results demonstrate that the propagation delay is less than 0.8ns at 50V level shifting and keeps almost constant when the floating ground ranges from -3V to 50V. The positive dV/dt immunity is 300V/ns. The negative dV/dt is 170V/ns under the condition that the level shifting capacitor does not discharge to floating power supply.