In the design of multi-stage operational amplifiers (Op-Amps), pole-zero (PZ) analysis lies at the core of whole design innovation for compensation. This paper proposes a signal-path recognition method to help with the auto-generation of readable analytical PZ expressions from a circuit netlist. Prior symbolic PZ extraction methods have limitations in either requiring numerical references or yielding insufficiently compactness after simplification. The proposed method circumvents these limitations via a two-phase process: a topology simplification phase and a term simplification phase. In the topology simplification phase, signal paths of a multi-stage Op-Amp are detected via programmable routines, capturing the main amplification stages and frequency compensation paths, based on which the transfer function and PZs can be generated. In the term simplification phase, we propose a method that only makes reference to the magnitude orders of terms by assuming elementary device parameter orders based on a technology file. Sixteen test cases featuring varied compensation strategies are employed to demonstrate the applicability of this research. Our implementation delivers a fully automated netlist-to-PZ workflow, which can generate informative PZ expressions in compact and readable forms within minutes, offering useful insights to the circuit designer.

Ferroelectric random access memory (FeRAM) is a promising candidate to further dynamic random access memory (DRAM) scaling. However, the design of the FeRAM bit cell is nontrivial as the ferroelectric device model is not well supported by EDA tools. Modern integrated circuit design heavily depends on circuit-level SPICE simulators that integrate compact device models through modified nodal analysis (MNA) representation. This paper presents a novel MNA-based SPICE simulation method for ferroelectric device models, targeted at the design space exploration of FeRAM bitcells. Furthermore, this paper provides a co-design procedure for FeRAM bitcells and sense amplifiers via a comprehensive case study.

Electromigration (EM) is one of the major concerns in the reliability analysis of very large-scale integration (VLSI) systems due to the continuous technology scaling. Accurately predicting the time-to-failure of integrated circuits (ICs) becomes increasingly important for modern IC design. However, traditional methods are often not sufficiently accurate, leading to undesirable over-design especially in advanced technology nodes. In this article, we propose an approach using multilayer perceptrons (MLPs) to compute stress evolution in the interconnect trees during the void nucleation phase. The availability of a customized trial function for neural network training holds the promise of finding dynamic mesh-free stress evolution on complex interconnect trees under time-varying temperatures. Specifically, we formulate a new objective function considering the EM-induced coupled partial differential equations (PDEs), boundary conditions (BCs), and initial conditions to enforce the physics-based constraints in the spatial–temporal domain. The proposed model avoids meshing and reduces temporal iterations compared with conventional numerical approaches like finite element method. Numerical results confirm its advantages on accuracy and computational performance.

An analog memristor crossbar-based Lyapunov equation solver is proposed in this article. It is an extension of memristor crossbar linear equation solver, but taking into account of the regularity with Lyapunov equation in the organization of crossbar. Nonideal effects due to co-design with CMOS analog circuits are studied in detail. Verification using a Verilog-AMS tool is performed to justify that with proper scaling on the memristor conductance values and other circuit signals, the solution quality of Lyapunov matrix equation can be improved.

In this paper a block circuit elimination method is proposed for realizable reduction of resistor-capacitor-inductor (RCL) networks. It is an extension of a recently published realizable RC reduction method, called HD-TICER (high-dimensional time-constant equilibration reduction), to reduction of multi-port RCL networks. A modified nodal analysis (MNA) formulation is adopted in a setting for dealing with the inductive elements, which is suited for developing a realizable high-dimensional reduction scheme. A new matrix-based method is presented to establish the basic computation scheme, which seems more intuitive than the previously employed driving point impedance (DPI) method. Furthermore, a pole-zero based low-order moment matching method is introduced for the purpose of circuit recovery after reduction. The main advantages of the proposed reduction method include: 1) an intuition-based topological formulation and reduction computation method, 2) a natural port preserving reduction method, and 3) an easy-to-implement circuit recovery procedure. Experimental numerical implementation has validated the effectiveness of the proposed reduction method. Comparison to other existing methods further highlights multiple benefits of this new circuit reduction method.

Despite the extraordinary applicative potentiality that dynamic graph inference may entail, its practical-physical implementation has been a topic seldom explored in literature. Although graph inference through neural networks has received plenty of algorithmic innovation, its transfer to the physical world has not found similar development. This is understandable since the most preeminent Euclidean acceleration techniques from CNN have little implication in the non-Euclidean nature of relational graphs. Instead of coping with the challenges arising from forcing naturally sparse structures into more inflexible stochastic arrangements, in DRAGON, we embrace this characteristic in order to promote acceleration. Inspired by high-performance computing approaches like Parallel Multi-moth Flame Optimization for Link Prediction (PMFO-LP), we propose and implement a novel efficient architecture, capable of producing similar speed-up and performance than baseline but at a fraction of its hardware requirements and power consumption. We leverage the hidden parallelistic capacity of our previously developed static graph convolutional processor ACE-GCN and expanded it with RNN structures, allowing the deployment of a multi-processing network referenced around a common pool of proximity-based centroids. Experimental results demonstrate outstanding acceleration. In comparison with the fastest CPU-based software implementation available in the literature, DRAGON has achieved roughly 191× speed-up. Under the largest configuration and dataset, DRAGON was also able to overtake a more power-hungry PMFO-LP by almost 1.59× in speed, and at around 89.59% in power efficiency. More importantly than raw acceleration, we demonstrate the unique functional qualities of our approach as a flexible and fault-tolerant solution that makes it an interesting alternative for an anthology of applicative scenarios.

As a brain-inspired artificial neural network computational model, a recurrent spiking neural network is composed of biologically plausible spiking neurons, which has taken on increasing importance in this study field mainly include complex network structure and implicit nonlinear mechanism. The paper presents a learning rule with spike weight for recurrent spiking neural networks, allowing for real-time communication system of complex spatiotemporal spike trains simulating organisms. First, a context layer with connectivity through copying the hidden layer between the input layer and the output layer is provided. The total error of the network for learning spike train patterns is then introduced, as well as a rule of spike weight based on different phases of spikes. Furthermore, the proposed supervised learning rule defines the learning process for synaptic weights in all layers based on the power-up of weighted spikes to transmit more information. In addition, the learning algorithm has been successfully tested and evaluated for major factors, such as different lengths and frequencies for desired output spike trains, demonstrating that high precision learning is possible even with limited iterative resources. Finally, an analysis of the recurrent layer parameters is conducted, including neuron number and connectivity degree.

Since the memristor emerged as a programmable analog storage device, it has stimulated research on the design of analog/mixed-signal circuits with the memristor as the enabler of in-memory computation. Due to the difficulty in evaluating the circuit-level nonidealities of both memristors and CMOS devices, SPICE-accuracy simulation tools are necessary for perfecting the art of neuromorphic analog/mixed-signal circuit design. This article is dedicated to a native SPICE implementation of the memristor device models published in the open literature and develops case studies of applying such a circuit simulation with MOSFET models to study how device-level imperfections can make adversarial effects on the analog circuits that implement neuromorphic analog signal processing. Methods on memristor stamping in the framework of modified nodal analysis formulation are presented, and implementation results are reported. Furthermore, functional simulations on neuromorphic signal processing circuits including memristors and CMOS devices are carried out to validate the effectiveness of the native SPICE implementation of memristor models from the perspectives of simulation accuracy, efficiency, and convergence for large-scale simulation tasks.

The TICER (TIme-Constant Equilibration Reduction) algorithm is a well-known resistor-capacitor (RC) network reduction algorithm. It finds wide applications in integrated circuit post-layout simulation tools. However, the original algorithm is one-dimensional in that each step eliminates one circuit node to obtain an approximately equivalent circuit by connecting additional elements to the neighboring nodes after each elimination. This work extends the TICER algorithm to its high-dimensional version in the sense that each step eliminates a subcircuit as a whole to obtain an approximately equivalent circuit, again by connecting extra elements to the neighboring nodes after each elimination. In practice the high-dimensional TICER (HD-TICER) algorithm finds many advantages over the classical one-dimensional TICER (1D-TICER) algorithm, which is a special case of the HD-TICER algorithm. An elegant mathematical derivation of the HD-TICER algorithm is provided by applying the notion of driving point impedance (DPI). The advantages of the HD-TICER algorithm are demonstrated by application to reductions of some purely resistive networks and RC networks. An approximate time constant estimation method is also provided for selection of a subblock circuit to eliminate.

ACE-GCN is a fast and resource/energy-efficient FPGA accelerator for graph convolutional embedding under data-driven and in-place processing conditions. Our accelerator exploits the inherent power law distribution and high sparsity commonly exhibited by real-world graphs datasets. Contrary to other hardware implementations of GCN, on which traditional optimization techniques are employed to bypass the problem of dataset sparsity, our architecture is designed to take advantage of this very same situation. We propose and implement an innovative acceleration approach supported by our “implicit-processing-by-association” concept, in conjunction with a dataset-customized convolutional operator. The computational relief and consequential acceleration effect arise from the possibility of replacing rather complex convolutional operations for a faster embedding result estimation. Based on a computationally inexpensive and super-expedited similarity calculation, our accelerator is able to decide from the automatic embedding estimation or the unavoidable direct convolution operation. Evaluations demonstrate that our approach presents excellent applicability and competitive acceleration value. Depending on the dataset and efficiency level at the target, between 23× and 4,930× PyG baseline, coming close to AWB-GCN by 46% to 81% on smaller datasets and noticeable surpassing AWB-GCN for larger datasets and with controllable accuracy loss levels. We further demonstrate the unique hardware optimization characteristics of our approach and discuss its multi-processing potentiality.

An automatic stage-form circuit reduction method for multistage operational amplifiers (opamps) is proposed. A tool based on this method can reduce a multistage opamp into a condensed stage-form macromodel, from which design equations can be generated automatically by another existing symbolic program. The proposed model generation method is fully symbolic; namely, it does not make reference to any numerical device values with a circuit, hence it does not require circuit biasing and sizing at an early design stage. The parameters coming with the generated models are dominant-effect approximation of the stage-related characteristics of the original circuits and thus are visually readable for design reasoning. Compensations in the original circuits are extracted automatically and reserved in the macromodel circuits. The user of this tool is only required to input the circuit stage information by identifying several key devices in the original circuits. As design equations can also be automatically generated from stage-form macromodels by a purely symbolic method, the proposed model generation method completes the path from a transistor-level opamp circuit to its characteristic design equations in a completely formal way. Examples are provided to demonstrate the effectiveness of the proposed model generation method, and numerical validation is further carried out to verify that the reduced symbolic models can successfully capture the key circuit behavior in the frequency domain for multistage opamps.

This paper addresses the problem of automatic analytical pole-zero (PZ) extraction for multistage operational amplifiers (opamps) with frequency compensation. Traditional methods mainly rely on numerical reference to derive approximate PZ expressions without incorporating any design knowledge. Such methods suffer from bad interpretability of the auto-generated results. This paper takes a topological approach and attempts to advocate that certain form of design knowledge can be incorporated in the symbolic term selection process for PZ generation. The generation engine selects the dominant terms by a formal inspection on the token patterns that are correlated to gain factors and compensation elements. Since the gain factors and compensation elements of an opamp are pertinent to the topological details of a circuit, the proposed PZ extraction method is closer to design conception than other numerical reference-based methods. Consequently, the generated pole/zero results are better interpretable. Application to a class of multistage opamps with a variety of compensation structures demonstrates that the proposed method is effective and can match human-derived results.

In the field of analog integrated circuit (IC) design, small-signal macromodels play indispensable roles for developing design insight and sizing reference. However, the subject of automatically generating symbolic low-order macromodels in human readable circuit form has not been well studied. Traditionally, work has been published on reducing full-scale symbolic transfer functions to simpler forms but without the guarantee of interpretability. On the other hand, methodologies developed for interconnect circuits (mainly resistor-capacitor-inductor (RCL) networks) are not suitable for analog ICs. In this work, a topological reduction method is introduced that is able to automatically generate interpretable macromodel circuits in symbolic form; that is, the circuit elements in the compact model maintain analytical relations of the parameters of the original full circuit. This type of symbolic macromodel has several benefits that other traditional modeling methods do not offer: First, reusability, namely that designer need not repeatedly generate macromodels for the same circuit even it is re-sized or re-biased; second, interpretability, namely a designer may directly identify circuit parameters (in the original circuit) that are closely related to the dominant frequency characteristics, such as dc gain, gain/phase margins, and dominant poles/zeros. The effectiveness and computational efficiency of the proposed method have been validated by several operational amplifier (opamp) circuit examples.

Lower upper (LU) factorization for sparse matrices is the most important computing step for circuit simulation problems. However, parallelizing LU factorization on the graphic processing units (GPUs) turns out to be a difficult problem due to intrinsic data dependence and irregular memory access, which diminish GPU computing power. In this paper, we propose a new sparse LU solver on GPUs for circuit simulation and more general scientific computing. The new method, which is called GPU accelerated LU factorization (GLU) solver (for GPU LU), is based on a hybrid right-looking LU factorization algorithm for sparse matrices. We show that more concurrency can be exploited in the right-looking method than the left-looking method, which is more popular for circuit analysis, on GPU platforms. At the same time, the GLU also preserves the benefit of column-based left-looking LU method, such as symbolic analysis and columnlevel concurrency. We show that the resulting new parallel GPU LU solver allows the parallelization of all three loops in the LU factorization on GPUs. While in contrast, the existing GPU-based left-looking LU factorization approach can only allow parallelization of two loops. Experimental results show that the proposed GLU solver can deliver 5.71χ and 1.46x speedup over the single-threaded and the 16-threaded PARDISO solvers, respectively, 19.56x speedup over the KLU solver, 47.13x over the UMFPACK solver, and 1.47x speedup over a recently proposed GPU-based left-looking LU solver on the set of typical circuit matrices from the University of Florida (UFL) sparse matrix collection. Furthermore, we also compare the proposed GLU solver on a set of general matrices from the UFL, GLU achieves 6.38x and 1.12x speedup over the singlethreaded and the 16-threaded PARDISO solvers, respectively, 39.39x speedup over the KLU solver, 24.04x over the UMFPACK solver, and 2.35x speedup over the same GPU-based left-looking LU solver. In addition, comparison on self-generated RLC mesh networks shows a similar trend, which further validates the advantage of the proposed method over the existing sparse LU solvers.

This paper introduces an educational tool and its implementation for automatically generating symbolic network functions of analog small-signal circuits. This tool has the following features: graphical schematic input, automatic generation of transfer function formula in clean s-expanded form, and dynamic linkage between symbols in formula and the selected elements in circuit. The last feature is unique in this contribution in that it can help students easily receive design insights. The details on implementing these key features are presented together with an illustrative example.

Symbolically generated network functions for an analog integrated circuit are complicated in general. For this reason a variety of simplification methods have been proposed in the literature. In this work a novel topology-based symbolic simplification method is proposed, which is capable of generating a simplified symbolic network function together with a simplified small-signal circuit. The technique is developed by applying the recently proposed graph-pair decision diagram (GPDD) algorithm that generates a symbolic network function stored in a binary decision diagram (BDD). Two types of element elimination can directly be operated on such a GPDD data structure. The performance variation by eliminating each symbol from the original circuit is assessed by the means of two monitored response metrics (dc gain and phase margin). After sorting the performance loss, those circuit elements with less performance loss are eliminated, resulting in a reduced GPDD which is automatically a simplified network function. A simplified small-signal circuit is available simultaneously after reduction. Applications to two operational amplifier examples confirm the effectiveness of the proposed methodology.

A symbolic macromodel for slew and settling characterization of fully differential switched-capacitor (SC) integrators is proposed in this work. This model is intended for fast behavioral simulation of data converters in the time-domain. The main advantages of the proposed model are: 1) it can be created automatically without the need of running a transient simulation; 2) it is fully composed of circuit elements that can be simulated by SPICE or MATLAB; 3) it is created in symbolic form so that adjustment of the transistor-level circuit is directly reflected in the macromodel without the need of remodeling. The proposed modeling methodology is validated by applying to SC integrators implemented by two different operational amplifiers. The step response waveforms of the integrator model have good agreement to the transistor-level simulation results with a speedup of about 20x.

Signal-to-noise ratio (SNR) is an important design metric for switched-capacitor sigma-delta modulators (SC-SDMs). In an automatic synthesis environment, fast SNR computation is of paramount importance. So far the main SNR computation method has been behavioral simulation. Other less accurate methods are based on empirical formulas. These methods could not contribute too much to the enhancement of synthesis efficiency. In this work a highly efficient and purely symbolic SNR computation method is proposed. The difficulty in the computation of noise power (requiring integration of a rational function) is overcome by Taylor polynomial approximation. Together with a symbolic loop-transfer analysis tool, the SNR can be computed fully symbolically. This novel computation method is applied to variational SC-SDM analysis. The effectiveness and efficiency are compared to behavioral Monte Carlo simulation results.

It is unknown to perform efficient PLL system-level verification with consideration of jitter induced by substrate or power-supply noise. With the consideration of nonlinear phase noise macromodel, this paper introduces a forward reachability analysis with stable backward correction for PLL system-level verification with jitter. By refining initial state of PLL through backward correction, one can perform an efficient PLL verification to automatically adjust the locking range with consideration of environmental noise induced jitter. Moreover, to overcome the unstable nature during backward correction, a stability calibration is introduced in this paper to limit error. To validate our method, the proposed approach is applied to verify a number of PLL designs including single-LC or coupled-LC oscillators described by system-level behavioral model with jitter. Experimental results show that our forward reachability analysis with backward correction can succeed in reaching the adjusted locking range by correcting initial states in presence of environmental noise induced jitter.

Dynamic stability margin of SRAM is largely suppressed at nano-scale due to not only dynamic noise but also process variation. A novel dynamic stability verification is developed in this paper based on analog reachability analysis for checking SRAM failure. In the presence of mismatch such as threshold voltage variation of all transistors, zonotope-based reachability analysis is deployed to efficiently verify SRAM failure at transistor level. The threshold voltage variation is considered by the modified input range of SRAM. As such, the suppressed stability margin and further failure region can be verified by performing a time-evolved reachability analysis with formed zonotope to distinguish safe and failure regions. One can perform efficient verification of the SRAM dynamic stability without repeated yet time-consuming Monte-Carlo simulations considering variations from all transistors. As demonstrated by numerical experiment results, the developed reachability analysis can accurately verify the SRAM dynamic stability under threshold voltage variations from all transistors. Speedup of more than 400x in runtime can be achieved over the Monte Carlo approach of 500 samples with the similar accuracy.

Symbolic circuit analysis is concerned with analytical construction of circuit response in the frequency (or time) domain, for which an efficient data structure is required. Recent research has justified that the binary decision diagram (BDD) is a superior data structure with the following distinguishing feature: a large number of product terms can be compactly represented by a BDD, on which numerical computations and analytical deductions can be performed directly. Using BDD for symbolic circuit analysis requires an efficient method for construction. In this paper, a graph-based construction method, called graph-pair decision diagram (GPDD), is developed. Given a small-signal circuit, a pair of graphs representing the circuit is created, from which a GPDD is constructed by successively reducing the graph pair. The GPDD algorithm, which generates cancellation-free symbolic terms, differs from the existing determinant decision diagram (DDD) algorithm. Detailed theory and implementable algorithms for the GPDD construction are developed, and a runtime performance comparison to DDD is made. It is demonstrated that the runtime performance using GPDD is comparable to that of DDD in terms of time and memory complexity for exact symbolic analysis, although the GPDD algorithm has to generate a much larger number of symbolic product terms.

In this article, we propose a new performance bound analysis of analog circuits considering process variations. We model the variations of component values as intervals measured from tested chips and manufacture processes. The new method first applies a graph-based analysis approach to generate the symbolic transfer function of a linear(ized) analog circuit. Then the frequency response bounds (maximum and minimum) are obtained by performing nonlinear constrained optimization in which magnitude or phase of the transfer function is the objective function to be optimized subject to the ranges of process variational parameters. The response bounds given by the optimization-based method are very accurate and do not have the over-conservativeness issues of existing methods. Based on the frequency-domain bounds, we further develop a method to calculate the time-domain response bounds for any arbitrary input stimulus. Experimental results from several analog benchmark circuits show that the proposed method gives the correct bounds verified by Monte Carlo analysis while it delivers one order of magnitude speedup over Monte Carlo for both frequency-domain and time-domain bound analyses. We also show analog circuit yield analysis as an application of the frequency-domain variational bound analysis.

The shrinking technology feature size and dense large-scale integration make process variation a challenging issue directly confronting the latest design automation tools. Process variation causes severe variation in interconnect networks, including very large-scale integrated interconnect structures, such as clock trees, clock mesh, power-ground networks, and other wiring structures in 3-D integrated circuits. The traditional moment computation techniques are only partly useful for analyzing such variational problems, however, their computational efficiency cannot meet the quickly rising needs, such as statistical analysis. This paper presents a novel symbolic moment calculator (SMC) for variational interconnect analysis. The moment calculator is constructed in a regular data structure that incorporates binary decision diagrams for data storage and computation. Given an interconnect circuit, such a computation diagram has to be constructed only once and can be repeatedly invoked for computation of moments with varying parameter values. Also, the SMC is friendly to interconnect synthesis in that it can be incrementally modified according to the modifications made to the circuit structure. Applications of the SMC for fast moment computation, sensitivity analysis, and statistical timing analysis are addressed. Significant efficiency is demonstrated comparing to other existing methods.

In this paper, we propose a new time-domain performance bound analysis method for analog circuits considering process variations. The proposed method, called TIDBA, consists of several steps to compute the bound performances in time domain. First the performance bound in frequency domain is computed for a linearized analog circuits by an variational symbolic analysis method and the Kharitonov's functions. Then the time domain performance bound is computed via a new general-signal transient bound analysis method. The new algorithm can give transient lower bound and upper bound of the performance variations affected analog circuits accurately and reliably. Experimental results from two industry benchmark circuits show that TIDBA gives the correct bounds for the Monte Carlo analysis while it delivers one order of magnitude speedup over the Monte Carlo method.

Parallel to algebraic methods, graphical circuit analysis methods have the advantage of cancellation-free. This paper proposes a graph reduction method for hierarchical symbolic circuit analysis by applying a binary decision diagram (BDD) for data sharing. This method is extended from the Graph-Pair Decision Diagram (GPDD) method which was developed for two-port dependent sources. New graph construction rules for multiple-port dependent sources are introduced, with which large analog circuits can be analyzed hierarchically. The new hierarchical method guarantees the cancellation-free property at each layer of hierarchy. The BDD-based hierarchical analysis method can greatly reduce the analysis complexity of the entire circuit, while the software construction and circuit partition remain easy. The new method is compared to the algebraic hierarchical method based on DDD (Determinant Decision Diagram) which does not have the cancellation-free property. Comparable performance can be achieved with the new method which has the extra cancellation-free property.

Passivity is an important property of circuits and systems to guarantee stable global simulation. Nonetheless, nonpassive models may result from passive underlying structures due to numerical or measurement error/inaccuracy. A postprocessing passivity enforcement algorithm is therefore desirable to perturb the model to be passive under a controlled error. However, previous literature only reports such passivity enforcement algorithms for pole-residue models and regular systems (RSs). In this paper, passivity enforcement algorithms for descriptor systems (DSs, a superset of RSs) with possibly singular direct term (specifically,D+DTorI-DDT) are proposed. The proposed algorithms cover all kinds of state-space models (RSs or DSs, with direct terms being singular or nonsingular, in the immittance or scattering representation) and thus have a much wider application scope than existing algorithms. The passivity enforcement is reduced to two standard optimization problems that can be solved efficiently. The objective functions in both optimization problems are the error functions, hence perturbed models with adequate accuracy can be obtained. Numerical examples then verify the efficiency and robustness of the proposed algorithms.

Linearized small-signal transistor models share the common circuit structure but may take different parameter values in the ac analysis of an analog circuit simulator. This property can be utilized for symbolic circuit analysis. This paper proposes to use a symbolic stamp for all device models in the same circuit for hierarchical symbolic analysis. Two levels of binary decision diagrams (BDDs) are used for maximum data sharing, one for the symbolic device stamp and the other for modified nodal analysis. The symbolic transadmittances of the device stamp share one BDD for storage saving. The modified nodal analysis (MNA) matrix formulated using symbolic stamp is of much lower dimension, hence it can be solved by a determinant decision diagram (DDD) with significantly reduced complexity. A circuit simulator is implemented based on the proposed partitioning architecture. It is able to analyze an op-amp circuit containing 44 MOS transistors exactly for the first time.

In this paper, we propose a new performance bound analysis of analog circuits considering process variations. We model the variations of component values as intervals measured from tested chip and manufacture processes. The new method applies a graph-based symbolic analysis and affine interval arithmetic to derive the variational transfer functions of analog circuits (linearized) with variational coefficients in forms of intervals. Then the frequency response bounds (maximum and minimum) are obtained by performing analysis of a finite number of transfer functions given by the Kharitonov's polynomial functions. We show that symbolic de-cancellation is critical for the affine interval analysis. The response bound given by the Kharitonov's functions are conservative given the correlations among coefficient intervals in transfer functions. Experimental results demonstrate the effectiveness of the proposed compared to the Monte Carlo method.

Recently significant research progress has been made toward the exact computation of symbolic transfer functions for large analog networks containing over 40 MOS transistors. A successful application of such a computation method for analog design requires an efficient method for ac-sensitivity analysis. It is addressed in this paper that the sensitivity of a transfer function to device sizes (or RC values) can be computed efficiently based on a hierarchical framework. It is demonstrated via examples that the ac-sensitivity can be used for improving the amplifier design metrics such as phase margin or pole/zero placement, etc.

Mesh circuits typically consist of many resistive links and many sources. Accurate analysis of massive mesh networks is demanding in the current integrated circuit design practice, yet their computation confronts numerous challenges. When variation is considered, mesh analysis becomes a much harder task. This paper proposes a symbolic computation technique that can be applied to the moment-based analysis of mesh networks with multiple sources. The variation issues are easily taken care of by a structured computation mechanism, which can naturally facilitate sensitivity based analysis. Applications are addressed by applying the computation technique to a set of mesh circuits with varying sizes.

Determinant decision diagram (DDD) uses a Binary Decision Diagram (BDD) to represent the Laplace expansion of a determinant. It is used as the core computation engine in some modern symbolic circuit simulators. The traditional implementations rely on a BDD package for the common-data sharing operations in which symbol ordering plays an essential role. This paper proposes a simple implementation method which does not use any BDD package. Sharing is implemented by directly hashing minors, while the requirement on symbol ordering is weakened to an expansion ordering. The basic mechanism used is a natural formulation of layered expansion which is analogous to manual expansion of a determinant, hence it is easily understood. The simplified DDD construction method not only makes the DDD implementation straightforward, but also results in greater efficiency. A simulator developed based on this new method solves the μa725 op-amp circuit in a few seconds by flat expansion.

This paper presents a symbolic AC sensitivity analysis technique using a graph-reduction based symbolic simulator GRASS. Symbolic sum-of-products are derived from a graph reduction process and represented by a binary decision diagram. The GRASS simulator maintains a one-to-one correspondence between the circuit parameters and the simulator symbols, with which differentiating the frequency response with respect to any circuit parameter becomes straightforward. The implementation details of symbolic AC sensitivity are presented and the potential applications are demonstrated.

A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed graph reduction process and a recursive sign determination algorithm. A symbolic analog circuit simulator is developed using a combination of these techniques. The simulator is able to analyze large analog circuits in the frequency domain. Experimental results are reported.

Symbolic model order reduction (SMOR) is a macromodeling technique that generates reduced-order models while retaining the parameters in the original models. Such symbolic reduced-order models can be repeatedly simulated with a greater efficiency for varying model parameters. Although the model-order-reduction concept has been extensively developed in literature and widely applied in a variety of problems, model order reduction from a symbolic perspective has not been well studied. Several methods developed in this paper include symbol isolation, nominal projection, and first-order approximation. These methods can be applied to models having only a few parametric elements and to models having many symbolic elements. Of special practical interest are models that have slightly varying parameters such as process related variations, for which efficient reduction procedures can be developed. Each technique proposed in this paper has been tested by circuit examples. Experiments show that the proposed methods are efficient and effective for many circuit problems

Efficient dc fault simulation of nonlinear analog circuits is addressed in this paper. Two techniques, one-step relaxation and adaptive simulation continuation, are proposed. By one-step relaxation, only one Newton-Raphson iteration is performed for each faulty circuit with the dc solution of the good circuit as the initial point, and the approximate solution is used for detecting the fault. The paper shows experimentally and justifies theoretically that approximate dc fault simulation by one-step relaxation can accomplish almost the same fault coverage as exact dc fault simulation. Exact dc fault simulation by adaptive simulation continuation is first to order faulty circuits based on the results of one-step relaxation, and then to use the solution of the previous faulty circuit as the initial point for the Newton-Raphson iteration of the next faulty circuit. Experiments on a set of 29 MCNC Circuit Simulation and Modeling Workshop benchmark circuits show that exact dc fault simulation by adaptive simulation continuation can achieve an average speedup of 4.4 and as high as 15 over traditional stand-alone fault simulation.