Demo Data from EDBT 2026 / reviewers in the wild / expert
Luc Séméria
dblp:52/4949
· DBLP profile ↗
6ranked-venue papers
6as first author
0since 2021 · last 2002
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 6 · 6 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 87% Processor architecture and microarchitecture · 13% | |
| Software engineering, system software, and programming languages
1 paper |
Program analysis · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
high-level synthesis |
0.1 | 2 | 2002 | RTL c-based methodology for designing and verifying a multi-threaded processor · DAC 2002 Resolution, optimization, and encoding of pointer variables for thebehavioral synthesis from C · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2001 |
Electronic design automation › hardware verification and test › formal verification
equivalence checking |
0.0 | 1 | 2002 | RTL c-based methodology for designing and verifying a multi-threaded processor · DAC 2002 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 2002 | RTL c-based methodology for designing and verifying a multi-threaded processor · DAC 2002 |
Program analysis › static analysis
pointer analysis |
0.0 | 1 | 2001 | Resolution, optimization, and encoding of pointer variables for thebehavioral synthesis from C · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2001 |
Processor architecture and microarchitecture
multithreading |
0.0 | 1 | 2002 | RTL c-based methodology for designing and verifying a multi-threaded processor · DAC 2002 |
Processor architecture and microarchitecture › multithreading
simultaneous multithreading |
0.0 | 1 | 2002 | RTL c-based methodology for designing and verifying a multi-threaded processor · DAC 2002 |
Methods — techniques the papers use, named apart from their topics
pointer analysis · 0.1heuristic encoding · 0.1compiler optimization · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2002 | RTL c-based methodology for designing and verifying a multi-threaded processorabstractA RTL C-Based design and verification methodology is presented with enabled the successful high speed validation of a 7 million gate simultaneous multi-threaded (SMT) network processor. The methodology is centered on statically scheduled C-based coding style, C to HDL translation, and a novel RTL-C to RTL-Verilog equivalence checking flow. It leverages improved simulation performance combined with static techniques to reduce the amount of RTL-Verilog and gate-level verification required during development. Luc Séméria, Renu Mehra, Barry M. Pangrle, Arjuna Ekanayake, Andrew Seawright, Daniel Ng |
DAC | 1 |
| 2001 | Resolution, optimization, and encoding of pointer variables for thebehavioral synthesis from CabstractAs designers may model mixed hardware-software systems using a subset of C or C++, we present SpC, a solution to synthesize and optimize hardware C models with pointers. In hardware, a pointer is not only the address of data in memory, but it may also reference data mapped to registers, ports, or wires. Pointer analysis is used to find the set of locations each pointer may reference in a program at compile time. In this paper, we address the problem of synthesizing and optimizing pointers to multiple variables or array elements. The value of the pointers are encoded and branching statements are used to dynamically access data referenced by pointers. A heuristic is used to efficiently encode the values of the pointers. Compiler techniques are also used to reduce storage before loads and stores. An implementation using the SUIF framework (Wilson et al., 1994; SUIF Compiler Framework) is presented, followed by some case studies and experimental results. Luc Séméria, Giovanni De Micheli |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2001 | Synthesis of hardware models in C with pointers and complex data structuresabstractOne of the greatest challenges in a C/C++-based design methodology is efficiently mapping C/C++ models into hardware. Many networking and multimedia applications implemented in hardware or mixed hardware/software systems now use complex data structures stored in multiple memories, so many C/C++ features that were originally designed for software applications are now making their way into hardware. Such features include dynamic memory allocation and pointers for managing data. We present a solution for efficiently mapping arbitrary C code with pointers and malloc/free into hardware. Our solution, which fits current memory management methodologies, instantiates an application-specific hardware memory allocator coupled with a memory architecture. Our work also supports the resolution of pointers without restriction on the data structures. We present an implementation based on the SUIF framework along with case studies such as the realization of a video filter and an ATM segmentation engine. Luc Séméria, Koichi Sato, Giovanni De Micheli |
IEEE Trans. Very Large Scale Integr. Syst. | 1 |
| 2000 | Methodology for hardware/software co-verification in C/C++ (short paper)abstractIn this paper we present our C/C++-based design environment for hardware/software co-verification.Our approach is to use C/C++ to describe both hardware and software throughout the design flow.Our methodology supports the efficient mapping of C/ C++ functional descriptions directly into hardware and software.The advantages of a C/C++-based flow from the verification point of view are presented.The use of C/C++ to model all parts of the system provides great flexibility and enables faster simulation compared to existing methodologies.We show how co-verification can be done efficiently and effectively at the various levels of abstraction, how coverification can be used to drive co-design through performance estimation and give an example of implementation for the 8051 architecture. Luc Séméria, Abhijit Ghosh |
ASP-DAC | 1 |
| 2000 | Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from CabstractOne of the greatest challenges in C/C++-based design methodology is to efficiently map C/C++ models into hardware. Many of the networking and multimedia applications implemented in hardware or mixed hardware/software systems are making use of complex data structures stored in one or multiple memories. As a result, many of the C/C++ features which were originally designed for software applications are now making their way into hardware. Such features include dynamic memory allocation and pointers used to manage data. We present a solution for efficiently mapping arbitrary C code with pointers and malloc/free into hardware. Our solution fits current memory management methodologies. It consists of instantiating a hardware allocator tailored to an application and a memory architecture. Our work also supports the resolution of pointers without restriction on the data structures. An implementation using the SUIF framework is presented, followed by some case studies such as the realization of a video filter. Luc Séméria, Koichi Sato, Giovanni De Micheli |
DATE | 1 |
| 1998 | SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from Cabstractk designers may model tied software-hardware systems using a subset of C or C++, we prtient SpC, a solution to synth=ize and optimize a C model with pointers.In hardware, a pointer is not ody the address of data in memory, but it may *O reference mtitiple variablw mapped to registers, ports or wire.Pointer anrdysis is used to fid the point-to-set of each pointer in the program.b thii paper, we address the problem of synthesizing and optimizing pointers to multiple variablm and array elements.Temporary variablti are defined to optimize loads and stores by minimizing the number of live variabl=.The combinational logic can *O be reduced by encoding the pointers vdu=.A implementation using the SUE framework is presented, followed by some case studies such as the synthwis of a 2D ~CT. Luc Séméria, Giovanni De Micheli |
ICCAD | 1 |