The through silicon via (TSV) array plays the significant role of vertical electrical interconnection in the three-dimensional stacked integrated circuits. The TSV faults and the inter-TSV crosstalk are two issues that must be addressed for the effective and reliable transmission in TSV arrays. The forbidden transition free (FTF) and forbidden pattern free (FPF) crosstalk avoidance code (CAC) can suppress the crosstalk in TSV array, and the built-in self-diagnosis (BISD) and self-repair techniques are able to localize and repair the TSV faults, respectively. The BISD usually consumes a non-negligible amount of time in the diagnosis mode. So the periodic BISD schemes have a dilemma between the transmission performance and the efficiency of fault detection. The on-demand BISD schemes have been applied to address this issue. This paper proposes a new on-line BISD triggering scheme based on the CAC-compatible error detection code (EDC). The proposed scheme checks the data transmitted through the TSV array in the working mode. And the BISD is invoked in time only if the EDC codecs detect errors. Compared with the existing similar schemes, the proposed scheme does not degrade the crosstalk suppression effect of the FTF/FPF-CAC methods, and it achieves a better balance in terms of the fault detection ability and the hardware overhead.

The March test is a widely-applied test method for memory arrays. Nowadays, the advanced memory technologies keep introducing new types of defects, which bring diverse multi-operation fault models in turn. The automatic March sequence generation methods are preferred to avoid the inefficient manual design. Most previous methods generate the March sequences that cover limited types of faults and strongly depend on the specific characteristics of known faults. To address this issue, this work proposes MarchGen, a March sequence generation method for memory faults with arbitrary number of operations. Firstly, the fault hierarchies, reduced taxonomy and generic test conditions of 2-composite faults are analyzed. Then, the heuristic March sequence generation workflow is designed accordingly, which takes either fault models or test sequences as input. Three optimization strategies are utilized to improve the fault coverage of the generated March sequences and the generation time consumption. The evaluation results show that the proposed method has low dependence on fault types. The generated March sequences reach 100% fault coverage for any simple and 2-composite faults or test sequences, and the generation time is roughly linear with the size of input set.

Digital static random access memory-based in-memory computing (SRAM-IMC) is a promising computation paradigm to break the von-Neumann bottleneck. However, the IMC architectures also bring a series of challenges for testing, because of the circuit structures and operations that do not exist in the conventional memories. One of the challenges is the testing of evaluation circuits in the digital SRAM-IMC architectures, because the primary inputs (PIs) of the evaluation circuits cannot be directly accessed by the testers. Several test approaches such as the conventional logic built-in self-test (LBIST) modules, the indirect and the scan-chain-based test methods are proposed to address this issue. Nevertheless, these solutions suffer from the low test performance or the high area consumption. This work proposes a reconfigurable built-in self-test (BIST) scheme for the evaluation circuits. By reusing the IMC bitcells and operations, the proposed BIST scheme implements the separate pattern generation (PG) and response analysis (RA) processes. Furthermore, the diverse pattern generators, including the Fibonacci linear feedback shift register (LFSR) and weighted LFSR (WLFSR) with adjustable feedback polynomials and the cellular automata (CA), are realized to improve the test efficiency and fault coverage. The evaluation results show that the proposed BIST scheme has better test performance comparing with the indirect and the scan-chain-based test approaches. The proposed BIST scheme has comparable test performance, whereas it has much less area overhead comparing with the conventional LBIST schemes. Additionally, the proposed BIST scheme is testable and repairable.

Neuromorphic computing has endeavored a novel computing paradigm that entails a bio-inspired architecture to reproduce the remarkable functionalities of the human brain, such as massively parallel processing and extremely low-power consumption. However, those promising merits can be greatly canceled by the mismatched communication infrastructure in large-scale hardware implementation, in view of the vast degree of neural connectivity, the unstructured spike dataflow, and the unbalanced model workload assignment. In an effort to tackle those challenges, this work presents NeuroHexa, a network-on-chip (NoC) architecture intended for multi-core neuromorphic design. NeuroHexa adopts a customized intra-chip hexagonal topology, which can be further cascaded in 6 directions by either 2D or 3D chiplet integration. Designed in globally asynchronous, locally synchronous (GALS) methodology, a group of processing nodes can operate in independent work pace to further improve resource utilization. To satisfy the varied requirement of data reuse across the chip, NeuroHexa proposes a flexible multicast routing mechanism to best adapt to the model-defined dataflow. And under a specific congestion scenario, NeuroHexa can switch its routing algorithm between deterministic routing and fully adaptive routing modes. The presented NoC router is evaluated in 28nm CMOS, where we achieve the maximal throughput as 179.2Gbps, and the best energy efficiency as 4.872pJ/packet at the area overhead of 0.0226mm2.

Situated Question Answering (SQA) involves reasoning the question based on the scene context from the questioner's perspective, enabling potential applications in human-centered embodied intelligence. Previous works handle this task by data-driven methods, generating answers in a closed-set or open-ended manner without explicit reasoning. Therefore, these works are often trapped in dataset bias, overfitting, and interpretability challenges. Inspired by the reasoning process of humans, we propose a Human-Inspired SQA model (Hi-QA), the first embodied agent that leverages human-like skills to understand the scene and perform interpretable reasoning. Specifically, Hi-QA leverages a specialized perception tool to gather information from 3D scenes for the reasoning module to reason questions with Large Language Models. The reflection module amends invalid reasoning and builds methodology memory to learn problem-solving methods. The distillation module distills prototypical information about objects, supporting the agent with supplementary knowledge. Experiments on ScanQA and SQA3D datasets validate that Hi-QA achieves state-of-the-art performance and highlight that human-inspired design significantly boosts the model's interpretability and generalizability.

In order to achieve the brain-like advantages over conservative computers, previous neuromorphic researchers have stretched the hardware explorations of the hybrid artificial neural network (ANN) and spiking neural network (SNN) inference approaches, as well as the efficient bio-plausible and gradient-based SNN training mechanisms. However, a versatile accelerator for both ANN-SNN inference and training is little addressed. In this work, we introduce HyNITA, a neuromorphic processor that supports accelerating both inference and training tasks of hybrid ANN and SNN models. Regarding the similarity and distinction, a pair of working stages are distinguished and distributed to multiple simple cores. The accelerator optimizes the interchange dataflow in a scalable chip design, following a reconfigurable design methodology to integrate the involved equation calculations in the dynamic process of neurons. The evaluation results show it achieves an accuracy of 99.65% and 99.34% on training ANN MNIST and SNN N-MNIST datasets.

The X-ray security inspection aims to identify any restricted items to protect public safety. Due to the lack of focus on unsupervised learning in this field, using pre-trained models on natural images leads to suboptimal results in downstream tasks. Previous works would lose the relative positional relationships during the pre-training process, which is detrimental for X-ray images that lack texture and rely on shape. In this paper, we propose the jigsaw style MAE (J-MAE) to preserve the relative position information by shuffling the position encoding of visible patches. This forces the network to perform semantic reasoning to understand the shape and composition of X-ray objects. Meanwhile, we propose the Incremental Shuffling Module (ISM) and Permute Predicting Module (PPM) to make the training process more stable and accelerate convergence. Our proposed method has consistently outperformed other methods on three downstream X-ray security inspection datasets.

Embodied intelligence based on vision-language models aims to learn from interactions and derive general intelligence. However, existing generalized vision-language models cannot understand domain knowledge in home scenarios due to the lack of sweeping robot multimodal datasets. In this paper, we propose the first multimodal dataset for sweeping robots, called SweepMM. We create textual data such as room type, scene descriptions, and moving recommendations using various approaches including rule-based, manual-based, and off-the-shelf model-based methods. Based on this dataset, we fine-tune the first generative pretrained model for sweeping robots, called SweepGPM. This model enables human-robot dialogue and surpasses previous state-of-the-art methods by 0.8% in room type recognition, 0.4% in obstacle detection, and 8.0% in lost item search, demonstrating the potential of embodied intelligence in sweeping robots.

Model quantization finds success in simplifying model inference in practical applications. However, it predominantly focuses on CNNs and 2D ViT models, with limited attention given to quantizing 3D models. We pensively explore 3D model quantization challenges and discover similar numerical distributions of Softmax and LayerNorm between 3D and 2D models. Consequently, we apply the quantization algorithms FQ-ViT and I-ViT designed for 2D ViT models to 3D model quantization to address performance issues caused by uneven numerical distributions in Softmax and LayerNorm. Our research includes extensive experiments using transformer architectures and establishes benchmarks, demonstrating successful quantization of 3D multimodal model UNITR. Notably, our approach experiences a slight decrease compared to FP32 while outperforming other state-of-the-art models. For example, in the 3D object detection task on the nuScenes dataset, the 8 -bit UNITR (FQ-ViT) achieves impressive NDS and mAP scores of $73.0 \%$ and $70.0 \%$, surpassing the full precision BEVFusion model.

3D visual grounding is tasked with locating a specific object within a 3D scene, as described by a given textual reference. This task is challenging because it requires (1) the accurate recognition of various objects in a 3D scene and (2) the understanding of spatial relations in the description. However, current studies encounter difficulties in situations where multiple similar objects are present or when the descriptions involve intricate and abstract relations. In this paper, a novel, simple, and efficient Object-Centric Referring network, namely 3D-OCR, is presented to take high-quality semantic representation and deep relation modeling into account. Specifically, an offline Fine-grained Semantic Enhancement (FSE) module is designed to reinforce the object-centric semantic awareness with fine-grained high-quality object semantic representations. To achieve superior object-centric relation awareness, we propose a Deep Relation Modeling (DRM) module with the explicit and implicit relation self-attention module, enriching object features with relational context. Moreover, we utilize a vision-language contrastive loss to further improve the matching process between point cloud and language. Comprehensive experiments conducted on the challenging ScanRefer and Nr3D datasets corroborate the exceptional performance of our method, with an increase of +1.47% on ScanRefer and +1.2% on Nr3D.

This paper revisits the development of generative self-supervised learning in 2D images and 3D point clouds in autonomous driving. In 2D images, the pretext task has evolved from low-level to high-level features. Inspired by this, through explore model analysis, we find that the gap in weight distribution between self-supervised learning and supervised learning is substantial when employing only low-level features as the pretext task in 3D point clouds. Low-level features represented by PoInt Cloud reconsTruction are insUfficient to learn 3D REpresentations (dubbed PICTURE). To advance the development of pretext tasks, we propose a unified generative self-supervised framework. Firstly, high-level features are demonstrated to exhibit semantic consistency with downstream tasks. We utilize the high-level features as an additional pretext task to enhance the understanding of semantic information during the pre-training. Next, we propose inter-class and intra-class discrimination-guided masking (I2Mask) based on the attributes of the high-level features, adaptively setting the masking ratio for each superclass. On Waymo and nuScenes datasets, we achieve 75.13% mAP and 72.69% mAPH for 3D object detection, 79.4% mIoU for 3D semantic segmentation, and 18.4% mIoU for occupancy prediction. Extensive experiments have demonstrated the effectiveness and necessity of high-level features.

This paper proposes a novel hybrid-triggered electrostatic discharge (ESD) power clamp circuit. By co- optimizing the transient and static triggered paths, the proposed circuit can achieve transient response time over 6 times longer than that of traditional transient circuit in the same footprint, thus greatly improving area efficiency. The trigger circuit (TC) area of the proposed circuit reduces 50% compared to the baseline circuit. In addition, the circuit achieves high false- trigger immunity and low leakage current of 7 nA. The proposed circuit achieves adjustable transient response time to accommodate different ESD events with high flexibility. All the studied circuits are fabricated using a 28-nm CMOS process. To verify the proposed circuit, the simulation and test results are analyzed in detail for this paper.

Most of heterogeneous information network (HIN) based recommendation models are based on the user and item modeling with meta-paths. However, they always model users and items in isolation under each meta-path, which may lead to information extraction misled. In addition, they only consider structural features of HINs when modeling users and items during exploring HINs, which may lead to useful information for recommendation lost irreversibly. To address these problems, we propose a HIN based unified embedding model for recommendation, called HueRec. We assume there exist some common characteristics under different meta-paths for each user or item, and use data from all meta-paths to learn unified users’ and items’ representations. So the interrelation between meta-paths are utilized to alleviate the problems of data sparsity and noises on one meta-path. Different from existing models which first explore HINs then make recommendations, we combine these two parts into an end-to-end model to avoid useful information lost in initial phases. In addition, we embed all users, items and meta-paths into related latent spaces. Therefore, we can measure users’ preferences on meta-paths to improve the performances of personalized recommendation. Extensive experiments show HueRec consistently outperforms state-of-the-art methods.

Precise prediction of users' behavior is critical for users' satisfaction and platforms' benefit. A user's behavior heavily depends on the user's general preference and contextual information (current location, weather etc.). In this paper, we propose a succinct hierarchical framework named Hierarchical Hybrid Feature Model (HHFM). It combines users' general taste and diverse contextual information into a hybrid feature representation to profile users' dynamic preference w.r.t context. Meanwhile, we propose an n-way concatenation pooling strategy to capture the non-linear and complex inherent structures of real-world data, which were ignored by most existing methods like Factorization Machines. Conceptually, our model subsumes several existing methods when choosing proper concatenation and pooling strategies. Extensive experiments show our model consistently outperforms state-of-the-art methods on three real-world data sets.

This paper investigates the bigFET gate bias voltage in power-rail electrostatic discharge (ESD) clamp circuit for enhanced transient noise immunity. Based on a timed shutoff circuit, a resistor pair is employed to bias the bigFET gate voltage to different ratios of VDD. Through detailed investigations, an optimized bigFET gate bias scheme is proposed. With the optimized scheme, enhanced transient noise immunity of the investigated circuit is achieved. Besides, the optimized scheme can induce the channel and parasitic bipolar junction transistor parallel shunt paths in ESD events, which result in a lower on-resistance. Moreover, the optimized scheme is also validated in the high-threshold-voltage bigFET samples.

A digital-controlled silicon neuron is presented, which can achieve a multi-mode biologically plausible spike shape. The proposed circuit can mimics the behaviors of known kinds of excitatory and inhibitory cortical neurons, including regular spiking (RS), chattering (CH), intrinsic bursting (IB), fast spiking (FS), and low-threshold spiking (LTS). The circuit is capable of generating different spiking patterns through simple digital control, which makes the circuit configurable for a large-scale spiking neural network (SNN). Implemented in a 65-nm CMOS technology, the proposed circuit maintains a good robustness over process, voltage and temperature (PVT) variations.

A power-rail electrostatic discharge clamp circuit with transient and static hybrid-detection enhanced triggering is proposed in this work. By skillfully co-optimizing the driving paths of both transient and static detection networks, the proposed circuit achieves a clamp device transient response time over 2 times longer than its RC time constant, which endows the proposed circuit with both promoted area-efficiency and safe clamping behaviors. Besides, the proposed circuit effectively combines the advantages of transient and static ones with tiny leakage current penalties. All investigated circuits are fabricated in a 65-nm CMOS process using 1.2-V thin-oxide devices. Simulation and test results are discussed in detail in this work to validate the proposed circuit.

A highly compact and low power consumption neuromorphic circuit with digital control signals which achieves the functional properties of biological neuron and synapse is proposed in this paper. The excitatory or inhibitory synapse could convert pre-synaptic spikes to current to charge or discharge the neuron. During the presence of the post-synaptic current (PSC), the ring oscillator (RO) based neuron is capable of generating regular spiking (RS), intrinsically bursting (IB) or fast spiking (FS) behaviors, which are controlled by digital signals. Based in a 65-nm CMOS technology, the silicon area of the excitatory synapse, the inhibitory synapse and the neuron is only 6.8 μm2, 1.4 μm2and 20.8 μm2, respectively. It is beneficial to the increasing scale of neural networks. Moreover, the overall power consumption of the circuit is only 418 nW.

Summary We present a practical large universe hierarchical attribute‐based encryption (LU‐HABE) scheme, which supports monotone access structures. In our system, key generation centers (KGCs), any one in which is labeled by a unique identity, are organized as a hierarchical structure. Thus, all secret keys issued by the KGC contain 2 parts: the identity‐related one and the attribute‐related one. Once the data owner wants to encrypt his/her data, he/she needs to specify certain numbers of pairs according to his/her demand. The pair consists of an identity of a KGC and a policy of attributes managed by the corresponding KGC, eg, IDi and (Mi, ρi). If and only if an identity associated with user's secret key is equal to or is an ancestor of one of the identities appearing in ciphertext, and simultaneously a set of attributes belonging to the user satisfies the policy, the user can decrypt it successfully. Our scheme is proved to be selectively secure in the standard model under the modified “q‐type” assumption similar to the ones used in former works and is extended to support online/offline encryption. To show the efficiency of our construction, we implement our original scheme and the extended one in Charm. Analyses show that both of them are very practical.

This work presents a novel power-rail electrostatic discharge (ESD) clamp circuit for nanoscale applications. By skillfully incorporating transient and static ESD detection mechanisms into its detection circuit, the proposed circuit achieves a wide range of adjustable triggering voltage (Ft1) while maintaining low standby leakage current (Ileak). Besides, the proposed circuit achieves significantly-improved false-triggering immunity compared with the transient-triggered circuit. All investigated circuits are fabricated in a 65-nm CMOS process. Simulation and test results have both confirmed the superiority of the proposed circuit. In addition, the proposed circuit achieves similar triggering behaviors in both transmission line pulsing (TLP) and very fast TLP (VF-TLP) tests.

A wide operating range and fast locking delay-locked loop (DLL) based frequency quadrupler that includes an eight-phase-clock generator and an edge combiner is proposed. The eight-phase-clock generator is composed of a coarse-code generator, a fine-code generator and a digital controlled delay line, which uses four differential delay units to generate equally spaced eight-phase clocks. The coarse-code generator adopts a time-to-digital scheme to achieve short locking time and wide operating range. A fine-code digital-to-analog converter in the fine-code generator converts the fine codes to analog voltage for high precision. Moreover, the novel edge-combiner circuit combines the eight-phase clocks to x4 frequency output with 50% duty cycle ratio. Experimental results in a 65-nm CMOS process show this frequency multiplier can cover a frequency range from 320 MHz to 2.4 GHz and cost 5~40 cycles to finish locking.

This paper presents a 0.5-2GHz RF front-end with Series N-path Filter. With series 8-path filter applied, an ultimate rejection larger than 46 dB with 30 dB out-of-band rejection at 50 MHz offset is achieved. Dynamic power consumption is saved due to small filter switch size compared with parallel structures. Utilizing a tunable narrow band LNA in front of series N-path filter, 3rdharmonic rejection exceeding 54 dB with robust to process variation is realized. These techniques improve the front-end's adjacent and far-end frequency selectivity in RF domain, relaxing mixer's linearity design pressure. Implemented in 65 nm CMOS process, the frontend achieves a NF of 2.6-5.7 dB and maximum gain of 46-60 dB at 0.5-2 GHz, consuming 18-26 mW from 1.2 V voltage supply and occupies an area of 0.56 mm2.

A wide range delay-locked loop (DLL) based clock and data recovery (CDR) circuit including coarse and fine tune blocks is proposed in this paper. The coarse tune block adopts a time to digital converter and digital control delay line to widen the frequency capture range, reduce locking time and prevent the false locking problem. In the fine tune block, a novel phase detector combines the tasks of sampling and charge-pump using half rate clock. Starting-control circuit can ensure CDR takes full use of the delay range provided by voltage control delay line. Moreover, a fully analog DLL technique is applied to exploit the benefits of low skew and jitter performance. The simulation result shows the proposed CDR can cover a wide frequency range from 180.5Mbps to 8Gbps, while the peak-to-peak jitter of recovery clock is 2.7ps at 200Mbps and 1.06ps at 8Gbps. Fabricated in a 65nm CMOS process, this design dissipates 9.9mW and 22.9mW respectively at 200 Mbps and 8Gbps from a 1.2 V supply.

This paper presents a low TX noise transmitter with digital modulated power amplifier (DPA) for UHF RFID reader System-on-Chip. With I/Q digital signals directly modulated on DPA, the transmitter eliminates the pulse shaping filter, up-conversion mixer and power amplifier driver, which are dominant noise contributors in a conventional RFID transmitter. A switch-mode power amplifier cell is adopted in the DPA, which suppresses the amplitude noise in the TX chain. An LO signal buffer strategy is proposed to minimize uncorrelated phase noise which cannot be cancelled by self-cancellation in the RFID receiver. A low noise self-adaptive LDO is designed for lowering TX noise and stable output power. The transmitter achieves a TX noise density lower than -145dBc/Hz and provides a peak output power of 24 dBm with 48% drain efficiency when transmitting CW signal. Through pre-distortion, the transmitter can achieve a spectrum mask with -50 dBc for ACPR1, -62 dBc for ACPR2 and -65dBc for ACPR3. The proposed transmitter is fabricated in a standard 0.18-μm CMOS process with an area of 1000×640μm2.

The paper introduces a new monitoring circuit to quantify the change in performance of devices undergoing NBTI stress at 65nm technology node. The proposed solution consists of a pMOS device experiencing accelerated NBTI stress, a Capacitive Switch, Relaxation Oscillator structure, serving as a monitoring unit, which allows to dynamically track the NBTI-induced degradation with time. The circuit measures the change of the relaxation frequency which is attributed to the saturation current shift in pMOSFET due to NBTI stress. The proposed circuit with counting unit produces a digital output which makes it easier to collect. The capacitive relaxation oscillator modeling has been established and verified by the experiments. Meanwhile, the circuit is easily to be integrated with the digital logic system. Based on the device matrix, the effect of initial saturation current distribution and NBTI-induced time-dependent variability can also be obtained.

A 1.0-V, 50-mA capacitor-less low-dropout (LDO) voltage regulator with 100pF internal output capacitor for SoC applications is presented. The proposed LDO makes use of a bi-directional asymmetric buffer (BDAB), which provides a signal inversion feedback path and a signal non-inversion feedforward path with different magnitudes at the same time. The feedback path can perform frequency compensation and transient enhancement, while the feedforward path can improve the stability and increase the unit-gain frequency (UGF) by removing right-half-plane (RHP) zero. Simulation results show that the LDO has robust stability, high UGF (up to 1.7-MHz even at no-load), and excellent transient response performance. The overshoot and undershoot of the output voltages are less than 100-mV when the load step changes between 0 and 50-mA in 1-μs, the settling time is 2-μs, while the dropout voltage is 100-mV at full-load current.

A novel scheme is presented for achieving high performance low-dropout (LDO) voltage regulators under the constraint of low supply voltage. This scheme makes use of a frequency-dependent feedback factor (FDFF). The FDFF has simple circuit structure and frequency-dependent gain. When it is used in the proposed LDO, the low voltage operation ability, wide-band high power-supply rejection (PSR) characteristic and excellent transient response performance can be obtained. Simulation results show that this LDO can work properly at 1.2-V supply voltage, and the overshoot is only 1mV, while the PSR is better than 40dB from dc to 100-MHz. Therefore, the FDFF based LDO is well suited for low-voltage ripple-sensitive applications.