We revisit the question of how much buffer an IP router should allocate for its droptail FIFO link. For a long time, setting the buffer size to the bitrate-delay product has been regarded as reasonable. Recent studies of interaction between queueing at IP routers and TCP congestion control offered alternative guidelines. First, we explore and reconcile contradictions between the existing rules. Then, we argue that the problem of link buffer sizing needs a new formulation: design a buffer sizing algorithm that accommodates needs of all Internet applications without engaging IP routers in any additional signaling. Our solution keeps network queues short: set the buffer size to 2L datagrams, where L is the number of input links. We also explain how end systems can utilize the network effectively despite such small buffering at routers.

Packets in the Internet can experience large queueing delays during busy periods. Backbone routers are generally engineered to have large buffers, in which packets may wait as long as half a second (assuming FIFO service, longer otherwise). During congestion periods, these buffers may stay close to full, subjecting packets to long delays, even when the intrinsic latency of the path is relatively small. This paper studies the performance improvements that can be obtained for short-lived TCP flows by using more sophisticated packet schedulers, than are typical of Internet routers. The results show that the large buffers found in WAN routers contribute only marginally to improving router throughput, and the higher delays that come with large buffers makes them a dubious investment. The results also show that better packet scheduling algorithms can produce dramatic improvements in fairness. Using ns-2 simulations, we show that algorithms using multiple queues can significantly outperform RED and Blue, especially at smaller buffer sizes. Given a traffic mix of short-lived TCP flows with different round-trip times, longer round-trip time flows achieve 80% of their fair-share using multiqueue schedulers, compared to 40% under RED and Blue. We observe a similar performance improvement for multi-hop paths. We also show that performance results can be reliably scaled across a wide range of parameter values, so long as the ratio of the buffer size to the link bandwidth-delay product is held invariant.

This report describes an ATM multipoint connection caching strategy (AMCC) to control the explosive growth of traffic within the network and at an endpoint in a large distributed interactive simulation (DIS) application such as a battlefield simulation. For very large DIS applications with 100000 entities, the current method of broadcasting information among entities will no longer be feasible due to the computational and network bandwidth limitations. Our scheme divides the simulation space into grids and each grid square or a set of grid squares forms a multicast group. Entities join the groups within their perception range and thus, they receive state updates only from entities within their perception range. The AMCC utilizes the unique capabilities of our dynamic multipoint ATM signaling protocol, CMAP. We have implemented the AMCC and have successfully demonstrated a small DIS battlefield simulation application running over our ATM testbed.

The primary goal of the Axon architecture is to support a high-performance data path delivering high network bandwidth directly to applications. The Axon network interface is described from the perspective of its simulation, and in particular and implementation of error and flow control in hardware. Background is provided on the simulation package that has been used to explore these mechanisms, and a brief overview is given of the Axon architecture is implemented by the simulator. The error control mechanism, the hardware design, and the functional and performance simulation results are outlined. The rate control scheme is described, along with its implementation and simulation.>