Through-silicon-via (TSV)-to-TSV coupling is a new phenomenon in 3-D ICs, and it becomes a significant source of signal integrity problems. The existing studies on its extraction and analysis, however, become inaccurate when handling more than two TSVs on full-chip scale. In this paper, we investigate the multiple TSV-to-TSV coupling issue and propose a model that can be efficiently used for full-chip extraction. Then, we perform an analysis on the impact of TSV parasitics on coupling and delay. Unlike the common belief that only the closest neighboring TSVs affect the victim, this paper shows that nonneighboring aggressors also cause nonnegligible coupling noise. Based on these observations, we propose an effective method of reducing the overall coupling level.

This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2$\micro\hbox{m}$-diameter, 6$\micro \hbox{m}$-height through-silicon vias (TSVs) and$3.4\nbsp\micro\hbox{m}$-diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core communicates with its dedicated 4KB SRAM block using face-to-face bond pads, which provide negligible data transfer delay between the core and the memory tiers. The maximum operating frequency is 277 MHz and the maximum memory bandwidth is 70.9 GB/s at 277 MHz. The peak measured memory bandwidth usage is 63.8 GB/s and the peak measured power is approximately 4 W based on eight parallel benchmarks.

TSV-to-TSV coupling is a new parasitic element in 3D ICs and can become a significant source of signal integrity problem. Existing studies on its extraction, however, becomes highly inaccurate when handling more than two TSVs on full-chip scale. In this paper we investigate the multiple TSV-to-TSV coupling issue and propose an accurate model that can be efficiently used for full-chip extraction. Unlike the common belief that only the closest neighboring TSVs affect the victim, our study shows that non-neighboring aggressors also cause non-negligible impact. Based on this observation, we propose an effective method of reducing the overall coupling level in multiple TSV cases.

This paper studies TSV-to-TSV coupling in 3D ICs. A full-chip SI analysis flow is proposed based on the proposed coupling model. Analysis results show that TSVs cause significant coupling noise and timing problems despite that TSV count is much smaller compared with the gate count. Two approaches are proposed to alleviate TSV-to-TSV coupling, namely TSV shielding and buffer insertion. Analysis results show that both approaches are effective in reducing the TSV-caused-coupling and improving timing.

In this paper we present a test structure and design methodology for testing, characterization, and self-repair of TSVs in 3D ICs. The proposed structure can detect the signal degradation through TSVs due to resistive shorts and variations in TSV. For TSVs with moderate signal degradations, the proposed structure reconfigures itself as signal recovery circuit to improve signal fidelity. The paper presents the design of the test/recovery structure, the test methodologies, and demonstrates its effectiveness through stand alone simulations as well as in a full-chip physical design of a 3D IC.