Current diffusion model based image denoising methods suffer from semantic inconsistency and distortion due to their inability to maintain structural integrity, while diffusion models face two inherent limitations: (1) mandatory sampling initiation from pure Gaussian noise that mismatches denoising scenarios, and (2) uncontrollable uncertainty during stochastic sampling processes. Our work is motivated by the potential to harness precise edge information as conditional guidance to recalibrate diffusion sampling trajectories, thereby aligning the generative process with denoising objectives while preserving critical image structures. We propose a new image denoising framework, the EGDCF: Edge-Guided Diffusion networks with Coarse-to-Fine learning for image denoising, that synergizes edge-aware conditional guidance with a coarse-to-fine refinement mechanism through three key components: edge extractor, conditional diffusion model, and iterative denoising scheduler. EGDCF first uses a trainable Canny operator to extract multi-scale edge maps from noisy inputs, while calculating the number of denoising steps in the diffusion model’s reverse process based on the noise level of the input, thereby aligning the denoising trajectory with the actual noise distribution. Then, these structural priors are injected into the modified U-Net backbone network through attention based feature fusion, thereby guiding the sampling trajectory of the diffusion model’s reverse process. Finally, by fusing the noise input with the denoising results as the input for a new iteration, a clean denoised image can be obtained after multiple iterations. Quantitative evaluations on Gaussian and real-world noise datasets show effectiveness of our proposed method compared to state-of-the-art methods, particularly effective in high-noise regimes where conventional approaches fail.

As CMOS technology continues to scale, the associated reduction in device reliability margins has made accurate reliability evaluation a critical component of digital circuit design. Traditional methods typically assess reliability based on the average behavior of multiple input vectors (MIVs), while neglecting the significant variation introduced by individual input vector (IIV). In practice, different IVs often exhibit heterogeneous reliability distributions, and in sequential circuits with temporal correlation, these differences may span several orders of magnitude. This paper proposes a probabilistic injection framework for reliability analysis that explicitly considers input correlation in a sequential circuit. The method enables both fine-grained evaluation for each IIV and global assessment across MIVs, thereby offering a comprehensive understanding of not only average circuit reliability but also reliability bounds under specific input conditions. Experimental results on ISCAS’89, ITC’99, IWLS’05 and reference benchmark circuits demonstrate that the proposed approach achieves higher accuracy and greater stability compared to traditional methods.

Recent studies have demonstrated that cross-domain recommendation (CDR) effectively addresses the cold-start problem. Most approaches rely on transfer functions to generate user representations from the source to the target domain. Although these methods substantially enhance recommendation performance, they exhibit certain limitations, notably the frequent oversight of similarities in user preferences, which can offer critical insights for training transfer functions. Moreover, existing methods typically derive user preferences from historical purchase records or reviews, without considering that preferences operate at three distinct levels: category, brand, and aspect, each influencing decision-making differently. This paper proposes a model that integrates the preferences from coarse to fine levels to improve recommendations for cold-start users. The model leverages historical data from the source domain and external memory networks to generate user representations across different preference levels. A meta-network then transfers these representations to the target domain, where user-item ratings are predicted by aggregating the diverse representations. Experimental results demonstrate that our model outperforms state-of-the-art approaches in addressing the cold-start problem on three CDR tasks.

Accurate prediction of throughput, measured in Transactions per Second (TPS), is critical for financial trading systems, as it ensures system stability and scalability under high transaction volumes. We address this challenge by introducing a hybrid model that combines Discrete Wavelet Transform (DWT), Convolutional Neural Networks (CNN), and a Gated Recurrent Unit with an Attention Mechanism (GRU-AM). Our approach decomposes the nonlinear, non-stationary TPS data into high- and low-frequency components using DWT, allowing CNN and GRU-AM models to capture dynamic and nonlinear features effectively. Experimental results on real-world trading system data demonstrate the method's effectiveness. Compared to a variety of models, including ARIMA, CNN, and GRU, our method improves prediction accuracy by 2% to 20%. These results underscore the model's enhanced accuracy and efficiency, providing robust support for TPS prediction in financial trading systems.

Abstract The globalization of the integrated circuit design industry makes it easier for the adversary to pirate intellectual property and insert hardware Trojans (HTs). Although many HT protection methods have been proposed, some malicious elements can still be inserted into vulnerable nodes. Trojans are usually inserted in the rare nodes with the lowest observability, which makes it hard for testers to discover them. In this paper, we propose a dual-protection technology to protect the circuit against HT attacks based on observability. First, we propose an algorithm to increase the low observabilities of the circuit, so as to make it difficult for attackers to implant HTs. Several existing approaches try to identify the low observability by setting a threshold artificially, which is not generic. We do not need to set thresholds when targeting the low observability. Second, we present another logic locking algorithm to enhance the entire circuit’s security further. Simulation results on ISCAS85 benchmark and several larger circuits show that the proposed HT protection method has increased the lowest observability of the circuit by an average of 370.76 times. Furthermore, the logic locking technique maximizes the ambiguity for an attacker. Compared with the state of the art, the proposed logic locking can obtain better results, achieving a Hamming distance that is closer to 50% between the correct and incorrect outputs when a wrong key is applied.

Traditional logic synthesis methods are based on Boolean logic, which tends to produce redundant logic structures in dense circuit applications, such as complex number operations and error detection/correction coding. Traditional Boolean and Reed-Muller (TB-RM) logic synthesis method combining traditional Boolean (TB) logic and Reed-Muller (RM) logic can improve comprehensive optimization indexes and reduce cost. The existing TB design method is not effective when dealing with constrained systems with high-resource utilization requirements. In addition, traditional synthesis methods do not consider multiobjective optimization of area, power consumption and reliability. To solve these problems, we propose an effective dual logic synthesis method (EDSM), which includes dual logic detection method (DDM) and differential evolution algorithm based on multidimensional mutation strategy (DE-MMS). DDM can complete the logic detection function, and DE-MMS can further optimize the polarity. In addition, to evaluate the soft errors occurring more efficiently at the logic level, we propose a soft error rate (SER) estimation model. Experimental results show that compared with state-of-the-art evolutionary algorithms, EDSM can search for optimal solutions in all optimization problems; compared with commonly used TB-based minimization methods, EDSM has obvious advantages in multiobjective optimization of area, power consumption and SER. After 6-LUT FPGA technology and standard cells mapping, by selecting area as the optimal cost implementation, we obtain average improvements in the area of 14% and 2%, respectively.

Area and reliability optimization have become the primary constraints in circuits logic synthesis. To address the increasing area and transient fault susceptibility in combinational circuits, we propose a high-dimensional genetic algorithm (HGA). HGA adopts an evolutionary scheme based on ternary tree, and uses adaptive crossover operator and flight operator to jump out of local optimum. Moreover, based on the HGA, we propose an area and reliability optimization method (AROM) for mixed polarity Reed-Muller logic circuits, which searches the best polarity with minimum area and soft error rate. The experimental results confirm that AROM can search for more desirable nondominated solutions in less time compared to existing optimization methods, and can be used as an effective electronic design automation tool for multi-objective optimization.

Aspect category sentiment analysis (ACSA) aims to simultaneously detect aspect categories and their corresponding sentiment polarities (category-sentiment pairs). Some recent studies have used pre-trained generative models to complete ACSA and achieved good results. However, for ACSA, generative models still face three challenges. First, addressing the missing predictions in ACSA is crucial, which involves accurately predicting all category-sentiment pairs within a sentence. Second, category-sentiment pairs are inherently a disordered set. Consequently, the model incurs a penalty even when its predictions are correct, but the predicted order is inconsistent with the ground truths. Third, different aspect categories should focus on relevant sentiment words, and the polarity of the aspect category should be the aggregation of the polarities of these sentiment words. This paper proposes a hierarchical generative model with a coverage mechanism using sequence-to-set learning to tackle all three challenges simultaneously. Our model’s superior performance is demonstrated through extensive experiments conducted on several datasets.

This paper presents a process-oriented GCC failure analysis method based on fault injection. We first analyze the process of GCC, systematically define the fault modes of GCC, and establish a GCC fault mode library. We also propose a software fault injection method based on SystemTap and develop a related fault injection tool. Subsequently, we proceed to carry out a series of fault injection experiments on GCC, aiming to unearth potential reliability issues. These experiments serve as a means to identify modules within GCC that are susceptible to failures and to propose potential enhancements. The results of these experiments unequivocally underline the existing problems in fault tolerance mechanisms across various aspects of GCC. These findings underscores the significance of our approach in failure analysis and reliability evaluation of GCC. Through a holistic analysis of diverse fault modes and their associated manifestations, our approach contributes to a more profound understanding of GCC failure behavior. It offers valuable insights to guide future optimization endeavors.

Accurate and efficient identification of reliability-critical paths (RCPs) not only facilitates fault localization and troubleshooting but also allows circuit designers to improve circuit reliability at a low cost. This article proposes a local and global adjacency probability matrix-based approach (LGAPM) to quickly and efficiently identify RCPs of combinational logic circuits. The approach reflects the criticality of the overall reliability of the circuit as well as the local criticality of gates in the path. In addition, we design a pruning-based method to accelerate RCP identification in large-scale circuits. The experimental results of the LGAPM on all 74 series circuits, ISCAS-85, and partial EPFL benchmark circuits show that the 74181 circuit with a minimum of 17 paths and the EPFL-remainder10 circuit with a maximum of 8.081 × 108paths take times of about 0.18s and 33931.04s, respectively. The average accuracy on small and medium-scale circuits is 94.24%, and the average stability on all-size circuits is 86.19%. Compared to the SAT-based method, hill-climbing algorithm, and random method, LGAPM’s metrics are superior and more appropriate for large-scale circuits. The overall circuit reliability can be improved from 0.7726 to 0.9238 on average by hardening a tiny number of gates in the identified the most RCPs and the average cost savings is 4.08 times over random hardening methods.

The identification of reliability-critical input vectors (RCIVs) is vital in the assessment and prediction of reliability boundaries for logic circuits. This article introduces an approach grounded in association rule analysis (ARA) to swiftly and efficiently identify RCIVs in both combinational and sequential circuits. The utilization of the ARA model for validating the circuit’s associated primary inputs enhances accuracy while simultaneously reducing the complexity of RCIVs identification. Orienting the generation of new samples with associated inputs expedites the identification process. Quantifying circuit complexity enables the adaptive assignment of algorithmic parameters to circuits of diverse sizes. The construction of input sets facilitates a precise evaluation of the reliability of individual input vectors in sequential circuits. Experimental results on benchmark circuits illustrate that this approach achieves a mean accuracy of 0.9952, with Monte Carlo (MC) method serving as the reference, for small and medium-sized circuits, and require only 20.71% of MC’s time overhead. The average coverage of 0.9884 surpasses the reference method by 1.8 times. The stability is 4.35 times higher with the random method on large scale circuits with 224,624 gates and 6,642 primary inputs. Circuit designers can swiftly ascertain the average reliability and reliability boundaries of a circuit by using this approach for RCIVs identification. By applying optimizations of the identified RCIVs to expedite convergence and mitigate fluctuations, the influence of these RCIVs can be minimized in reliability evaluation and testing.

Amid growing concerns about hardware security, comprehensive security testing has become essential for chip certification. This paper proposes a deep-testing method for identifying Trojans of particular concern to middle-to-high-end users, with a focus on illegal instructions. A hidden instruction Trojan can employ a low-probability sequence of normal instructions as a boot sequence, which is followed by an illegal instruction that triggers the Trojan. This enables the Trojan to remain deeply hidden within the processor. It then exploits an intrusion mechanism to acquire Linux control authority by setting a hidden interrupt as its payload. We have developed an unbounded model checking (UMC) technique to uncover such Trojans. The proposed UMC technique has been optimized with slicing based on the input cone, head-point replacement, and backward implication. Our experimental results demonstrate that the presented instruction Trojans can survive detection by existing methods, thus allowing normal users to steal root user privileges and compromising the security of processors. Moreover, our proposed deep-testing method is empirically shown to be a powerful and effective approach for detecting these instruction Trojans.

The high overhead of tracing, the amount of up-front effort required to select trace points, and the lack of effective data analysis model are the significant barriers to the adoption of intra-component tracing for fault diagnosis today. This paper introduces a novel method for fault diagnosis by combining function level adaptive tracing, fault injection, and graph convolutional network. In order to implement this method, we introduce techniques for (i) selecting function level trace points, (ii) constructing approximate function call trees for programs when using adaptive tracing, and (iii) constructing graph convolutional network with fault injection campaign. We evaluate our method on four widely used open source server software: Redis, Nginx, Httpd, and SQlite. The experimental results show that our method outperforms log-based method, full tracing method, and Gaussian influence method in terms of accuracy, efficiency, and performance impact on the diagnosis target.

Software fault injection is a fundamental technique for studying the dependability of software systems. The code mutation based defect injections encounter efficiency (i.e., dormant faults) and accuracy (when they are not done at the source code level) issues. Software error injections directly emulate the effects of software defects, which is more efficient and practical. But, whether the injected errors truly represent the impact of bugs in the real world is still an open problem. Several studies have investigated the representativeness problem of component interface (API) errors. However, the component API error injections are relatively coarse in granularity because they regard the component programs as black boxes. Thus, they cannot be used to analyze the internal error behaviors within the components. To overcome this issue, we propose a finite state machine for generating representative code mutations (as baseline) and a novel tracing approach for collecting function call interface data. That enables the analysis of the representativeness of program internal errors from the perspective of function call interface for C/C++ programs by fault-free and fault injection control experiments. The experimental results imply that the traditional error models cannot accurately emulate software defects at function call interfaces. We provide useful suggestions based on our findings for improving the representativeness of function call interface error injection.

Area optimization is one of the most important contents of circuits logic synthesis. The smaller area has stronger testability and lower cost. However, searching for a circuit with the smallest area in a large-scale space of polarity is a combinatorial optimization problem. The existing optimization approaches are inefficient and do not consider the time cost. In this paper, we propose a multi-strategy wolf pack algorithm (MWPA) to solve high-dimension combinatorial optimization problems. MWPA performs global search based on the proposed global exploration strategy, extends the search area based on the Levy flight strategy, and performs local search based on the proposed deep exploitation strategy. In addition, we propose a fast area optimization approach (FAOA) for fixed polarity Reed-Muller (FPRM) logic circuits based on MWPA, which searches the best polarity corresponding to a FPRM circuit. The experimental results confirm that FAOA is highly effective and can be used as a promising EDA tool.

The dependability of systems gains extensive attention as they are vulnerable to unexpected events, such as soft errors in circuits. Many works proposed to enhance the reliability of circuits at a low cost by hardening the reliability-critical gates (RCGs). However, it is challenging and necessary to determine the gates that need to be improved, especially for sequential circuits. Currently, methods used to locate RCGs for sequential circuits are struggling to balance the accuracy and computational overhead. This paper presents a method for locating RCGs of sequential circuits, the states of gates are aggregated into slices based on the time window graph model, then a probability-based calculation method is proposed for quantifying the criticality of gate reliability oriented to slices, finally, locating RCGs for sequential circuits which takes the accumulation of faults into consideration. Experiments on fifty ISCAS-89 and six ITC-99 benchmark circuits show that, on average, the accuracy of our method is 0.9417 of that of Monte Carlo (MC) method, and the speed and memory cost are 1725 times faster and 5.57 times lower than those of MC method. In addition, the proposed method is much faster and more accurate than stochastic method for large-scale circuits.

We present a biomedical knowledge enhanced pre-trained language model for medicinal product vertical search. Following ELECTRA’s replaced token detection (RTD) pre-training, we leverage biomedical entity masking (EM) strategy to learn better contextual word representations. Furthermore, we propose a novel pre-training task, product attribute prediction (PAP), to inject product knowledge into the pre-trained language model efficiently by leveraging medicinal product databases directly. By sharing the parameters of PAP’s transformer encoder with that of RTD’s main transformer, these two pre-training tasks are jointly learned. Experiments demonstrate the effectiveness of PAP task for pre-trained language model on medicinal product vertical search scenario, which includes query-title relevance, query intent classification, and named entity recognition in query.

The keyphrase generation task is a challenging work that aims to generate a set of keyphrases for a piece of text. Many previous studies based on the sequence-to-sequence model were used to generate keyphrases, and they introduce a copy mechanism to achieve good results. However, we observed that most of the keyphrases are composed of some important words (seed words) in the source text, and if these words can be identified accurately and copied to create more keyphrases, the performance of the model might be improved. To address this challenge, we propose a DualCopyNet model, which introduces an additional sequence labeling layer for identifying seed words, and further copies the words for generating new keyphrases by dual copy mechanisms. Experimental results demonstrate that our model outperforms the baseline models and achieves an obvious performance improvement.

Reliable circuits help prevent artificial intelligence (AI) systems from being corrupted by the soft errors occurred in memories or combinational circuits, which promotes the development of AI security. However, it is a great challenge to measure the reliability of combinational circuits at register transfer level (RTL) rapidly and efficiently. In this paper, a new fast and accurate computational model based on stochastic computation (SC) is presented to meet these objectives. In the proposed approach, the circuit netlists at RTL are parsed to satisfy the requirements of SC on the bitstream structure of the circuits, and then a Sobol sequence-based algorithm for generating uniform non-Bernoulli sequences is built to reduce the random fluctuations occurred in probability calculations. After that, an adaptive algorithm based on a MAX–MIN ant system is constructed using graphics processing unit-based parallel schemes to greatly accelerate the calculation. The experimental results validate our proposed technique, showing that this approach was approximately 51 and 42 times faster than the traditional SC approach and the stochastic computational model (SCM), respectively; its required sequence length was approximately 1.66 times shorter than that of the traditional SC approach, and its relative error was two times smaller than that of the SCM.

The identification of reliability-critical primary input leads (RCPIs) plays an important role in the testing and prediction of reliability boundaries of logic circuits. This article presents a gate-sensitive-attributes-based approach to estimate the criticality of the primary input leads in combinational circuits to their reliability. Oriented to the input vector, a subcircuit-based traversal method marks the critical input leads of each gate in a circuit. Gate-sensitive attributes and a reverse recursive algorithm quantify the effect of each RCPI on circuit reliability under the input vector. A parallel calculation method based on subcircuits with only one primary output reduces the computational complexity to accelerate the calculation process. Similarity-based clustering avoids unnecessary calculations, and a self-adaptive strategy is used to check convergence. Experimental results on benchmark circuits show that the average accuracy of this approach is 0.9634 with Monte Carlo (MC) as the reference and it is 3445 times faster than the MC on average while its average memory cost is 1.67 greater than the MC model. Although the fitness of the worst input vector obtained by other reference methods is 1.09 times better than that of this approach on average, this approach is approximately 21 times faster than that reference method on average.

Approximate arithmetic circuit (AAC) has emerged as a promising high-performance and energy-efficient circuit paradigm, which can be used in many applications with inherent error tolerance. To guarantee the usability of AACs and the availability of resilient applications, it is necessary to analyze the reliability of AACs. Most current literature focus on the error characteristics of AACs and few methods can be applied to estimate the reliability of AACs. These methods mostly have exponential time complexities and evaluate the average reliability assuming the input combinations are equally likely. In reality, the primary input (PI) signals can be given with any probability from 0 to 1. In this article, we assume that the PIs have random signal probabilities and propose approaches to reliability boundary estimation for AACs. First, we propose a new efficient and accurate method to evaluate the reliability of AACs. The method mainly calculates the AAC reliability for an input vector set, and furthermore, during the calculation, the correlation problem is considered to increase accuracy. Then, based upon the proposed AAC reliability evaluation method, we present the approaches to finding the reliability boundary. Randomly given signal probabilities of every PI, two heuristic search algorithms are utilized to find the lowest reliability. A comparison of the results on three series of AACs and the circuits in the EvoApprox8b library confirms that the proposed reliability evaluation method is more accurate and efficient than the previous method. Further experiments verify the plausibility of the calculated reliability boundary of AACs.

This article presents a bounded model checking (BMC)-based temperature-aware software-based self-testing (SBST) technique to test worst case delay faults within the highest temperature range. The BMC-based SBST method first defines the sequential constraint. It develops a sequentially constrained automatic test pattern generation (ATPG) to ensure that the generated delay test patterns can emerge in functional mode. It then uses the processor’s multiple-level information to reduce the model complexity, avoid aborts due to time-outs during the BMC process, and generate test programs automatically. A temperature-aware SBST method has then been developed to ensure that the test temperature is within the specified range and test the worst case delays under high temperature. Experimental results demonstrate that the proposed technique achieves an extremely high coverage for delay faults and effectively avoids yield loss caused by the overtesting problem. Its test quality also outperforms that of the existing methods. The generated SBST programs are successful and efficient in testing worst case delay faults under high temperature.

Recently, approximate arithmetic circuits (AACs) have been widely used in applications with inherent error tolerance. To guarantee the usability of AACs in the approximation applications, it is necessary to analyze AAC reliability. In this paper, we propose two accurate AAC reliability evaluation methods based on signal reliability analysis, where subtraction correlation coefficient and division correlation coefficient are applied respectively to solve the correlation problem caused by fanout reconvergence. The accuracy and scalability of these two methods are verified by randomly selected circuits from the EvoApprox8b library. The experimental results show that, compared with Monte Carlo (MC) simulation, our two proposed methods have average error rates of 0.34% and 0.65% and the run-time costs are 0.012% and 0.019% of MC’s simulation time. Moreover, the proposed methods are superior to two recently reliability analysis based methods in terms of efficiency and accuracy.

Very-large-scale network-on-chip (VLS-NoC) has become a promising fabric for supercomputers, but this fabric may encounter the many-fault problem. This article proposes a deterministic routing algorithm to tolerate the effects of many faults in VLS-NoCs. This approach generates routing tables offline using a breadth-first traversal algorithm and stores a routing table locally in each switch for online packet transmission. The approach applies the Tarjan algorithm to degrade the faulty NoC and maximizes the number of available nodes in the reconfigured NoC. In 2D NoCs, the approach updates routing tables of some nodes using the deprecated channel/node rules and avoids deadlocks in the NoC. In 3D NoCs, the approach uses a forbidden-turn selection algorithm and detour rules to prevent faceted rings and ensures the NoC is deadlock-free. Experimental results demonstrate that the proposed approach provides fault-free communications of 2D and 3D NoCs after injecting 40 faulty links. Meanwhile, it maximizes the number of available nodes in the reconfigured NoC. The approach also outperforms existing algorithms in terms of average latency, throughput, and energy consumption.

This paper explores an intrusion mechanism to microprocessors using illegal instructions, namely hidden instruction Trojan (HIT). It uses a low-probability sequence consisting of normal instructions as a boot sequence, followed by an illegal instruction to trigger the Trojan. The payload is a hidden interrupt to force the program counter to a specific address. Hence the program at the address has the super privileges. Meanwhile, we use integer programming to minimize the trigger probability of HIT within a given area overhead. The experimental results demonstrate that HIT has an extremely low trigger probability and can survive from the detection of the existing test methods.

Generating functional tests for processors has been a challenging problem for decades in the very large-scale integration testing field. This paper presents a method that generates software-based self-tests by leveraging bounded model checking (BMC) techniques and targeting, for the first time, out-of-order [out-of-order execution (OOE)] superscalar processors. To combat the state-space explosion associated with BMC, the proposed method starts by combining module-level abstraction-refinement with slicing to reduce the size of the model under verification. Next, an off-the-shelf BMC solver is used on the obtained extended finite-state machines to generate the leading sequences that are necessary to excite internal processor functions. Finally, constrained automatic test-pattern generation is used to cover all structural faults within every function excited by the obtained leading sequences. Experimental results show that the proposed method leads to extremely high fault coverage on the critical components corresponding to OOE operations in functional mode. The method therefore helps in tackling the over-testing problem that is inherent to the full-scan test approach.

Rapid advancement in micro-electromechanical techniques leads to the wide application of wireless sensor networks (WSNs). In a linear WSN (LWSN), all sensor nodes are arranged in a straight line to monitor health status of some linear infrastructure structure such as bridges, highways, pipelines, etc. To enhance reliability of the infrastructure monitoring services, LWSNs are often designed to incorporate a limited number of backbone nodes for transferring or relaying information, leading to a more complex hybrid structure. In this paper, a multivalued decision diagram (MDD)-based analytical approach is proposed to evaluate performance of an LWSN system with backbone nodes. Particularly, we model and analyze the probability that the hybrid LWSN performs at a particular performance level, which is characterized by the number of sensor nodes being able to reach the base station. A single compact MDD model is constructed by sharing all isomorphic submodel structures involved in different performance levels. The MDD model, once being constructed, can be reused for evaluation using different failure time distributions or mission time. A case study is presented to substantiate the application of the proposed MDD approach for developing the optimal backbone node allocation strategy to guarantee the reliability requirement on the infrastructure monitoring services.

Wafer-level NoC has emerged as a promising fabric to further improve supercomputer performance, but this new fabric may suffer from the many-fault problem. This paper presents a deterministic-path routing algorithm for tolerating many faults on wafer-level NoCs. The proposed algorithm generates routing tables using a breadth-first traversal strategy, and stores one routing table in each NoC switch. The switch will then transmit packages according to its routing table online. We use the Tarjan algorithm to dynamically reconfigure the routes to avoid the faulty nodes and develop the deprecated link/node rules to ensure deadlock-free communication of the NoCs. Experimental results demonstrate that the proposed algorithm does not only tolerate the effects of many faults, but also maximizes the available nodes in the reconfigured NoC. The performance of the proposed algorithm in terms of average latency, throughput, and energy consumption is also better than those of the existing solutions.

In recent years, more and more companies have moved from closed source software development to open source software (OSS) development. The reliability assessment of OSS has become an important issue. However, due to the lack of a standardized development process and uncertain number of participating developers, it is hard to measure the reliability of OSS compared to closed source software. This paper proposes a framework for reliability automatic assessment of OSS based on JIRA. It contains the failure data acquisition module, the reliability modeling module and the reliability attribute analysis module. The proposed framework is applied on popular OSS Kafka to assess the reliability. The experimental results show that the proposed framework is good for the reliability assessment of OSS.

The existing analytical methods for estimation of the reliability of approximate circuits are based on probability transfer module (PTM) method and Monte Carlo (MC) method. However, the PTM-based method is confined to small-scale approximate circuits and large circuits with weak signal correlation, and the MC method is time-consuming to obtain accurate results. This paper presents two methods for reliability estimation of gate-level approximate circuits based on probability gate model (PGM). The first is non-process correlation algorithm that does not consider the correlation among signals to obtain an approximate value of circuit reliability, and its time complexity keeps a linear relation with the number of gates. The second is the processing correlation algorithm which can estimate the correlation caused by fanout nodes of the approximate circuits, and it has the obvious advantage on accuracy, but its time complexity is exponential with the number of fanout nodes in the circuit. Experimental results demonstrate the validity and accuracy of the proposed methods.

Anomaly detection plays an important role in large-scale distributed systems. System logs are significant source of troubleshooting and problem diagnosis. Most of the existing anomaly detection methods apply only one machine learning model to extract feature from structured logs. However, each machine learning model has different strength towards different target system. It is hard for developers to know which is the best method to their practical problem at hand. This paper proposes two methods for anomaly detection based on the machine learning ensemble models. The first method takes mixture of experts to combine the weighted prediction of ensemble members to generate the final prediction. The second method divides the sample into n parts, then use n models to extracting features. Experimental results demonstrate the validity and accuracy of the proposed methods.

The sensitivity of circuit input vectors plays an important role in estimating circuit reliability bounds and identifying reliability-critical gates. Consequently, to effectively calculate the circuit sensitivity for the input vectors is becoming a necessity for nanocircuits, helping circuit designers to select the architecture that best optimizes the tradeoffs between reliability and area power delay. Combining probability signals and employing the iterative strategy presented in Monte Carlo method, this paper proposes an iterative algorithm based on a probabilistic transfer matrix to investigate the circuit sensitivity for the given input vectors, ensuring computational precision and speed. Simulation results on benchmark circuits show that the proposed algorithm is an efficient and accurate method to calculate the sensitivity of the applied input vectors, and that it can be used to improve circuit reliability at a small cost in the early stages of circuit design.

With the widely using of VLSI circuits, their security issue has been a critical factor to the security of the modern system. In this paper, we propose a testing method using Bounded Model Checking (BMC) to test the small Trojan that is injected by slightly modifying the original design. First, we implement physical inspection on the training chip set that has the same function but from different sources, and extract suspicious circuit pairs by pairwise comparison on the chips. Second, we use BMC to detect the inconsistent functions on the suspicious circuit pairs. Third, we collects these inconsistent functions as well as their corresponding input sequences into a vulnerability scanner library, and test the other chips using that library. Experimental results show the proposed method can detect the small Trojan in sequential circuits with large sequential depth using an optimized computing time. Furthermore, the method can accurately distinguish small Trojans from circuit optimizations in logic synthesis.

Approximate adders have become a focus of approximate circuit design. However, there has been a lack of appropriate methods to evaluate their reliability. The existing analytical methods for accurate circuits cannot be applied to approximate circuits directly, and the Monte-Carlo simulation is time-consuming. Some metrics such as worst-case error, error distance, mean error distance and normalized error distance have been used to describe the reliability characters and arithmetic performance of approximate circuits, but they cannot directly calculate the reliability. This paper presents two methods for approximate adders reliability estimation based on the probabilistic transfer matrix (PTM) model. The first method takes the sum of the probabilities of all acceptable outputs as the probability of acceptable result corresponding to each input. The second method calculates the probability of acceptable result according to the deviation between the acceptable output and exact output. The reliability of approximate adders is calculated by combining the probabilities of the input vectors and those of the corresponding acceptable results. Experimental results demonstrate the validity and accuracy of the proposed methods.

Online testing is critical to ensure reliable operation of manycore systems based on a network-on-chip (NoC) interconnection fabric. We present a software-based online NoC self-testing solution based on bounded model checking (BMC). The proposed method first implements BMC on a sliced extended finite-state machine, and extracts the leading sequences necessary to excite NoC functions. Next, it targets the structural faults within every function excited by the leading sequence through constrained ATPG. Finally, a test protocol is developed to make the test responses observable. Experimental results show that the proposed method achieves high fault coverage in functional mode and outperforms previously proposed solutions. In addition, the fault coverage is very close to that of full-scan testing, but without any area overhead.

Increasing power density and thermal hotspots has become a major problem for integrated circuits. The problem is exacerbated when applying tests to a System-on-Chip (SoC). Running a test individually may exceed the given temperature threshold. So scheduling tests to reduce the test application time (TAT) while keep the cores thermally safe has become a key issue. Dynamic Voltage and Frequency Scaling (DVFS) has been widely used in modern IC devices to control power and temperature. We exploit such features for thermal-aware test scheduling and propose a method to efficiently determine the scaling factor which leads to optimized TAT without violating the thermal constraints. The proposed method can also be used to efficiently calculate the maximum temperature certain tests can achieve when DVFS is applied. After formulating the problem into an MILP model, experimental results on ITC'02 benchmarks showed that DVFS can be used to deal with power intensive tests efficiently and exploiting such features can achieve up to 16.37% reduction of TAT.

Despite the numerous prevention and protection techniques that have been developed, the exploitation of memory corruption vulnerabilities still represents a serious threat to the security of software systems and networks. Because of the adoption of the write or execute only policy (W⊕X) and address space layout randomization (ASLR), modern operate systems have been strengthened against code injection attacks. However, attackers have responded by employing code reuse attacks, in which software vulnerability is exploited to weave control flow through existing code base. Solutions targeting different aspects of the attack itself have had some success, but none of them can be a silver bullet. Under this situation, it is necessary to develop a general prevention to mitigate code reuse attacks. In this paper, we present a novel and general defense technique called control flow lazily check (CFLC), which allows for effective enforcement of control flow integrity. Specifically, instead of immediately determining the violation of control flow before the control flow transfer takes place, CFLC detects the violation after the transfer. Further, CFLC ensures that no deviation can be used to bypass the checking code and craft a malicious system call neither. To reduce the performance overhead, we introduce a coarse-grained CFLC based on the principle that a success intrusion must invoke a system call. We have implemented CFLC with the help of dynamic binary instrumentation tool and the evaluation demonstrates that CFLC can not only prevent code reuse attacks but also code injection attacks. It is shown that CFLC has achieved significant safety than other existing defenses with a modest performance penalty.

The rapid development of nanotechnology has opened up new possibilities and introduced new challenges for circuit design. It is very important to study new analysis methods for accurate circuit reliability. Few methods for evaluating circuit reliability were proposed in recent years. For example, the original probabilistic transfer matrix (PTM) model has large time and space overhead, so it can only calculate small scale circuits, the improved PTM model proposed in [2] can handle large scale circuits but it also has large time overhead. In this paper, the concept of macro-gate is defined and an iterative PTM model based on macro-gate is proposed. Based on this model, a circuit reliability evaluation algorithm that can calculate the circuit reliability from primary input to any level of the circuit is given. The complexity of the proposed algorithm related to the number of macro-gates contained in the circuit is linear. Experimental results show that the proposed method has the same accuracy as the PTM model, but it has lower time overhead for large circuits.

Non-parametric statistical methods are applied to verdict that early failure behavior of the testing process may have less impact on later failure process, so it happens in software failure time prediction that one does not have enough information to estimate the software failure process well but do have enough information to estimate the failure data at given instance. The prediction accuracy of software reliability prediction models based on recurrent neural network, feed-forward neural network, relevance vector machine, support vector machine and some nonhomogeneous Poisson process models is compared. Experimental results show that software failure time prediction models based on transduction inference theory could achieve higher prediction accuracy.

This paper proposes a new safe measurement-based estimation method for Worst-Case Execution Time (WCET) of programs in real-time systems. The latest progress in Pattern Recognition of learning to detect unseen object classes by between-class attribute transfer has been used for automatic test-data generation in our method. Based on control flow graph partition, execution profiles of each basic block and probabilities of their executions can be extracted during program executions driven by test data. Afterwards, a critical path can be identified by calculating its execution probability among all feasible paths. With measurement for critical paths, WCET can be obtained by adding static analysis of hardware features to measurement results. The objective of this paper is not to present finished or almost finished work. Instead we hope to trigger discussion and solicit feedback from the community in order to avoid pitfalls experienced by others and to help focus our research.

To estimate the reliability and find the weak point of circuits at design phase, several high-level evaluation methods have been proposed recently. However, most of these methods can only be used for combinational circuits. In this paper, we propose a reliability evaluation method based on probabilistic transfer matrices to accurately estimate the reliability of a flip flop circuit. The proposed method is compared with the method in for the D-type flip-flop. Experimental results confirmed that our method is accurate.

Although either of temporal ordering and frequency distribution information embedded in process traces can profile normal process behaviors, but none of ever published schemes uses both of them to detect system call anomaly. This paper claims combining those two kinds of useful information can improve detection performance and firstly proposes sequential frequency vector (SFV) to exploit both temporal ordering and frequency information for system call anomaly detection. Extensive experiments on DARPA-1998 and UNM dataset have substantiated the claim. It is shown that SFV contains richer information and significantly outperforms other techniques in achieving lower false positive rates at 100% detection rate.

Existing redundant multithreading (RMT) detects faults by comparing the result of each instruction between the master and slave threads, which can lead to huge comparison and communication overhead. To address this problem, the checkpoint-based RMT (like RVQ_F) was proposed, but in such architectures, master threads must wait for slave threads to arrive at the same position at each checkpoint, this may delay the release of resources occupied by master threads and decrease performance. This paper proposes an asynchronous checkpoint-based redundant multithreading architecture (AC-RMT), in which two context saving rooms are set aside for each thread, one for detecting faults, and the other for saving the last checkpoint used for fault restoration. Compared with RVQ_F, AC-RMT efficiently boosts performance because, by avoiding the waiting of master threads at checkpoints, resources can be released timely.

In order to evaluate software from the third party whose source codes are not available, after a careful analysis of the statistic data sorted by orthogonal defect classification, and the corresponding relation between patterns of high level language programs and machine codes, we propose a fault injection scheme at machine code level suitable respectively to the IA32 ARM and MIPS architecture, which takes advantage of mutating machine code. To prove the feasibility and validity of this scheme, two sets of programs are chosen as our experimental target: Set I consists of two different versions of triangle testing algorithms, and Set II is a subset of the Mibench which is a collection of performance benchmark programs designed for embedded systems; we inject both high level faults into the source code written in C language and the corresponding machine code level faults directly into the executables, and monitor their running on Linux. The results from experiments show that at least 96% of total similarity degree is obtained. Therefore, we conclude that the effect of injecting corresponding faults on both the source code level and machine code level are mostly the same. Therefore, our scheme is rather useful in analyzing system behavior under faults.

This paper proposes a novel N-modular redundancy (NMR) structure with concurrent output error location (COEL) capability. The concurrent output error locatable NMR structure consists of a conventional NMR structure and a totally self-checking (TSC) extra circuit with N+1 two-rail code outputs. This extra circuit is used for locating the output error produced by any replicated module or the voter, and the internal fault produced by the extra circuit itself. Such a self-checking extra circuit is called the output error locator (OEL). It is constructed by conventional TSC two-rail code checkers (TRCs) and self-testing multi-input comparators. Each comparator is made by adding one extra two-rail code input to the cascaded multi-input comparator. The error handling capabilities, hardware complexity and propagation delay are analyzed for the proposed OEL. The performance of the proposed scheme and that of the Gaitanis's scheme are compared for a triple modular redundancy (TMR) structure.