Demo Data from EDBT 2026 / reviewers in the wild / expert
Emilio Wuerges
dblp:52/7552
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 2020
0000-0001-5560-5603ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 76% Embedded and real-time systems · 9% Memory systems · 7% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design
engineering change order |
0.4 | 1 | 2020 | 3-Step Rectilinear Minimum Spanning Tree Construction for Obstacle-Avoiding Component-to-Component Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Electronic design automation › physical design › routing › VLSI routing
obstacle-avoiding routing |
0.4 | 1 | 2020 | 3-Step Rectilinear Minimum Spanning Tree Construction for Obstacle-Avoiding Component-to-Component Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Electronic design automation
physical design |
0.4 | 1 | 2020 | 3-Step Rectilinear Minimum Spanning Tree Construction for Obstacle-Avoiding Component-to-Component Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Electronic design automation › physical design
routing |
0.4 | 1 | 2020 | 3-Step Rectilinear Minimum Spanning Tree Construction for Obstacle-Avoiding Component-to-Component Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Memory systems › cache
cache behavior |
0.2 | 1 | 2013 | Reconciling real-time guarantees and energy efficiency through unlocked-cache prefetching · DAC 2013 |
Processor architecture and microarchitecture › instruction fetch
instruction prefetching |
0.2 | 1 | 2013 | Reconciling real-time guarantees and energy efficiency through unlocked-cache prefetching · DAC 2013 |
Embedded and real-time systems
worst-case execution time analysis |
0.2 | 1 | 2013 | Reconciling real-time guarantees and energy efficiency through unlocked-cache prefetching · DAC 2013 |
Embedded and real-time systems › energy-efficient embedded systems
energy-efficient real-time systems |
0.0 | 1 | 2013 | Reconciling real-time guarantees and energy efficiency through unlocked-cache prefetching · DAC 2013 |
Methods — techniques the papers use, named apart from their topics
rectilinear minimum spanning tree · 0.43-step construction · 0.4unlocked-cache prefetching · 0.2software prefetching · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | 3-Step Rectilinear Minimum Spanning Tree Construction for Obstacle-Avoiding Component-to-Component RoutingabstractThe continuous growth of digital integrated designs demands constant improvement in tools and development processes. Engineering change order (ECO) are design changes that occur late in the design process and require that subsequent stages must be adapted. ECO changes after the place and route flow can result in a large number of disconnected components and design tools are expected to reconnect these components on the fly. The ICCAD 2017 contest problem B launched a race to solve this challenge. This article presents two new solutions that outperform the top published solutions for this problem, with reduced routing costs and 21% shorter execution time. Moreover, our solutions are simpler, more general and pave the way for optimal minimum spanning tree-based obstacle-avoiding component-to-component routing. Emilio Wuerges |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2013 | Reconciling real-time guarantees and energy efficiency through unlocked-cache prefetchingabstractFor real-time tasks, cache behavior must be constrained via cache locking or predicted by WCET analysis. Since the former gives up energy efficiency for predictability, this paper proposes a novel code optimization that reduces the miss rate of unlocked instruction caches and, provenly, does not increase the WCET. We optimized the 37 programs from the Mälardalen WCET benchmark for 36 cache configurations and two technologies. By exploiting software prefetching on top of on-demand fetching, we reduced the memory's contribution to the energy consumption (by 11.2%), to the average case execution time (by 10.2%), and to the WCET (by 17.4%). Emilio Wuerges, Rômulo Silva de Oliveira, Luiz Cláudio Villar dos Santos |
DAC | 1 |
| 2013 | Quality assessment of subsampling patterns for pel decimation targeting high definition videoabstractAlthough pel decimation has been widely used to reduce the computational effort in video coding, there is no consensus about the optimal subsampling pattern. This paper presents an extensive analytical and statistical comparison of several different subsampling patterns using analysis of variance. The investigation includes commonly used patterns as well as seven proposed ones. The experiments were conducted on 19 video samples in a range of five resolutions (being nine videos at 1080p) and 30 bitrates by using the state-of-the-art x264 encoder running successive elimination exhaustive search. Two objective quality metrics were reported, PSNR and DSSIM, resulting in 10680 experimental points. The analysis of such amount of data allowed us to conclude that the proposed 4:3 ratio shows less than 5% in DSSIM and 1% in PSNR losses, being more than two times faster than full sampling. Compared with higher decimation, it presents a better trade-off between speedup and quality loss. Ismael Seidel, Bruno George de Moraes, Emilio Wuerges, José Luís Güntzel |
ICME | 3 |