This work presents a supervised machine learning (ML) technique to suppress static and dynamic errors in time-interleaved (TI) successive-approximation-register (SAR) analog-to-digital converters (ADCs). Traditional methods rely on high-speed buffers and complex calibration algorithms to address reference ripple, gain mismatch, timing mismatch, and offset mismatch, increasing area/cost and design complexity. By contrast, the proposed ML-based approach uses a low-speed SAR ADC to digitally correct these errors, enhancing performance and lowering power consumption without requiring implicit knowledge of error sources or complex calibration procedures. The proposed ML calibration is demonstrated on a 2-channel time-interleaved ADC test-chip fabricated in 28nm CMOS and improves SNDR/SFDR by more than 21/38dB respectively.

This work presents a machine learning (ML) technique to suppress reference ripple errors in successive approximation register (SAR) analog-to-digital converter (ADC). Reference voltage ripple due to switching in SAR ADC introduces dynamic error which manifests as spurs in the output spectrum and limits ADC resolution. Conventional techniques to suppress reference ripple require large decoupling capacitor and high-speed reference voltage buffer which consume large area and power. The proposed ML approach uses a supervised technique in which a low-speed 10MHz SAR ADC is used for learning and correcting reference ripple error in a 200MHz SAR ADC. Simulated in 28nm CMOS technology, the proposed ML approach reduces overall ADC power consumption by 4.9x without degrading performance.

Over the years, successive approximation register (SAR) analog-to-digital converter (ADC) designs have adopted different techniques to correct static and dynamic errors. This work proposes a machine-learning (ML) approach that uses a single model to correct both static and dynamic errors without requiring prior knowledge of these errors or complex design efforts. The proposed technique derives a custom feature set from the ADC output and uses supervised learning technique with a low-speed reference ADC to learn a representation of the ADC errors and correct them continuously in the back-end. The proposed ML correction is demonstrated on a 10-bit SAR ADC fabricated in 65nm CMOS and improves SNDR and SFDR by more than 8dB and 25dB respectively. The proposed ML technique adopts online learning and adaptively updates all the model weights individually to achieve fast convergence.

This work presents a supervised machine learning (ML) technique to simultaneously suppress static and dynamic errors in successive approximation register (SAR) analog-to-digital converter (ADC) and a delta-sigma digital-to-analog converter (DAC). Capacitor mismatches, reference ripple and kick-back errors in switched-capacitor circuits, and element mismatch and inter-symbol interference (ISI) errors are the sources of static and dynamic errors in SAR ADC and $\Delta \Sigma$ DAC respectively. Conventional approaches employ dynamic element matching, error-shaping and high-speed reference buffers for suppressing these errors at the cost of increased power/area penalties and complex design efforts. The proposed ML approach uses a supervised technique in which a low-speed SAR ADC is used for learning and correcting dynamic errors digitally in both ADC and DAC using a single on-chip ML circuit. The key advantages of the proposed approach are - detailed knowledge of error generation mechanisms are not needed for calibration, reduction in power consumption and improvement in data converter performance.

This work presents a fusion artificial intelligence (AI) framework that combines patient electronic medical record (EMR) and physiological sensor data to accurately predict early risk of sepsis 4 hours before onset. The fusion AI model has two components - an on-chip AI model that continuously analyzes patient electrocardiogram (ECG) data and a cloud AI model that combines EMR and prediction scores from on-chip AI model to predict fusion sepsis onset score. The on-chip AI model is designed using analog circuits for high energy efficiency that allows integration with resource constrained wearable device. The on-chip AI reduces by 4.5× compared to digital baseline, and by 4× compared to state-of-the-art bio-medical AI ICs. Combination of EMR and sensor physiological data improves prediction performance compared to EMR or physiological data alone, and the late fusion model has an accuracy of 92.2% in predicting sepsis 4 hours before onset. The key differentiation of this work over existing sepsis prediction literature is the use of single modality patient vital (ECG) and simple demographic information, instead of comprehensive laboratory test results and multiple vital signs.

This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications.

Spiking neural network (SNN) is promising but the development has fallen far behind conventional deep neural networks (DNNs) because of difficult training. To resolve the training problem, we analyze the closed-form input-output response of spiking neurons and use the response expression to build abstract SNN models for training. This avoids calculating membrane potential during training and makes the direct training of SNN as efficient as DNN. We show that the nonleaky integrate-and-fire neuron with single-spike temporal-coding is the best choice for direct-train deep SNNs. We develop an energy-efficient phase-domain signal processing circuit for the neuron and propose a direct-train deep SNN framework. Thanks to easy training, we train deep SNNs under weight quantizations to study their robustness over low-cost neuromorphic hardware. Experiments show that our direct-train deep SNNs have the highest CIFAR-10 classification accuracy among SNNs, achieve ImageNet classification accuracy within 1% of the DNN of equivalent architecture, and are robust to weight quantization and noise perturbation.

This work presents a true random number generator (TRNG) that uses noise and jitter in a continuous-time, deltasigma modulator (CTDSM) as entropy source. A multi-bit non-return-to-zero (NRZ) feedback digital-to-analog converter (DAC) ensures that input swing seen by the front-end integrators is small and dominated by CTDSM noise and jitter, thus allowing the proposed circuit to simultaneously operate as both CTDSM and TRNG which is a key differentiation of this work compared to state-of-the-art TRNGs. Voltage controlled ring oscillators are used to implement integrators in the proposed CTDSM. Fabricated in 65nm CMOS, the TRNG has an energy efficiency of 3pJ/bit at throughput of 33Mbps and 3.5pJ/bit at 200Mbps, and passes all NIST tests with a minimum pass rate> 0.96. The measured minimum entropy of the TRNG bits is > 0.9995 across multiple chips and voltage/temperature corners without any calibration.

A recurrent neural network (RNN) is presented in this work for automatic detection of atrial fibrillation from raw ECG signals without any hand-crafted feature extraction. We designed a stacked long-short term memory (LSTM) network - a special RNN with capability of learning long-term temporal dependencies in the ECG signal. The RNN is digitally synthesized in 65nm CMOS process, and consumes 21.8nJ/inference at 1kHz operating frequency, while achieving state-of-the-art classification accuracy of 85.7% and f1-score of 0.82. The energy consumption of the proposed RNN is 8 χ lower than state-of-the-art integrated circuits for arrhythmia detection.

This paper presents fully-integrated analog neural network classifier architecture for low resolution image classification that eliminates memory access. We design custom activation functions using single-stage common-source amplifiers, and apply a hardware-software co-design methodology to incorporate knowledge of the custom activation functions into the training phase to achieve high accuracy. Performing all computations entirely in the analog domain eliminates energy cost associated with memory access and data movement. We demonstrate our classifier on multinomial classification task of recognizing downsampled handwritten digits from MNIST dataset. Fabricated in 65nm CMOS process, the measured energy consumption for down-sampled MNIST dataset is 173pJ/classification, which is 3× better than state-of-the-art. The prototype IC achieves mean classification accuracy of 81.3% even after down-sampling the original MNIST images by 96% from 28 × 28 pixels to 5 × 5 pixels.

This work presents a stochastic ring voltage controlled oscillator (VCO) based analog-to-digital converter (ADC) that combines spatial redundancy with staggered averaging to reduce both noise and distortion. Staggered averaging reduces quantization noise more than simple averaging with single clock phase for the same amount of spatial redundancy for VCO-ADCs. 4 continuous-time (CT) second-order VCO based sub-ADCs are run in parallel, and their outputs are sampled with multi-phase clocks followed by averaging to form the overall ADC output. We present behavioral simulation results and measurement results on 65nm CMOS test chip. Measurement results show staggered averaging improves SNR by an average of 7.6dB compared to single ADC. In contrast, simple averaging with 4 sub-ADCs can improve SNR by 6dB. The test chip consumes 0.36mW power and has SNDR of 63dB over 0.5MHz bandwidth.

This work presents a unified weak physical unclonable function (PUF) and a true random number generator (TRNG) based on the current-steering digital-to-analog converter (DAC) and ring voltage-controlled oscillator (VCO). Entropy source for the weak PUF is the mismatch between NMOS and PMOS transistors in a cascode current DAC as well as the mismatch between VCO quantizers, while entropy source for the TRNG is thermal noise in the DAC and VCO and clock jitter. Instead of using spatial entropy sources for the PUF, i.e., multiple unit PUF elements, the proposed architecture utilizes temporal entropy source by capturing the output of unit PUF element over multiple cycles, which reduces area significantly. A unified PUF/TRNG prototype is fabricated in 65-nm CMOS and consumes 0.36 pJ/bit at a throughput of 100 Mb/s. The PUF has a measured intra-HD of 0.0906 and inter-HD of 0.4859, while the raw TRNG bitstream has an entropy of 0.9991 and passes all the NIST statistical randomness tests.

In this paper, a wide dynamic range, current-mode four-quadrant analog multiplier circuit is proposed that utilizes MOS translinear principle. The proposed multiplier is designed in 65nm technology using CMOS transistors operating in weak inversion. A thorough analysis of the proposed design is performed using Spectre and monte-carlo simulations. The multiplier consumes a low power of 0.48μW and supports an input range of ±200nA while operating from 0.8V supply and exhibits an average total harmonic distortion (THD) 1.12%. Post layout simulation results show a high figure-of-merit (FoM) of 1302 verifying superiority of our design against other state-of-the-art multiplier circuits.

A second-order ΔΣ current-to-digital converter (CDC) for IoT sensing applications is presented in this paper. The proposed CDC uses pseudo-differential current-starved ring oscillators as phase domain integrators. A negative feedback loop relaxes input ring oscillator nonlinearity. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Digital differentiation using XOR implements an intrinsic first-order high-pass shaping of static element mismatch in the current steering digital-to-analog converter. A prototype CDC in 65nm CMOS process achieves 62dB dynamic range at 0.48pJ/conversion-step and has 20X better energy-efficiency than state-of-the-art.

An analog artificial neural network (ANN) classifier using a common-source amplifier based nonlinear activation function is presented in this work. A shallow ANN is designed using transistor level circuits and a multinomial (10 classes) classification accuracy of 0.82 is achieved on the MNIST dataset which consists of handwritten images of digits from 0-9. Use of common-source amplifier structure simplifies the ANN and results in 5X lower energy consumption than existing analog classifiers. The classifier performance is validated using Spectre and Matlab simulations.

Physically Unclonable Functions (PUFs) are extensively used in hardware security blocks as key-generators and light-weight authentication. With recent advances in machine learning (ML), most existing PUFs are shown to be vulnerable to modeling attacks based on ML algorithms. We present a novel silicon strong PUF architecture that cascades three strong PUFs to implement a single strong PUF that is resistant to ML based modeling attacks. Designed in 65nm CMOS technology, the proposed PUF with 260challenge response pairs consume 0.43pJ/bit energy consumption from a power supply of 0.8V. The simulated inter-HD and intra-HD of the PUF are 0.5065 and 0.0696 respectively. When subjected to ML based modeling attacks, the prediction accuracy is 60% for logistic regression, artificial neural networking and support vector machine with nonlinear RBF kernel.

Ring oscillators (ROs) are increasingly being used for ΔΣ ADC. This is because of the highly digital nature of ROs which makes them very amenable for design in scaled CMOS technologies. This work presents recent advances in RO based ΔΣ ADCs. In addition to being low power and scaling friendly, ring oscillators also possess intrinsic integration and quantization properties, which make them well suited for oversampling ADC applications. This work presents a review on both discrete-time and continuous-time ring oscillator based delta-sigma ADCs, as well as a novel second-order phase-locked loop (PLL)-like ring oscillator based ΔΣ ADC.

The effects of comparator input common-mode voltage Vcmare analyzed in this paper. The analysis clearly shows a trade-off in the choice of Vcmin terms of offset, noise, power and speed. Based on the analysis, an energy efficient SAR ADC switching technique is proposed with less Vcmvariation and better linearity compared with the widely used monotonic switching technique. Both the simulation results and prototype measured results match with the analysis.

This paper shows frequency dependence of switching energy of bottom-plate sampled successive approximation register (SAR) analog-to-digital converters (ADC) and presents a technique that achieves 86% reduction in switching energy compared to the conventional SAR over a wide frequency range. The switching energy has been calculated by taking into account both the power drawn from reference as well as the power consumed by the switches themselves. The results have been verified through MATLAB and SPICE simulations.

This paper presents an improved ISI shaping technique for multi-bit ΔΣ DACs. Compared to the prior ISI shaping method (Lars Risbo et al, JSSC, 2011) that monitors only the up (0 → 1) transitions, the proposed technique makes use of both the up and down (1 → 0) transitions with negligible hardware cost. It provides a finer control of the transition activity, thereby improving the ISI shaping effect. In addition, due to the tight coupling between the ISI and mismatch shaping loops, the proposed technique also improves the mismatch shaping result. Simulation results show that it can reduce ISI induced distortions by 10 dB compared to the prior ISI shaping technique and 50 dB compared to DWA.

This paper presents a simple but high performance architecture for multi-channel analog-to-digital conversion. Based on compressive sensing, only one SAR ADC is needed to convert multi-channel sparse inputs, leading to significant analog power saving and hardware saving. Moreover, it helps avoid problems occurring in conventional multi-channel ADCs such as timing skew, offset mismatch, and gain mismatch. A 12-bit SAR ADC converting 4-channel sparse signals simultaneously is designed in 130nm CMOS process. The design reaches a SNDR of 66.3dB and consumes an average power of 58μW at the sampling frequency of 1MHz. The L1minimization method is chosen to reconstruct the input signals. The single-tone and multi-tone inputs can be reconstructed with a minimum precision of 68dB and 55dB THD, respectively.

This paper presents an in-depth analysis of the generation of tones in the output spectra of vector-quantizer (VQ) based multibit mismatch-shaped ΔΣ digital-to-analog converters (DACs). Building upon the analysis, a simple yet elegant method of adding dither to remove tones from the output spectra is presented. It achieves a better mismatch shaping performance with a low hardware cost compared to existing dithering techniques.