This paper presents the design and applications of the Open-Source Circuit Radiation Effects (OSCRE) simulation framework. The framework addresses the challenges of simulating radiation effects in integrated circuits by providing a custom library of SPICE-compatible radiation simulation cells and a user-friendly interface based on open-source EDA tools. The radiation library can be easily configured by the circuit designer to model different behaviors of single-event effects (SEE) in a circuit, including double exponential, dual double exponential, and adaptive double exponential effects. We demonstrate the effectiveness and utility of OSCRE to simulate radiation effects in two example circuits: an SRAM cell and an op amp.

FPGAs have been shown to operate reliably within harsh radiation environments by employing single-event upset (SEU) mitigation techniques, such as configuration scrubbing, triple-modular redundancy, error correction coding, and radiation aware implementation techniques. The effectiveness of these techniques, however, is limited when using complex system-level designs that employ complex I/O interfaces with single-point failures. In previous work, a complex SoC system running Linux applied several of these techniques only to obtain an improvement of 14 \(\times\) in mean time to failure (MTTF). A detailed post-radiation fault analysis found that the limitations in reliability were due to the DDR interface, the global clock network, and interconnect. This article applied a number of design-specific SEU mitigation techniques to address the limitations in reliability of this design. These changes include triplicating the global clock, optimizing the placement of the reduction output voters and input flip-flops, and employing a mapping technique called “striping.” The application of these techniques improved MTTF of the mitigated design by a factor of 1.54 \(\times\) and thus provides a 22.8X \(\times\) MTTF improvement over the unmitigated design. A post-radiation fault analysis using BFAT was also performed to find the remaining design vulnerabilities.

FPGAs are increasingly being used in space and other harsh radiation environments. However, SRAM-based FPGAs are susceptible to radiation in these environments and experience upsets within the configuration memory (CRAM), causing design failure. The effects of CRAM upsets can be mitigated using triple-modular redundancy and configuration scrubbing. This work investigates the reliability of a soft RISC-V SoC system executing the Linux operating system mitigated by TMR and configuration scrubbing. In particular, this paper analyzes the failures of this triplicated system observed at a high-energy neutron radiation experiment. Using a bitstream fault analysis tool, the failures of this system caused by CRAM upsets are traced back to the affected FPGA resource and design logic. This fault analysis identifies the interconnect and I/O as the most vulnerable FPGA resources and the DDR controller logic as the design logic most likely to cause a failure. By identifying the FPGA resources and design logic causing failures in this TMR system, additional design enhancements are proposed to create a more reliable design for harsh radiation environments.

In harsh environments such as space, radiation and charged particles cause Single-Event Effects, faults occurring randomly on any electronic component. These must be mitigated to ensure device functionality. Modern mitigation methods, such as triple modular redundancy, are very effective against Single-Event Transients (SETs), but incur a minimum of$3\times $cost in area. Single-Event Upsets (SEUs) affect sequential elements and are regularly repaired using memory scrubbing. Scrubbing is a slow serial process, going through every memory word looking for errors to repair. It involves a non-negligible Time To Detect (TTD) before repair, during which other events can occur and compromise the system. Field Programmable Gate Arrays (FPGAs) rely heavily on sequential elements to store their configuration; thus, FPGA’s SEU detection time is critical to ensuring design integrity in harsh conditions. In this paper, we propose In-Memory Error Code Correction Checking (IMECCC), a method to replace memory scrubbing and improve FPGA configuration memory protection in high radiation environments. Our method allows asynchronous SEU detection, and replaces the scrubbing’s variable time to detect with a fixed TTD. We show that IMECCC reduces FPGA’s TTD by at least 116,$000\times $on average, with an area increase of$1.56\times $, using a test architecture resembling a Xilinx Virtex 5 QV at a 60MHz scrubbing frequency.

Field programmable gate arrays (FPGAs) are used in large numbers in data centers around the world. They are used for cloud computing and computer networking. The most common type of FPGA used in data centers are re-programmable SRAM-based FPGAs. These devices offer potential performance and power consumption savings. A single device also carries a small susceptibility to radiation-induced soft errors, which can lead to unexpected behavior. This article examines the impact of terrestrial radiation on FPGAs in data centers. Results from artificial fault injection and accelerated radiation testing on several data-center-like FPGA applications are compared. A new fault injection scheme provides results that are more similar to radiation testing. Silent data corruption (SDC) is the most commonly observed failure mode followed by FPGA unavailable and host unresponsive. A hypothetical deployment of 100,000 FPGAs in Denver, Colorado, will experience upsets in configuration memory every half-hour on average and SDC failures every 0.5–11 days on average.

This paper presents Maverick, a proof-of-concept computer-aided design (CAD) flow for generating reconfigurable modules (RMs) which target partial reconfiguration (PR) regions in field-programmable gate array (FPGA) designs. After an initial static design and PR region are created with Xilinx's Vivado PR flow, the Maverick flow can then compile and configure RMs onto that PR region—without the use of vendor tools. Maverick builds upon existing open source tools (Yosys, RapidSmith2, and Project X-Ray) to form an end-to-end compilation flow. This paper describes the Maverick flow and shows the results of it running on a PYNQ-Z1's ARM processor to compile a set of HDL designs to partial bitstreams. The resulting bitstreams were configured onto the PYNQ-Z1's FPGA fabric, demonstrating the feasibility of a single-chip embedded system which can both compile HDL designs to bitstreams and then configure them onto its own programmable fabric.

Traditionally, an FPGA vendor's own set of computer-aided design (CAD) tools are used to generate circuits for a given vendor's FPGAs. However, numerous non-vendor CAD tools have been introduced to supplement the vendor-provided tools, allowing novel ideas to be explored and a variety of technical challenges to be addressed. This poster presents Maverick, a stand-alone CAD flow for compiling Verilog to bitstreams for Xilinx 7-Series devices. After an initial configuration design is created with Xilinx's Vivado partial reconfiguration (PR) flow to define a static design and a PR region, the Maverick flow can then compile and map Verilog design into that PR region - without the use of vendor tools. The Maverick flow combines two existing open source projects (Yosys and Project X-Ray) with our own RapidSmith2 tools to form an end-to-end compilation flow. It uses Yosys (synthesis), RapidSmith2 (pack, place, route), and the Project X-Ray tools (bitstream generation), taking Verilog designs as input and generating partial bitstreams as output. Several modifications were made to these existing tools and completely new tools were created, including a new RapidSmith2-based router, as a part of this work. This poster details these CAD steps and shows the results of the CAD flow running on a PYNQ-Z1 SoC's ARM processor to compile a set of HDL designs to partial bitstreams. The resulting bitstreams were configured onto the PYNQ-Z1's FPGA fabric, demonstrating the feasibility of a single-chip system which can both compile HDL designs to bitstreams and then configure them onto its own fabric.

FPGAs are being used in large numbers within cloud computing to provide high-performance, low-power alternatives to more traditional computing structures. While FPGAs provide a number of important benefits to cloud computing environments, they are susceptible to radiation-induced soft errors, which can lead to silent data corruption or system instability. Although soft errors within a single FPGA occur infrequently, soft errors in large-scale FPGAs systems can occur at a relatively high rate. This paper investigates the failure rate of several FPGA applications running within an FPGA cloud computing node by performing fault injection experiments to determine the susceptibility of these applications to soft-errors. The results from these experiments suggest that silent data corruption will occur every few hours within a 100,000 node FPGA system and that such a system can only maintain high-levels of reliability for short periods of operation. These results suggest that soft-error detection and mitigation techniques may be needed in large-scale FPGA systems.

TMR combined with configuration scrubbing is an effective technique to mitigate against radiation-induced CRAM upsets on SRAM-based FPGAs. However, its effectiveness is limited by low-level common mode failures due to the physical mapping of a design to the FPGA device. This paper describes how common mode failures are introduced during the implementation process and introduces an approach for resolving them through a custom incremental placement tool for Xilinx 7-Series FPGAs. Multiple designs across multiple generations of devices are shown to be sensitive to common mode failures. Applying the incremental placement technique yields an improvement of 10,721x over an unmitigated design through fault-injection testing. Radiation testing is then performed to show that the of this technique is 91,500 days in GEO orbit, a 367x improvement over the unmitigated design and a 5x improvement over baseline TMR.

Undergraduate students rapidly implement a partially-reconfigured, real-time video processor on the Xilinx PYNQ board. The video processor performs various real-time operations including Sobel edge detection, embossing, averaging, an interactive Pong game, etc., using a separate partially-reconfigurable bit-stream for each distinct function. Selection of image-processing functions is accomplished by a Python-based graphical user interface that is accessed via a Jupyter notebook. As users select image-processing functions the appropriate partial bit-stream is automatically downloaded to the FPGA. The resulting system is easily and quickly developed by several undergraduate students over a period of about 10 weeks with very little supervision. All files related to the project are available for download on GitHub. The productivity benefits provided by PYNQ, including Jupyter-based documentation, tutorials, and executable Python code greatly ease development effort making PYNQ an excellent FPGA platform for education.

Processors are an essential component in most satellite payload electronics and handle a variety of functions including command handling and data processing. There is growing interest in implementing soft processors on commercial FPGAs within satellites. Commercial FPGAs offer reconfigurability, large logic density, and I/O bandwidth; however, they are sensitive to ionizing radiation and systems developed for space must implement single-event upset mitigation to operate reliably. This paper investigates the improvements in reliability of a LEON3 soft processor operating on a SRAM-based FPGA when using triple-modular redundancy and other processor-specific mitigation techniques. The improvements in reliability provided by these techniques are validated with both fault injection and heavy ion radiation tests. The fault injection experiments indicate an improvement of 51× and the radiation testing results demonstrate an average improvement of 10×. Orbit failure rate estimations were computed and suggest that the TMR LEON3 processor has a mean-time to failure of over 76 years in a geosynchronous orbit.

Over the past few decades, the use of reconfigurable computing for aerospace applications has become increasingly common despite its sensitivity to ionizing radiation. Tools are needed to test and implement fault-mitigation mechanisms to increase the reliability of FPGAs in space. This paper introduces a tool called the JTAG Configuration Manager (JCM) that provides high-speed programmable access to the configuration memory of Xilinx FPGAs using the JTAG serial protocol. The JCM consists of a linux-based software library running on an embedded ARM processor paired with a hardware state machine implemented in programmable logic. Two important uses of the JCM are configuration scrubbing and fault injection. The high-speed JTAG interface allows such operations to run at up to 60 MHz, which is several times faster than traditional JTAG FPGA configuration methods. The JCM also has access to the XADC on-chip temperature monitoring and the internal Boundary SCAN, making it useful for many testing and debugging applications.

This paper describes a tightly integrated phased-array radar platform for a UAV-based sense and avoid application. The system leverages heterogeneous computing on a Zynq 7000 SoC processor to efficiently process the large streams of radar data required to guide a small Unmanned Air Vehicle (UAV) away from obstacles and intruding air vehicles. The system is mounted on a small UAV which requires stringent size, weight, and power constraints, and thus data processing must be done efficiently. The system is implemented on the commercial MicroZed development board. Low-level radar data-stream processing is performed in the FPGA fabric on the Zynq, which accelerates processing and improves energy efficiency. The Zynq ARM CPUs are used to perform higher-level radar processing and avoidance algorithms. The final proof of concept system is 2.25 × 4 × 1.5 in3weighing only 120 g (0.26 lbs) and consumes 8 watts of power. As an example, the improvements demonstrated by executing the FFT algorithm in hardware will be highlighted where hardware FFT processing provides a 17× improvement in processing time and a 49× improvement in energy efficiency over a CPU only implementation on the same SoC.

Configuration scrubbing is a technique used for repairing Single Event Upsets (SEUs) within the configuration memory of an FPGA. Scrubbing approaches have been developed using hardware external to the FPGA communicating through a configuration port and using hardware within the FPGA by communicating with an internal configuration port (ICAP). More recent FPGAs such as the Xilinx Zynq 7-Series SoCs provide internal programmable processors that can configure the FPGA logic very rapidly using an internal Processor Configuration Access Port (PCAP). These SoC/FPGAs also provide automatic internal scrubbing through the use of high-speed readback and configuration error correction. This paper presents a novel form of FPGA configuration scrubbing for the Zynq-7000 SoC family by combining the high-speed PCAP configuration port with internal scrubbing. This novel scrubber corrects single-bit upsets in several microseconds and detects these upsets in 8 ms.

In recent years, the RapidSmith CAD tool [1] has been used with ISE to create custom CAD tools targeting Xilinx FPGAs. This tool flow was based on the Xilinx Design Language (XDL), a human-readable representation of a netlist that contains placement and routing information. The XDL interface also provided device representation files (XDLRC files), detailing the available resources of a given FPGA part. Using RapidSmith, a Xilinx design could be exported out of ISE at any stage of the design flow, manipulated in RapidSmith (logic modification, place, or route), and imported back into ISE to complete the remainder of implementation.

Soft processors are increasingly used on SRAM-based FPGAs for reliable computing systems. In a radiation environment like space, the configuration memory used to configure a soft processor is sensitive to single event upsets (SEUs). Tools are needed to evaluate and estimate the reliability of soft processors in these environments. Fault injection is used to evaluate the configuration memory sensitivity of soft processor designs. This paper describes our fault injection experiments and the sensitivity results on each soft processor experiment. A suite of five benchmarks were executed on the MicroBlaze soft processor to measure the sensitivity of the processor to the software being executed. In addition, several soft processors were evaluated on a Virtex-5 FPGA: Micro Blaze, LEON3, Arm Cortex-M0, Open RISC, and Pico Blaze. For the software benchmarks, we find that the sensitivity varies as much as 54%. For simple processor configurations running the Towers of Hanoi benchmark, we measure as low as 7,116 sensitive bits for the Pico Blaze, and as high as 112,223 sensitive bits for the Cortex M0.

Field-programmable gate arrays (FPGAs) have been shown to provide high computational density and efficiency for many computing applications by allowing circuits to be customized to any application of interest. FPGAs also support programmability by allowing the circuit to be changed at a later time through reconfiguration. There is great interest in exploiting these benefits in space and other radiation environments. FPGAs, however, are very sensitive to radiation and great care must be taken to properly address the effects of radiation in FPGA-based systems. This paper will highlight the effects of radiation on FPGA-based systems and summarize the challenges in deploying FPGAs in such environments. Several well-known mitigation methods will be described and the unique ability of FPGAs to customize the system for improved reliability will be discussed. Finally, two case studies summarizing successful deployment of FPGAs in radiation environments will be presented.

Over the past 15 years many organizations have researched the use of Static-Random Access Memory (SRAM)-based Field-Programmable Gate Arrays (FPGAs) in space. Although the components can provide a performance improvement over radiation-hardened processing components, random soft errors can occur from the naturally occurring space radiation environment. Many organizations have been developing methods for characterizing, emulating, and simulating radiation-induced events; mitigating and removing radiation-induced computational errors; and designing fault-tolerant reconfigurable spacecraft. Los Alamos National Laboratory has fielded one of the longest space-based FPGAs experiments, called the Cibola Flight Experiment (CFE), using Xilinx Virtex FPGAs. CFE has successfully deployed commercial SRAM FPGAs into a low-Earth orbit with Single-Event Upset (SEU) mitigation and was able to exploit effectively the reconfigurability and customization of FPGAs in a harsh radiation environment. Although older than current state-of-the-art FPGAs, these same concepts are used to deploy newer FPGA-based space systems since the launch of the CFE satellite and will continue to be useful for newer systems. In this article, we present how the system was designed to be fault tolerant, prelaunch predictions of expected on-orbit behaviors, and on-orbit results.

Recent developments in High-Level Synthesis (HLS) for FPGAs are making it possible to “run” C code on FPGAs thereby making modern programming environments available to FPGA developers. In this paper, C code for a complex optical-flow algorithm is optimized for both a desktop PC and for an FPGA-based system, the Xilinx Zynq-7000, a device containing both a programmable fabric and two ARM cores. The paper discusses how the code is optimized and restructured to execute effectively on the programmable fabric and the ARM cores. The resulting Zynq version of the C code is competitive with the desktop PC but only consumes 1/7th as much energy.

With the growing density and shrinking feature size of modern semiconductors, it is increasingly difficult to manufacture defect free semiconductors that maintain acceptable levels of reliability for long periods of time. These systems are increasingly susceptible to wear-out by failing to meet their operational specifications for an extended period of time. The reconfigurability of FPGAs can be used to repair post-manufacturing faults by configuring the FPGA to avoid a damaged resource. This paper presents a method for repairing FPGA devices with wear-out faults by precomputing a set of repair circuits that, collectively, can repair a fault found in any logic block of the FPGA. This approach relies on logic placement to create "repair" circuits that avoid specific logic blocks. Three repair placement algorithms will be presented that generate a complete set of repair designs during the conventional placement process. The number of repairs needed to create a complete repair set depends heavily on the utilization of the FPGA resources. The three algorithms are tested against several benchmarks and with multiple area constraints for each benchmark. The best repair placement approach described in the paper generates a full set of repair circuits at a computation cost of 16X that of a conventional placer and with circuits of comparable quality.

Softcore processors are an attractive alternative to using radiation-hardened processors in space-based applications. Unlike traditional processors however, the logic and routing of a softcore processor are vulnerable to the effects of single-event upsets (SEUs). This paper applies two common SEU mitigation techniques, TMR with checkpointing and DWC with checkpointing, to the LEON3 softcore processor. The improvement in reliabilty over an unmitigated version of the processor is measured using three metrics: the architectural vulnerability factor (AVF), mean time to failure (MTTF), and mean useful instructions to failure (MuITF). Using configuration memory fault injection, we found that DWC with checkpointing improves the MTTF and MuITF by over 35x, and that TMR with triplicated input and outputs improves the MTTF and MITF by over 6000x.

Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems that employ configuration scrubbing, majority voters are needed in all feedback paths to ensure proper synchronization between the TMR replicates. Synchronization voters, however, consume additional resources and impact system timing. This paper will introduce and contrast four algorithms for inserting synchronization voters while automatically performing TMR. The area cost and timing impact of each algorithm on a number of circuit benchmarks will be reported. This paper will demonstrate that one of the algorithms provides the best overall timing performance results with an average 9.8% increase in critical path length over a triplicated design without voters. Another algorithm provides far better area results at a slightly higher timing cost (an average 2.1% area increase over a triplicated design without voters).

"Open Source", ubiquitous in the software community, has grown to become vital in application domains served by reconfigurable computing. But what exactly is "Open Source", and what are the values and pitfalls it brings? This workshop draws together technologists from academia and industry to share their experiences, opinions, and lessons learned.

This paper presents a novel IP core reuse strategy which reduces design time from days to hours for communication circuits such as digital radio receivers. This design productivity is obtained by leveraging a highly parameterized library of communication specific cores. These cores are described in IP-XACT XML with vendor extensions describing the timing behavior of their communication interfaces. A synthesis tool, called Ogre, was created that generates the communication interfaces between cores described in IP-XACT and synthesizes full designs from structural synchronous dataflow specifications. Design productivity improvements are demonstrated with several radio receiver designs.

The FPGA compilation process (synthesis, map, placement, routing) is a time-consuming process that limits designer productivity. Compilation time can be reduced by using pre-compiled circuit blocks (hard macros). Hard macros consist of previously synthesized, mapped, placed and routed circuitry that can be relatively placed with short tool runtimes and that make it possible to reuse previous computational effort. Two experiments were performed to demonstrate feasibility that hard macros can reduce compilation time. These experiments demonstrated that an augmented Xilinx flow designed specifically to support hard macros can reduce overall compilation time by 3x. Though the process of incorporating hard macros in designs is currently manual and error-prone, it can be automated to create compilation flows with much lower compilation time.

Reconfigurable radios implemented on FPGAs operating in high-radiation environments are subject to single-event- upsets (SEUs). The traditional mitigation method of applying triple modular redundancy (TMR) to the entire design does not have to be used in this application. This is because the majority of the SEUs impact the overall performance (measured by bit error rate) in the same way additive noise does. The results of this paper show which sections must be protected from SEUs and provide a guide for the bit error rate performance versus FPGA area tradeoff as a function of SEU mitigation.

The Cibola Flight Experiment (CFE) is an experimental small satellite developed at the Los Alamos National Laboratory to demonstrate the feasibility of using FPGA-based reconfigurable computing for sensor processing in a space environment. The CFE satellite was launched on March 8, 2007 in low-earth orbit and has operated extremely well since its deployment. The nine Xilinx Virtex FPGAs used in the payload have been used for several high-throughput sensor processing applications and for single-event upset (SEU) monitoring and mitigation. This paper will describe the CFE system and summarize its operational results. In addition, this paper will describe the results from several SEU detection circuits that were performed on the spacecraft.

Reconfigurable computing systems remain difficult to use and program. One way to increase design productivity for these systems is through reuse of previously developed and verified intellectual property (IP) cores. This paper presents CHREC XML, a XML schema that facilitates IP reuse by encapsulating the details of reusable IP cores at multiple levels of abstraction. This schema is independent from any design language or tool and can be used by any tool to understand many details about the interface of a reusable circuit. An IP integration tool was also created based on this schema to demonstrate the ease of IP reuse when cores are described in this meta-data description. This IP integration tool allows a designer to easily select and integrate IP cores from a variety of languages/tools and automatically run the appropriate tools to generate the cores in a form usable by downstream implementation tools.

SRAM-based FPGA devices are susceptible to single event effects (SEE) including single event upsets (SEU) within the configuration memory. Configuration scrubbing along with TMR or other hardware redundancy techniques are often used to mitigate the effects of these SEUs. However, the use of traditional configuration scrubbing prevents the ability to reconfigure the FPGA dynamically or to perform partial reconfiguration. This paper presents a novel technique that allows partial reconfiguration to be used with configuration scrubbing. A self scrubber, utilizing a small portion of the FPGA, performs the necessary operations to reconfigure a portion of the design while continuously scrubbing the entire FPGA.

Field-programmable gate arrays are well-suited to DSP and digital communications applications. SRAM-based FPGAs, however, are susceptible to radiation-induced single-event upsets (SEUs) when deployed in space environments. These effects are often handled with the area and power-intensive TMR mitigation technique. This paper evaluates the effects of SEUs in the FPGA configuration memory as noise in a digital filter, showing that many SEUs in a digital communications system cause effects that could be considered noise rather than circuit failure. Since DSP and digital communications applications are designed to withstand certain types of noise, SEU mitigation techniques that are less costly than TMR may be applicable. This could result in large savings in area and power when implementing a reliable system. Our experiments show that, of the SEUs that affected the digital filter with a 20 dB SNR input signal, less than 14% caused an SNR loss of more than 1 dB at the output.

As FPGA logic density continues to increase, new techniques are needed to store initial configuration data efficiently, maintain usability, and minimize cost. In this paper, a novel compression technique is presented for Xilinx Virtex partially reconfigurable FPGAs. This technique relies on constrained hardware design and layout combined with a few simple compression techniques. This technique uses partial reconfiguration to separate a hardware design into two separate regions: a static and partial region. A bitstream containing only the static region is then compressed by removing empty frames. This bitstream will be stored in non-volatile memory and used for initialization. The remaining logic is configured through partial reconfiguration over a communication network. By applying this technique, a high level of compression was achieved (almost 90% for the V4 LX25). This compression technique requires no extra decompression circuitry and compression levels improve as device size increases.

There are several interesting compilation tools on the market for synthesizing FPGA circuits from "high" level languages. These tools advertise the ability to generate high-quality FPGA circuits from a variety of specification formats such procedural languages (C, Fortran, etc.), modeling languages (SystemC), or from signal flow graphs. These tools claim significant improvements in design productivity by allowing the designer to operate at higher levels of abstraction than available with traditional RTL-level synthesis.Some claim that these high-level tools will completely change the way we design FPGAs. Those with this view believe that these tools will replace today's design approaches and VHDL/Verilog design will "wither away" like assembly language programming. They believe that the FPGA designer of the future will only need basic programming skills to create a high-quality FPGA designs. The arcane RTL design methodology used today will be a thing of the past. Others believe that these tools are just another fad in the long line of failed high-level design tools. They suggest that procedural languages like C are ill-suited to express the fine-grain parallelism available in hardware. Further, the synchronization/timing semantics needed to implement parallel hardware are not available. Perhaps of most concern to those in this camp is the lower quality circuits synthesized by these tools. What good is a high-level tool if it can't meet your timing or performance constraint? If high-level tools are successful, those with this view believe they will be limited to small niche markets with limited appeal to the average designer.What is the future of FPGA design? Will higher-level design tools finally provide the productivity and quality that has been promised? Or, are these tools just another passing fad? This panel will address these questions and discuss the future FPGA design. The panel will include experts from a variety of perspectives including representatives from high-level tool vendors, FPGA manufacturers, and experienced designers. Each panelist will give a brief summary of their views on this topic, followed by questions and lively debate. Audience participation is actively encouraged and audience members will have the opportunity for asking questions and making statements.

The primary goal during synthesis of digital signal processing (DSP) circuits is to minimize the hardware area while meeting a minimum throughput constraint. In field-programmable gate array (FPGA) implementations, significant area savings can be achieved by using slower, more area-efficient circuit modules and/or by time-multiplexing faster, larger circuit modules. Unfortunately, manual exploration of this design space is impractical. In this paper, we introduce a design exploration methodology that identifies the lowest cost FPGA pipelined implementation of an untimed synchronous data-flow graph by combined module selection with resource sharing under the context of pipeline scheduling. These techniques are applied together to minimize the area cost of the FPGA implementation while meeting a user-specified minimum throughput constraint. Two different algorithms are introduced for exploring the large design space. We show that even for small DSP algorithms, combining these techniques can offer significant area savings relative to applying any of them alone

This paper introduces the low-power intelligent tool environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization. These tools leverage an established FPGA design environment, JHDL, that allows design logic and power utilization to be displayed, analyzed, and cross-probed simultaneously at a level of abstraction close to the design entry point. Circuit logic, FPGA architecture and power information are correlated to create accurate power prediction and estimation models. These models and power analysis tools can then be used to create power optimization algorithms. Power optimization algorithm development is supported through the use of tools to query and sort circuit characteristics and drop in COTS CAD tool compliant constraints. These constraints can be used to guide the COTS placement and routing tools to optimize for power

A synthesis environment called DSynth has been created for synthesizing high-performance pipelined circuits for FPGAs from synchronous data flow specifications. The goal of this work is to generate the minimum size circuit that meets the throughput constraint of the data flow model. To achieve this constraint efficiently, this approach relies heavily upon a library of pre-characterized pipelined circuit modules. In addition, resource sharing is used extensively to reduce the overall hardware cost

In FPGA designs significant area savings can be achieved by using slower, more area-efficient circuit modules or by time-multiplexing faster circuit modules. Unfortunately, the ability of designers to manually make such trade-offs is limited by the large number of different architectural possibilities. In order to automatically perform these trade-offs, we have developed a synthesis methodology that generates pipelined data-path circuits from a high-level data-flow specification. This methodology is capable of selecting among a variety of circuit implementations for each operation, a synthesis technique often called module selection, and generating control logic to time multiplexing each circuit module, a synthesis technique often called resource sharing. These techniques are applied together to minimize the area cost of the resulting circuit while meeting a user-specified minimum throughput constraint. We show that even for small benchmark circuits, combining these techniques can offer significant area savings relative to applying them alone.

In this paper we outline a methodology and tool suite capable of modeling the power consumption of an FPGA design at the post synthesis, or EDIF, level. Modeling at this level has the following advantages: 1) early power feedback in the design flow, 2) power results displayed at a high level, closer to the logical design entry point 3) and the elimination of bulky, low-level timing accurate simulation and stimulus files. These three aspects allow a designer to quickly and easily generate power estimates, relate the results back to their original logical level design entry, and explore design trade-off scenarios. The results presented here were derived using Xilinx Virtex2 FPGAs and tool suites, however the techniques apply to all FPGAs.

Triple-modular redundancy has been proposed as a technique for improving the reliability of FPGA circuits in the presence of radiation-induced SEUs. This technique masks circuit faults by voting on the output of three identical circuit modules. A critical design decision in any TMR system is the placement of voters between the TMR modules. This paper presents a technique for selecting the appropriate location of voters within feedback paths of an FPGA circuit. Voting within the feedback path will repair corrupted state variables and tolerate online repair of the FPGA configuration.

Summary form only given. We describe novel methods of exploiting the partial, dynamic reconfiguration capabilities of Xilinx Virtex 1000 FPGAs to manage transient faults due to radiation in space environments. The on-orbit fault detection scheme uses a radiation-hardened reconfiguration controller to continuously monitor the configuration bit streams of 9 Virtex FPGAs and to correct errors by partial, dynamic reconfiguration of the FPGAs while they continue to execute. To study single event upset (SEU) impact on our signal processing applications, we use a novel fault injection technique to corrupt configuration bits, thereby simulating SEU faults. By using dynamic reconfiguration, we can run the corrupted designs directly on the FPGA hardware, giving many orders of magnitude speed-up over purely software techniques. The fault injection method has been validated against proton beam testing, showing 97.6% agreement. Our work highlights the benefits of dynamic reconfiguration for space-based reconfigurable computing.

FPGAs are an appealing solution for space-based remote sensing applications. However, in a low-Earth orbit, FPGAs (field programmable gate arrays) are susceptible to Single-Event Upsets (SEUs). In an effort to understand the effects of SEUs, an SEU simulator based on the SLAAC-1V computing board has been developed. This simulator artificially upsets the configuration memory of an FPGA and measures its impact on FPGA designs. The accuracy of this simulation environment has been verified using ground-based radiation testing. This simulation tool is being used to characterize the reliability of SEU mitigation techniques for FPGAs.

This paper introduces an IP evaluation and delivery framework that operates within Java applets. The use of such applets allows circuit designers to create, evaluate, test, and obtain FPGA circuits directly within a Web browser. Based on the JHDL design tool, these applets allow structural viewing, circuit simulation, and netlist generation of application-specific circuits. An important component of this framework is the ability to deliver black-box simulation models as executable Java applets. These applet-based simulation models can be tied to third-party simulation tools using network sockets. Several techniques for interfacing black-box applet models to external simulators are described.

This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain FPGA circuits directly within a web browser. Based on the JHDL design tool, these applets allow structural viewing, circuit simulation, and netlist generation of application-specific circuits. Applets can be customized to provide varying levels of IP visibility and functionality as needed by both customer and vendor.

An adaptive amplification operation has been designed and tested in configurable hardware for a computationally intensive object recognition system. This configurable system provides over forty-one times the throughput of an industry-standard embedded processor by exploiting the bandwidth of internal block memories and parallelism within the algorithm. Operating at less than one half the power of the programmable processor, the configurable approach performs the computation with 90 times less energy. The improvements in both performance and power are obtained by customizing the datapath, memory interfaces, and control to the amplification algorithm.

No abstract available.

The ability to provide flexibility and allow fine-grain circuit specialization make field programmable gate arrays (FPGA's) ideal candidates for computing elements within application-specific architectures. The benefits of gate-level specialization and reconfigurability can be extended by reconfiguring circuit resources at run-time. This technique, termed run-time reconfiguration (RTR), allows the exploitation of dynamic conditions or temporal locality within application-specific problems. For several applications, this technique has been shown to reduce the hardware resources required for computation. The use of this technique on conventional FPGA's, however, requires additional time for circuit reconfiguration. A functional density metric is introduced that balances the advantages of RTR against its associated reconfiguration costs. This metric is used to justify run-time reconfiguration against other more conventional approaches. Several run-time reconfigured applications are presented and analyzed using this approach.

Circuit specialization techniques such as constant propagation are commonly used to reduce both the hardware resources and cycle time of digital circuits. When reconfigurable FPGAs are used, these advantages can be extended by dynamically specializing circuits using run-time reconfiguration (RTR). For systems exploiting constant propagation, hardware resources can be reduced by folding constants within the circuit and dynamically changing the constants using circuit reconfiguration. To measure the benefits of circuit specialization, a functional density metric is presented. This metric allows the analysis of both static and run-time reconfigured circuits by including the cost of circuit reconfiguration. This metric will be used to justify runtime constant propagation as well as analyze the effects of reconfiguration time on run-time reconfigured systems.

No abstract available.

A dynamic instruction set computer (DISC) has been developed that supports demand-driven modification of its instruction set. Implemented with partially reconfigurable FPGAs, DISC treats instructions as removable modules paged in and out through partial reconfiguration as demanded by the executing program. Instructions occupy FPGA resources only when needed and FPGA resources can be reused to implement an arbitrary number of performance-enhancing application-specific instructions. DISC further enhances the functional density of FPGAs by physically relocating instruction modules to available FPGA space.