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EDBT 2026 Demo / reviewers in the wild / expert

Joseph C. Werbickas

dblp:52/868 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 1984
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 92% Integrated circuit design · 4% Reconfigurable computing and FPGAs · 4%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design		 0.021984
The Variable Geometry Automated Universal Array Layout System (VGAUA) · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1984
VGAUA: The Variable Geometry Automated Universal Array layout System · DAC 1983
Electronic design automation › physical design › placement and routing
gate array layout		 0.011984
The Variable Geometry Automated Universal Array Layout System (VGAUA) · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1984
Electronic design automation › physical design
layout automation		 0.011984
The Variable Geometry Automated Universal Array Layout System (VGAUA) · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1984
Electronic design automation
logic synthesis		 0.011983
APSS: An automatic PLA synthesis system · DAC 1983
Electronic design automation › logic synthesis › programmable logic array
programmable logic array design		 0.011983
APSS: An automatic PLA synthesis system · DAC 1983
Electronic design automation › physical design
VLSI layout		 0.011983
VGAUA: The Variable Geometry Automated Universal Array layout System · DAC 1983
Reconfigurable computing and FPGAs › FPGA physical design
FPGA layout		 0.011983
VGAUA: The Variable Geometry Automated Universal Array layout System · DAC 1983

Methods — techniques the papers use, named apart from their topics

metallization personalization · 0.0
YearPublicationVenuePosition
1984 The Variable Geometry Automated Universal Array Layout System (VGAUA)
abstract
This paper presents the Variable Geometry Automated Universal Array (VGAUA) fully automatic physical layout program for gate array LSI which uses a single unique metallization pattern to personalize the array design. This fully automatic layout system minimizes the cost and time required for IC design and can be used over a range of array sizes from 800 to 3500 gates. Each array size has its own unique, optimized, fixed geometry design for all levels except the programmable metallization level.
David C. Smith, Richard Noto, Fred Borgini, Shanti S. Sharma, Joseph C. Werbickas
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.5
1983 VGAUA: The Variable Geometry Automated Universal Array layout System
David C. Smith, Richard Noto, Fred Borgini, Shanti S. Sharma, Joseph C. Werbickas
 DAC5
1983 APSS: An automatic PLA synthesis system
M. W. Stebnisky, M. J. McGinnis, Joseph C. Werbickas, Rathin Putatunda, A. Feller
 DAC3