With the increase of devices connected to 5G services, the importance of tuning User Equipment (UE) to their assigned frequency slot becomes increasingly vital. This paper approached this issue by securing the control signals sent through a Serial Peripheral Interface (SPI) in digital beamforming radios. This was done by securing three distinct components: the transmitting end of the channel, the transmission medium, and the receiving end of the channel. To secure the transmitter, a module was created that monitors transmitted messages to ensure correct operation. For the security of the transmission medium, a comparison study was performed between different error detecting and correcting algorithms against the authors' own solution comparing which alternatives were more effective at reducing the errors on a transmission line. For the receiving end, a dynamic lock-and-key system was implemented to make sure that the radios know that they are connected to a legitimate device. These three components were simulated and evaluated individually to ensure that each one provided its part of the secure system, and a post-synthesis simulation of a system with all three solutions was then performed to show that these aspects together can create a cohesive secure system.

Semiconductors use on-chip components, referred to as instruments, for test, debugging, firmware programming, configuration and other important functions. The instruments are needed to ensure proper device operation, however, they may be exploited by an adversary in an attack. Many different actors are involved in semiconductor development and manufacturing, this makes it important to restrict access to instruments which should not be available for all users.In this paper, we propose an authenticated instrument sharing scheme, which makes instruments available for some users while remaining hidden and inaccessible for others. Also protecting users against inside threats, like hardware trojans, in third party instruments in the device. The scheme is implemented for instrument access within an IEEE Std. 1687 (IJTAG) network, which is a frequently used standard for on-chip instrument access and integration. When deployed, our solution is (1) secure, as users are only able to access instruments they are authorized to use, other instruments remain hidden, and (2) efficient, as all of the user’s instruments will be directly accessible through the IJTAG network, after a one-step authentication process, with no additional access time overhead. We demonstrate our solution with a use case.

A variable gain transimpedance amplifier (TIA) is presented featuring single-ended to differential conversion by means of negative feedback. The proposed topology also ensures stability when amplifier gain is varied. Furthermore, effective input capacitance of the TIA is reduced by using a positive capacitive feedback. The circuit is intended for intermediate frequency (IF) over fiber systems, but can be readily adapted for other applications. When simulated with a photodiode capacitance of 1.4 pF, the TIA exhibits a tunable gain range of 51 to 73dBΩ with a bandwidth of 550 MHz. The circuit designed in a standard 65nm CMOS process consuming 4mA from a 1.2V supply, achieves a spurious free dynamic range (SFDR) of 109dB·Hz2/3at 100 MHz.

In this paper, design and measurements of a fully integrated power amplifier (PA) are presented. The PA consists of two amplifying chains each having a driver and a power stage. A low loss on chip power combiner combines the outputs from two amplifying chains, and also performs impedance transformation and differential to single-ended conversion. To linearize the PA, the driver stage is biased in class-C, acting as a pre-distorter for the power stage which is biased in class-AB. The linearization scheme is validated by measurements, improving the third order intermodulation distortion (IMD3) by 7dB, output referred 1-dB compression point by 4dB, and adjacent channel leakage ratio (ACLR) by 4.5 dB. With a supply voltage of 2.2V, the PA delivers a saturated output power of 26.1 dBm with a power added efficiency (PAE) of 26.8% at operating frequency of 2.24 GHz. The measured power gain of the PA is 21.8 dB, and the output referred 1-dB compression point is 25.4 dBm. The ACLR1 (5 MHz offset) is better than -33 dBc while transmitting a 23dBm WCDMA signal. The circuit is manufactured in a standard 65nm CMOS process and occupies 1mm2of chip area.