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Chi-Chih Chang

dblp:53/1921 · DBLP profile ↗
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10ranked-venue papers
2as first author
9since 2021 · last 2026
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 5 · 1 first-author · 5 since 2021Systems, architecture and hardware · 3 · 3 since 2021Graphics, computer vision, multimedia, augmented reality and games · 2 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Artificial intelligence
7 papers
Efficient and distributed learning · 89% Deep learning architectures and training · 7% Language models and text generation · 3%
Computer architecture, parallel and distributed computing, and storage systems
3 papers
Hardware accelerators and domain-specific architectures · 77% Reconfigurable computing and FPGAs · 17% Processor architecture and microarchitecture · 6%

Topics — the 21 heaviest of 22, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Machine learning › Efficient and distributed learning
model compression
5.462026
Bit-Serial Acceleration of LLM Inference With Mixture-of-Datatype Quantization · IEEE Trans. Computers 2026
Speculate Deep and Accurate: Lossless and Training-Free Acceleration for Offloaded LLMs via Substitute Speculative Decoding · NeurIPS 2025
Quamba2: A Robust and Scalable Post-training Quantization Framework for Selective State Space Models · ICML 2025
Machine learning › Efficient and distributed learning › model compression › quantization
post-training quantization
1.722025
Quamba2: A Robust and Scalable Post-training Quantization Framework for Selective State Space Models · ICML 2025
Quamba: A Post-Training Quantization Recipe for Selective State Space Models · ICLR 2025
Machine learning › Efficient and distributed learning › model compression
quantization
1.012026
Bit-Serial Acceleration of LLM Inference With Mixture-of-Datatype Quantization · IEEE Trans. Computers 2026
Hardware accelerators and domain-specific architectures › machine learning accelerator › transformer accelerator
LLM inference accelerator
1.012026
Bit-Serial Acceleration of LLM Inference With Mixture-of-Datatype Quantization · IEEE Trans. Computers 2026
Hardware accelerators and domain-specific architectures
machine learning accelerator
1.012026
Bit-Serial Acceleration of LLM Inference With Mixture-of-Datatype Quantization · IEEE Trans. Computers 2026
Machine learning › Efficient and distributed learning
inference acceleration
0.912025
Speculate Deep and Accurate: Lossless and Training-Free Acceleration for Offloaded LLMs via Substitute Speculative Decoding · NeurIPS 2025
Machine learning › Efficient and distributed learning
inference efficiency
0.912025
Palu: KV-Cache Compression with Low-Rank Projection · ICLR 2025
Machine learning › Efficient and distributed learning › KV cache management
KV cache compression
0.912025
Palu: KV-Cache Compression with Low-Rank Projection · ICLR 2025
Machine learning › Efficient and distributed learning › model compression
low-rank approximation
0.912025
FLRC: Fine-grained Low-Rank Compressor for Efficient LLM Inference · EMNLP 2025
Machine learning › Efficient and distributed learning
low-rank projection
0.912025
Palu: KV-Cache Compression with Low-Rank Projection · ICLR 2025
Machine learning › Efficient and distributed learning › inference acceleration
speculative decoding
0.912025
Speculate Deep and Accurate: Lossless and Training-Free Acceleration for Offloaded LLMs via Substitute Speculative Decoding · NeurIPS 2025
Machine learning › Deep learning architectures and training
state space model
0.912025
Quamba2: A Robust and Scalable Post-training Quantization Framework for Selective State Space Models · ICML 2025
Reconfigurable computing and FPGAs
FPGA architecture
0.912025
Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration · FPGA 2025
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator
0.912025
Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration · FPGA 2025
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
sparse neural network acceleration
0.912025
Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration · FPGA 2025
Processor architecture and microarchitecture › computer arithmetic
bit-serial arithmetic
0.312026
Bit-Serial Acceleration of LLM Inference With Mixture-of-Datatype Quantization · IEEE Trans. Computers 2026
Natural language and speech › Language models and text generation
large language model
0.312025
Quamba: A Post-Training Quantization Recipe for Selective State Space Models · ICLR 2025
Natural language and speech › Language models and text generation
large language model inference
0.312025
FLRC: Fine-grained Low-Rank Compressor for Efficient LLM Inference · EMNLP 2025
Machine learning › Efficient and distributed learning › model compression
sparse neural network
0.312025
Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration · FPGA 2025
Machine learning › Efficient and distributed learning › model compression › sparsity
structured sparsity
0.312025
Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration · FPGA 2025
Machine learning › Deep learning architectures and training › attention mechanism
transformer attention
0.312025
Palu: KV-Cache Compression with Low-Rank Projection · ICLR 2025

Methods — techniques the papers use, named apart from their topics

quantization · 6.4bit-serial computing · 2.0selective scan · 1.7hadamard transform · 1.7low-rank decomposition · 1.7systolic array · 0.9structured sparsity · 0.9sorting · 0.9progressive decoding · 0.9draft model construction · 0.9clustering · 0.9GPU kernel optimization · 0.9
YearPublicationVenuePosition
2026 Bit-Serial Acceleration of LLM Inference With Mixture-of-Datatype Quantization
abstract
Large language models (LLMs) have achieved significant breakthroughs on machine learning tasks. Yet the substantial memory footprint of LLMs significantly hinders their wide deployment. In this paper, we propose BitMoD, an algorithm-hardware co-design solution for efficient LLM deployment. On the algorithm side, BitMoD introduces “fine-grained data type adaptation”, which uses a different data type to quantize a group (e.g., 128) of weights and key-value-cache (KV-cache). Through the careful design of these data types, BitMoD is able to quantize LLM weights and KV-cache to sub-4-bit precision while maintaining high accuracy. On the hardware side, BitMoD employs the bit-serial computing paradigm to easily support multiple numerical precisions and data types, thus providing a flexible trade-off between model accuracy and hardware efficiency. Furthermore, we design low-cost hardware components to effectively handle online KV-cache quantization and per-group partial sum dequantization. Our evaluation on a diverse set of LLMs demonstrates that BitMoD significantly outperforms state-of-the-art LLM quantization methods on both discriminative and generative tasks. Combining the superior model performance with an efficient accelerator design, BitMoD surpasses the state-of-the-art LLM accelerator in terms of both hardware performance and energy efficiency.
Yuzong Chen 0001, Chi-Chih Chang, Xilai Dai, Ahmed F. AbouElhamayed, Marta Andronic, George A. Constantinides, Mohamed S. Abdelfattah
IEEE Trans. Computers2
2025 FLRC: Fine-grained Low-Rank Compressor for Efficient LLM Inference
abstract
Although large language models (LLM) have achieved remarkable performance, their enormous parameter counts hinder deployment on resource-constrained hardware.Low-rank compression can reduce both memory usage and computational demand, but applying a uniform compression ratio across all layers often leads to significant performance degradation, and previous methods perform poorly during decoding.To address these issues, we propose the Finegrained Low-Rank Compressor (FLRC), which efficiently determines an optimal rank allocation for each layer, and incorporates progressive low-rank decoding to maintain text generation quality.Comprehensive experiments on diverse benchmarks demonstrate the superiority of FLRC, achieving up to a 17% improvement in ROUGE-L on summarization tasks compared to state-of-the-art low-rank compression methods, establishing a more robust and efficient framework to improve LLM inference.
Yu-Chen Lu, Chong-Yan Chen, Chi-Chih Chang, Yu-Fang Hu, Kai-Chiang Wu
EMNLP3
2025 Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration
abstract
FPGA architectures have recently been enhanced to meet the substantial computational demands of modern deep neural networks (DNNs). To this end, both FPGA vendors and academic researchers have proposed in-fabric blocks that perform efficient tensor computations. However, these blocks are primarily optimized for dense computation, while most DNNs exhibit sparsity. To address this limitation, we propose incorporating structured sparsity support into FPGA architectures. We architect 2D systolic in-fabric blocks, named systolic sparse tensor (SST) slices, that support multiple degrees of sparsity to efficiently accelerate a wide variety of DNNs. SSTs support dense operation, 2:4 (50%) and 1:4 (75%) sparsity, as well as a new 1:3 (66.7%) sparsity level to further increase flexibility. When demonstrating on general matrix multiplication (GEMM) accelerators, which are the heart of most current DNN accelerators, our sparse SST-based designs attain up to 5× higher FPGA frequency and 10.9× lower area, compared to traditional FPGAs. Moreover, evaluation of the proposed SSTs on state-of-the-art sparse ViT and CNN models exhibits up to 3.52× speedup with minimal area increase of up to 13.3%, compared to dense in-fabric acceleration.
Endri Taka, Ning-Chi Huang, Chi-Chih Chang, Kai-Chiang Wu, Aman Arora 0001, Diana Marculescu
FPGA3
2025 Palu: KV-Cache Compression with Low-Rank Projection
abstract
Post-training KV-Cache compression methods typically either sample a subset of effectual tokens or quantize the data into lower numerical bit width. However, these methods cannot exploit redundancy in the hidden dimension of the KV tenors. This paper presents a hidden dimension compression approach called Palu, a KV-Cache compression framework that utilizes low-rank projection to reduce inference-time LLM memory usage. Palu decomposes the linear layers into low-rank matrices, caches compressed intermediate states, and reconstructs the full keys and values on the fly. To improve accuracy, compression rate, and efficiency, Palu further encompasses (1) a medium-grained low-rank decomposition scheme, (2) an efficient rank search algorithm, (3) low-rank-aware quantization compatibility enhancements, and (4) an optimized GPU kernel with matrix fusion. Extensive experiments with popular LLMs show that Palu compresses KV-Cache by 50% while maintaining strong accuracy and delivering up to 1.89× speedup on the RoPE-based attention module. When combined with quantization, Palu’s inherent quantization-friendly design yields small to negligible extra accuracy degradation while saving additional memory than quantization-only methods and achieving up to 2.91× speedup for the RoPE-based attention. Moreover, it maintains comparable or even better accuracy (up to 1.19 lower perplexity) compared to quantization-only methods. These results demonstrate Palu’s superior capability to effectively address the efficiency and memory challenges of LLM inference posed by KV-Cache. Our code is publicly available at: https://github.com/shadowpa0327/Palu.
Chi-Chih Chang, Chien-Yu Lin, Chong-Yan Chen, Yu-Fang Hu, Pei-Shuo Wang, Ning-Chi Huang, Luis Ceze, Mohamed S. Abdelfattah, Kai-Chiang Wu
ICLR1
2025 Quamba: A Post-Training Quantization Recipe for Selective State Space Models
abstract
State Space Models (SSMs) have emerged as an appealing alternative to Transformers for large language models, achieving state-of-the-art accuracy with constant memory complexity which allows for holding longer context lengths than attention-based networks. The superior computational efficiency of SSMs in long sequence modeling positions them favorably over Transformers in many scenarios. However, improving the efficiency of SSMs on request-intensive cloud-serving and resource-limited edge applications is still a formidable task. SSM quantization is a possible solution to this problem, making SSMs more suitable for wide deployment, while still maintaining their accuracy. Quantization is a common technique to reduce the model size and to utilize the low bit-width acceleration features on modern computing units, yet existing quantization techniques are poorly suited for SSMs. Most notably, SSMs have highly sensitive feature maps within the selective scan mechanism (i.e., linear recurrence) and massive outliers in the output activations which are not present in the output of token-mixing in the self-attention modules. To address this issue, we propose a static 8-bit per-tensor SSM quantization method which suppresses the maximum values of the input activations to the selective SSM for finer quantization precision and quantizes the output activations in an outlier-free space with Hadamard transform. Our 8-bit weight-activation quantized Mamba 2.8B SSM benefits from hardware acceleration and achieves a 1.72 $\times$ lower generation latency on an Nvidia Orin Nano 8G, with only a 0.9\% drop in average accuracy on zero-shot tasks. When quantizing Jamba, a 52B parameter SSM-style language model, we observe only a $1\%$ drop in accuracy, demonstrating that our SSM quantization method is both effective and scalable for large language models, which require appropriate compression techniques for deployment. The experiments demonstrate the effectiveness and practical applicability of our approach for deploying SSM-based models of all sizes on both cloud and edge platforms.
Hung-Yueh Chiang, Chi-Chih Chang, Natalia Frumkin, Kai-Chiang Wu, Diana Marculescu
ICLR2
2025 Quamba2: A Robust and Scalable Post-training Quantization Framework for Selective State Space Models
abstract
State Space Models (SSMs) are gaining attention as an efficient alternative to Transformers due to their constant memory complexity and comparable performance. Yet, deploying large-scale SSMs on cloud-based services or resource-constrained devices faces challenges. To address this, quantizing SSMs using low bit-width data types is proposed to reduce model size and leverage hardware acceleration. Given that SSMs are sensitive to quantization errors, recent advancements focus on quantizing a specific model or bit-width to improve their efficiency while maintaining performance. However, different bit-width configurations, such as W4A8 for cloud service throughput and W4A16 for improving question-answering on personal devices, are necessary for specific scenarios. To this end, we present Quamba2, compatible with \textbf{W8A8}, \textbf{W4A8}, and \textbf{W4A16} for both \textbf{Mamba} and \textbf{Mamba2}, addressing the rising demand for SSM deployment across various platforms. We propose an offline approach to quantize inputs of a linear recurrence in 8-bit by sorting and clustering for $x$, combined with a per-state-group quantization for $B$ and $C$. To ensure compute-invariance in the SSM output, we offline rearrange weights according to the clustering sequence. The experiments show Quamba2-8B outperforms several state-of-the-art SSMs quantization methods and delivers 1.3$\times$ and 3$\times$ speedup in the pre-filling and generation stages and 4$\times$ memory reduction with only a $1.6$% accuracy drop on average. The code and quantized models will be released at:
Hung-Yueh Chiang, Chi-Chih Chang, Natalia Frumkin, Kai-Chiang Wu, Mohamed S. Abdelfattah, Diana Marculescu
ICML2
2025 Speculate Deep and Accurate: Lossless and Training-Free Acceleration for Offloaded LLMs via Substitute Speculative Decoding
abstract
The immense model sizes of large language models (LLMs) challenge deployment on memory-limited consumer GPUs. Although model compression and parameter offloading are common strategies to address memory limitations, compression can degrade quality, and offloading maintains quality but suffers from slow inference. Speculative decoding presents a promising avenue to accelerate parameter offloading, utilizing a fast draft model to propose multiple draft tokens, which are then verified by the target LLM in parallel with a single forward pass. This method reduces the time-consuming data transfers in forward passes that involve offloaded weight transfers. Existing methods often rely on pretrained weights of the same family, but require additional training to align with custom-trained models. Moreover, approaches that involve draft model training usually yield only modest speedups. This limitation arises from insufficient alignment with the target model, preventing higher token acceptance lengths. To address these challenges and achieve greater speedups, we propose SubSpec, a plug-and-play method to accelerate parameter offloading that is lossless and training-free. SubSpec constructs a highly aligned draft model by generating low-bit quantized substitute layers from offloaded target LLM portions. Additionally, our method shares the remaining GPU-resident layers and the KV-Cache, further reducing memory overhead and enhance alignment. SubSpec achieves a high average acceptance length, delivering 9.1$\times$ speedup for Qwen2.5 7B on MT-Bench (8GB VRAM limit) and an average of 12.5$\times$ speedup for Qwen2.5 32B on popular generation benchmarks (24GB VRAM limit).
Pei-Shuo Wang, Jian-Jia Chen, Chun-Che Yang, Chi-Chih Chang, Ning-Chi Huang, Mohamed S. Abdelfattah, Kai-Chiang Wu
NeurIPS4
2024 Transformer and Its Variants for Identifying Good Dice in Bad Neighborhoods
abstract
Good-die-in-bad-neighborhood (GDBN) is a widely adopted method utilizing the fact that manufacturing defects tend to exhibit spatial dependency and form a cluster or specific pattern of bad dice on a wafer. Existing research studies on GDBN mainly focus on learning such spatial relationships within a limited observation window through simple mechanisms such as linear regression or multilayer perceptron model. In this paper, we propose MetaFormer-GDBN, a transformer-based deep learning model with the observation window extending to the entire wafer to include broader pattern information. The enhanced neighboring information and model capacity allow our method to capture more complex patterns of bad dice. Experiments show that compared to previous work, our method can achieve up to 50 % performance improvement, reducing the DPPM (defective parts per million) with minimal yield loss.
Cheng-Che Lu, Chi-Chih Chang, Chia-Heng Yen, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao
VTS2
2024 FLORA: Fine-grained Low-Rank Architecture Search for Vision Transformer
abstract
Vision Transformers (ViT) have recently demonstrated success across a myriad of computer vision tasks. However, their elevated computational demands pose significant challenges for real-world deployment. While low-rank approximation stands out as a renowned method to reduce computational loads, efficiently automating the target rank selection in ViT remains a challenge. Drawing from the notable similarity and alignment between the processes of rank selection and One-Shot NAS, we introduce FLORA, an end-to-end automatic framework based on NAS. To overcome the design challenge of supernet posed by vast search space, FLORA employs a low-rank aware candidate filtering strategy. This method adeptly identifies and eliminates underperforming candidates, effectively alleviating potential undertraining and interference among subnetworks. To further enhance the quality of low-rank supernets, we design a low-rank specific training paradigm. First, we propose weight inheritance to construct supernet and enable gradient sharing among low-rank modules. Secondly, we adopt low-rank aware sampling to strategically allocate training resources, taking into account inherited information from pre-trained models. Empirical results underscore FLORA’s efficacy. With our method, a more fine-grained rank configuration can be generated automatically and yield up to 33% extra FLOPs reduction compared to a simple uniform configuration. More specific, FLORA-DeiT-B/FLORA-Swin-B can save up to 55%/42% FLOPs almost without performance degradtion. Importantly, FLORA boasts both versatility and orthogonality, offering an extra 21%-26% FLOPs reduction when integrated with leading compression techniques or compact hybrid structures. Our code is publicly available at https://github.com/shadowpa0327/FLORA.
Chi-Chih Chang, Yuan-Yao Sung, Shixing Yu, Ning-Chi Huang, Diana Marculescu, Kai-Chiang Wu
WACV1
2004 Embedding information within dynamic visual patterns
abstract
There exist many scenarios in which the automatic distinction between human and machines is desirable. This paper describes a texture-image based approach to encode text information in such a way that machine vision algorithms will experience difficulties while humans can extract the embedded text effortlessly. We exploit both static and dynamic visual patterns to diversify the image content and discourage automatic processing. Examples of the resulting patterns are presented and their properties are discussed.
Wen-Hung Liao, Chi-Chih Chang
ICME2