Shigeo Sato

dblp:53/2013 · DBLP profile ↗
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27ranked-venue papers
3as first author
9since 2021 · last 2025
0000-0003-3912-357XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 23 · 3 first-author · 5 since 2021Systems, architecture and hardware · 4 · 4 since 2021
YearPublicationVenuePosition
2025 Event-Driven Inference with Spiking Neural Networks Enhanced by Non-Volatile Analog Spin-Orbit Torque Devices
abstract
Edge computing is becoming increasingly important, with the major challenge being the development of edge devices capable of performing tasks, such as classification and prediction, with high energy efficiency overcoming the limitations of the traditional von Neumann architecture. We propose an inference system based on a liquid state machine that combines spiking neural networks with non-volatile analog memory devices, inspired by information processing in the biological brain. Multiply accumulate operations were successfully demonstrated using three-terminal analog spintronics devices with a spin-orbit torque-induced magnetization switching as analog synaptic weights. This system operates in an event-driven manner based on spike events. Because the memory is non-volatile, the static power consumption is reduced to almost zero. This characteristic is particularly effective for edge devices that process low-frequency sensor signals, such as those used for keyword spotting or environmental monitoring.
Satoshi Moriya, Yosuke Iida, Aurélien Lagarrigue, K. Vihanga De Zoysa, Masaya Ishikawa, Hideaki Yamamoto, Sunsuke Fukami, Shigeo Sato
ISCAS8
2025 Directional intermodular coupling enriches functional complexity in biological neuronal networks
abstract
Hierarchically modular organization is a canonical network topology that is evolutionarily conserved in the nervous systems of animals. Within the network, neurons form directional connections defined by the growth of their axonal terminals. However, this topology is dissimilar to the network formed by dissociated neurons in culture because they form randomly connected networks on homogeneous substrates. In this study, we fabricated microfluidic devices to reconstitute hierarchically modular neuronal networks in culture (in vitro) and investigated how non-random structures, such as directional connectivity between modules, affect global network dynamics. Embedding directional connections in a pseudo-feedforward manner suppressed excessive synchrony in cultured neuronal networks and enhanced the integration-segregation balance. Modeling the behavior of biological neuronal networks using spiking neural networks (SNNs) further revealed that modularity and directionality cooperate to shape such network dynamics. Finally, we demonstrate that for a given network topology, the statistics of network dynamics, such as global network activation, correlation coefficient, and functional complexity, can be analytically predicted based on eigendecomposition of the transition matrix in the state-transition model. Hence, the integration of bioengineering and cell culture technologies enables us not only to reconstitute complex network circuitry in the nervous system but also to understand the structure-function relationships in biological neuronal networks by bridging theoretical modeling with in vitro experiments.
Nobuaki Monma, Hideaki Yamamoto, Naoya Fujiwara, Hakuba Murota, Satoshi Moriya, Ayumi Hirano-Iwata, Shigeo Sato
Neural Networks7
2025 Analog VLSI Implementation of Subthreshold Spiking Neural Networks and Its Application to Reservoir Computing
abstract
Neuromorphic computing achieves highly energy-efficient computations while adapting to environmental changes. Processing time series data by spiking neural networks can further reduce the power consumption of neuromorphic computing devices because most of the energy in the network is consumed only when the neuron generates and transmits a spike. In this study, we designed fully analog two-variable spiking neuron and spiking neural network circuits, taking advantage of the physical properties of transistors as analog devices. The energy consumption of the circuit for generating a spike was 22.7 fJ/spike when the MOS transistors were operating in the subthreshold region. The proposed circuits were implemented on an analog very large-scale integrated (VLSI) circuit chip in a$0.18~\mu $m CMOS process. The circuits exhibit complex spike dynamics even under subthreshold operation according to chip measurements. We demonstrated that the spike sequence generated by the spiking neural network circuit was successfully applied to spoken digit recognition tasks via a reservoir computing framework with 14.4 fJ/SOP efficiency. These results provide important insights into edge AI applications of SNN-based neuromorphic hardware.
Satoshi Moriya, Masaya Ishikawa, Satoshi Ono, Hideaki Yamamoto, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas, Shigeo Sato
IEEE Trans. Circuits Syst. I Regul. Pap.8
2024 Design of Mixed-Signal LSI with Analog Spiking Neural Network and Digital Inference Circuits for Reservoir Computing
abstract
Edge computing requires low-power, real-time processing of complex information. Spiking neural networks are highly expected to be applied to edge computing due to their efficient computing properties. Here, we design a mixed-signal LSI consisting of an analog spiking neural network and digital inference circuits for edge device. The two-variable spiking neuron circuits operate in an analog manner using the physical properties of transistors and are connected through synaptic circuits to form a network. The neural network successfully operates and exhibits complex nonlinear behavior in response to external inputs. The power consumption of the spike generation is as low as tens of femtojoules per spike because the transistors in the circuits operate in the subthreshold region, which is enough to be used as edge computing devices. In addition, a digital circuit was designed to perform real-time inference using the spiking sequences from the analog spiking neural network. The result showed that the mixed-signal LSI consisting of the analog spiking neural network and the digital inference circuits can be applied to the spoken digit classification task in real time. The proposed system has the potential to be used as ultra-low-power neuromorphic hardware in practical applications.
Satoshi Moriya, Hideaki Yamamoto, Masaya Ishikawa, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas, Shigeo Sato
IJCNN7
2024 Bifurcation phenomena observed from two-variable spiking neuron integrated circuit
abstract
A compact two-variable spiking neuron integrated circuit was proposed. Measurements of the circuit confirmed various types of spike responses with ultra-low power consumption. In this study, the two-variable spiking neuron circuit is modified to generate chaotic spike trains suitable for complex spatiotemporal information processing. The chaotic behavior is confirmed with time waveforms, return maps, bifurcation diagrams, and diversity index of inter-spike intervals through circuit simulations and experiments.
Takemori Orima, Yoshihiko Horio, Satoshi Moriya, Shigeo Sato
ISCAS4
2023 Real-Time Adaptive Physical Sensor Processing with SNN Hardware
Jordi Madrenas, Bernardo Vallejo Mancero, Josep Angel Oltra, Mireya Zapata, Jordi Cosp, Robert Calatayud, Satoshi Moriya, Shigeo Sato
ICANN (5)8
2022 A Fully Analog CMOS Implementation of a Two-variable Spiking Neuron in the Subthreshold Region and its Network Operation
abstract
Edge computing requires the processing of real-time and personalized information with low power consumption. Neuromorphic devices are promising candidates for applications related to edge computing. Rate neurons, which are typically used in neuromorphic hardware, persistently consume power regardless of their outputs. To further reduce the power consumption of neuromorphic devices, spiking neurons are more suitable because they are event-driven, and information is transferred only when the neuron fires. Herein, we propose a two-variable spiking neuron circuit that operates in a fully analog manner by utilizing the physical properties of transistors as analog devices. By operating in the subthreshold region of the MOS transistor, the energy required to produce a spike is approximately tens of fJ/spike. Furthermore, the analog neuron can exhibit complex spike dynamics, such as chattering, as confirmed using post-layout simulations. The simulations indicated that a neural network comprising the proposed neuron circuits operates successfully and exhibits complex nonlinear behavior. These results provide a basis for dedicated hardware spiking neuron circuits, which could be used as ultra-low-power neuromorphic hardware in various applications, such as realizing liquid-state machines for processing time-series signals.
Satoshi Moriya, Hideaki Yamamoto, Shigeo Sato, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas
IJCNN3
2021 A Subthreshold Spiking Neuron Circuit Based on the Izhikevich Model
Shigeo Sato, Satoshi Moriya, Yuka Kanke, Hideaki Yamamoto, Yoshihiko Horio, Yasushi Yuminaka, Jordi Madrenas
ICANN (5)1
2021 Hardware-Software Co-Design for Efficient and Scalable Real-Time Emulation of SNNs on the Edge
abstract
This paper introduces a novel workflow for Distributed Spiking Neural Network Architecture (DSNA). As such, the hardware implementation of Single Instruction Multiple Data (SIMD)-based Spiking Neural Network (SNN) requires the development of user-friendly and efficient toolchain in order to maximise the potential that the architecture brings. By using a novel SNN architecture, a custom designed hardware/software toolchain has been developed. The toolchain performance has been experimentally checked on a Band-Pass Filter (BPF), obtaining optimized code and data.
Josep Angel Oltra, Jordi Madrenas, Mireya Zapata, Bernardo Vallejo Mancero, Diana Mata-Hernandez, Shigeo Sato
ISCAS6
2019 An Izhikevich Model Neuron MOS Circuit for Low Voltage Operation
Yuki Tamura, Satoshi Moriya, Tatsuki Kato, Masao Sakuraba, Yoshihiko Horio, Shigeo Sato
ICANN (1)6
2019 Quantitative Analysis of Dynamical Complexity in Cultured Neuronal Network Models for Reservoir Computing Applications
abstract
Reservoir computing is a machine learning paradigm that was proposed as a model of cortical information processing in the brain. It processes information using the spatiotemporal dynamics of a large-scale recurrent neural network and is expected to improve power efficiency and speed in neuromorphic computing systems. Previous theoretical investigation has shown that brain networks exhibit an intermediate state of full coherence and random firing, which is suitable for reservoir computing. However, how reservoir performance is influenced by connectivity, especially which revealed in recent connectomics analysis of brain networks, remains unclear. Here, we constructed modular networks of integrate-and-fire neurons and investigated the effect of modular structure and excitatory-inhibitory neuron ratio on network dynamics. The dynamics were evaluated based on the following three measures: synchronous bursting frequency, mean correlation, and functional complexity. We found that in a purely excitatory network, the complexity was independent of the modularity of the network. On the other hand, networks with inhibitory neurons exhibited complex network activity when the modularity was high. Our findings reveal a fundamental aspect of reservoir performance in brain networks, contributing to the design of bio-inspired reservoir computing systems.
Satoshi Moriya, Hideaki Yamamoto, Ayumi Hirano-Iwata, Shigeru Kubota, Shigeo Sato
IJCNN5
2017 Complexity Reduction of Neural Network Model for Local Motion Detection in Motion Stereo Vision
Hisanao Akima, Susumu Kawakami, Jordi Madrenas, Satoshi Moriya, Masafumi Yano, Koji Nakajima, Masao Sakuraba, Shigeo Sato
ICONIP (6)8
2017 Modularity-dependent modulation of synchronized bursting activity in cultured neuronal network models
abstract
In a dissociated culture, neuronal networks spontaneously generate highly stereotypical activity characterized by synchronous bursting. With recent advancements in microfabrication technology, the topologies of cultured neuronal networks can now be engineered to have, e.g., the modular connectivity that is often found in vivo. In this paper, we construct networks of leaky integrate-and-fire neurons to theoretically investigate the effect of modular connectivity on the synchronous bursting activity of cultured neuronal networks. Modular network models are created by defining the number of modules and changing the connection formation probability within a given module, while maintaining a constant connection density. We find that the synchronized bursting frequencies in networks with the same numbers of neurons and connections are solely dependent on their modularity. We also investigate the mechanism behind the network-to-network variation of the activity in random networks, finding that local measures, such as the neuron in-degree and the self-connection, are the important factors. Out results indicate an economic advantage for networks bearing a modular structure and provides a graph-theoretical description of this mechanism.
Satoshi Moriya, Hideaki Yamamoto, Hisanao Akima, Ayumi Hirano-Iwata, Michio Niwano, Shigeru Kubota, Shigeo Sato
IJCNN7
2017 Neuro-inspired quantum associative memory using adiabatic hamiltonian evolution
abstract
It is widely believed that the real parallel computation achieved by quantum computers has an enormous computing potential. In order to expand its applicable field, we have investigated the fusion of quantum and neural computations. As a first step of implementing learning function on quantum computers, we have proposed a novel quantum associative memory (QuAM) by considering an analogy between neural associative network and qubit network. The memorizing procedure of the QuAM is realized with a Hamiltonian derived from qubit-qubit interactions, and the retrieving procedure is based on the adiabatic Hamiltonian evolution. The memory capacity of the QuAM has been nominally estimated as 2N-1where N is a number of qubits, but its retrieve property has not been discussed in our previous study. This paper proposes a retrieving process for the QuAM and evaluates its performance in detail. The results indicate that the average of the retrieving probability is over 50% even when the qubit network memorizes 2N-1patterns and thus the QuAM is successfully implemented.
Yoshihiro Osakabe, Shigeo Sato, Hisanao Akima, Masao Sakuraba, Mitsunaga Kinjo
IJCNN2
2014 Majority neuron circuit having large fan-in with non-volatile synaptic weight
abstract
We present a design of a majority neuron circuit with non-volatile synaptic weights. It is based on an analog majority circuit composed of controlled current inverters (CCIs). The proposed circuit is immune to device parameter fluctuations, and its fan-in is estimated about 1000. Synaptic weights are realized on the neuron circuit by adding variable resistors. We consider a design of a non-volatile synaptic weight by using a three-terminal magnetic domain-wall motion (DWM) device. The operation of a fully connected recurrent neural network composed of the proposed circuits has been confirmed by SPICE simulation.
Hisanao Akima, Yasuhiro Katayama, Koji Nakajima, Masao Sakuraba, Shigeo Sato
IJCNN5
2011 Method of Solving Combinatorial Optimization Problems with Stochastic Effects
Takahiro Sota, Yoshihiro Hayakawa, Shigeo Sato, Koji Nakajima
ICONIP (3)3
2008 Study on the performance of neuromorphic adiabatic quantum computation algorithms
abstract
Quantum computation algorithms indicate possibility that non-deterministic polynomial time (NP-time) problems can be solved much faster than by classical methods. Farhi et al. [2], [3] have proposed an adiabatic quantum computation (AQC) for solving the three-satisfiability problem (3-SAT). We have proposed a neuromorphic quantum computation algorithm based on AQC, in which an analogy to an artificial neural network (ANN) is considered in order to design a Hamiltonian. However, in the neuromorphic AQC, the relation between its computation time and the probability of correct answers is not clear yet. In this paper, we study both of residual energy and the probability of finding solution as a function of computation time. The results show that the performance of the neuromorphic AQC depends on the characteristic of Hamiltonians.
Aiko Ono, Shigeo Sato, Mitsunaga Kinjo, Koji Nakajima
IJCNN2
2007 Energy Dissipation Effect on a Quantum Neural Network
Mitsunaga Kinjo, Shigeo Sato, Koji Nakajima
ICONIP (2)2
2006 A Study on Learning with a Quantum Neural Network
abstract
A quantum neural network based on the adiabatic quantum computation is one of candidates to overcome the difficulty for developing a quantum computation algorithm. In this paper, we propose a new learning method for a quantum neural network inspired by Hebb learning. Preliminary but successful results by numerical simulations have been shown. The results indicate that a quantum learning like Hebb rule can be implemented.
Mitsunaga Kinjo, Shigeo Sato, Koji Nakajima
IJCNN2
2005 Basic property of a quantum neural network composed of Kane's qubits
abstract
It has been known a variety of optimization problems can be solved with a neural network, and a quantum computer executes real parallel computation. A quantum neural network has been proposed in order to incorporate quantum dynamics. In this paper, we test the possibility of real implementation of a quantum neural network with a nuclear spin as a qubit. First, we introduce the relation between spin and neuron, then describe the adiabatic Hamiltonian evolution applied for the state change. Next, we describe a real spin quantum system and show the simulation results. A nuclear spin system proposed by Kane behaves as a neuron with inhibitory interactions as expected in analogy to a Hopfield network.
Yuuki Nakamiya, Mitsunaga Kinjo, Osamu Takahashi, Shigeo Sato, Koji Nakajima
IJCNN4
2004 Implementation of a large scale hardware neural network system based on stochastic logic
abstract
We present a large scale hardware neural network system which consists of 16 chips, 1024 neurons. The system is realized by using stochastic logic. Stochastic logic makes possible to implement numerous neurons on a VLSI chip and to build a system comprising multiple chips easily. In addition, stochastic logic has a characteristic as some noise is generated while coding operations. This noise is effective for escaping from the local minima in a Hopfield network. The availability of this noise is confirmed in the measurement of our system.
Akiyoshi Momoi, Shunsuke Akimoto, Shigeo Sato, Koji Nakajima
IJCNN3
2004 A study on neuromorphic quantum computation
abstract
A quantum computer employing a single quantum as a qubit executes real parallel computation. Several algorithms have been proposed for quantum computation. However, these algorithms are applicable only to a limited number of applications. Therefore, a general purpose algorithm should be studied and developed for practical use in the near future. We focus on the adiabatic evolution algorithm in order to incorporate an artificial neural network(ANN)-like method and discuss how to use this algorithm for solving an optimization problem.
Shigeo Sato, Mitsunaga Kinjo, Osamu Takahashi, Yuuki Nakamiya, Koji Nakajima
IJCNN1
2004 Design of Single Electron Circuitry for a Stochastic Logic Neural Network
Hisanao Akima, Shigeo Sato, Koji Nakajima
KES2
2003 Quantum Adiabatic Evolution Algorithm for a Quantum Neural Network
Mitsunaga Kinjo, Shigeo Sato, Koji Nakajima
ICANN2
2003 Implementation of a new neurochip using stochastic logic
abstract
Even though many neurochips have been developed and investigated, the best suitable way for implementation has not been known clearly. Our approach is to exploit stochastic logic for various operations required for neural functions. The advantage of stochastic logic is that complex operations can be implemented with a few ordinary logic gates. On the other hand, the operation speed is not so fast since stochastic logic requires certain accumulation time for averaging. However, a huge integration can be achieved and its reliability is high because all of operations are done on digital circuits. Furthermore, we propose a nonmonotonic neuron realized by stochastic logic, since the nonmonotonic property is efficient for the performance enhancement in association and learning. In this paper, we show the circuit design and measurement results of a neurochip comprising 50 neurons are shown. The advantages of nonmonotonic and stochastic properties are shown clearly.
Shigeo Sato, Ken Nemoto, S. Akimoto, Mitsunaga Kinjo, Koji Nakajima
IEEE Trans. Neural Networks1
2000 Characteristics of Small Scale Non-Monotonic Neuron Networks Having Large Potentiality for Learning
abstract
We report a study on learning ability of a deterministic Boltzmann machine (DBM) with neurons which have a nonmonotonic activation function. We use an end-cut-off-type function with a threshold parameter '/spl theta/' as the nonmonotonic function. Numerical simulations of nonlinear problems, such as the 2-parity problem and the 4-parity problem, show that the DBM network with nonmonotonic neurons has higher learning ability compared to the network with monotonic neurons.
Mitsunaga Kinjo, Shigeo Sato, Koji Nakajima
IJCNN (4)2
1999 A study on DBM network with non-monotonic neurons
abstract
In this paper, we report a study on learning ability of a deterministic Boltzmann machine (DBM) with neurons which have a nonmonotonic activation function. We use an end-cut-off-type function with a threshold parameter '/spl theta/' as the nonmonotonic function. Numerical simulations of learning nonlinear problems, such as the XOR problem and the ADD problem, show that the DBM network with nonmonotonic neurons has higher learning ability compared to the network with monotonic neurons, and that the nonmonotonic neural network has novel effects which adjust the number of neurons. We have designed an integrated circuit of the 2-3-1 DBM network. The use of the nonmonotonic neurons make it possible to integrate a large scale neural network because of the simple circuit design.
Mitsunaga Kinjo, Shigeo Sato, Koji Nakajima
IJCNN2