The key advantages of stochastic computing (SC) are its simple arithmetic circuits and high tolerance for bit errors. Deterministic SC (DSC) improves SC by using deterministic bitstreams, resulting in accurate results without fluctuation. Recently, a platform that conducts DSC in the time domain has been proposed. This platform enhances the feasibility of DSC and brings it closer to becoming a mainstream computational paradigm. However, its circuit is unable to represent all rational numbers. This work improves the platform by enabling the representation of all rational numbers for computation. Furthermore, it reduces hardware costs and power consumption, paving the way for new SC applications.

True random number generator (TRNG) is a crucial component in security. In typical TRNGs, entropy comes directly from device noises. In this work, an improved method of using frequency-mixing as means for enriching entropy is implemented. A group of electromagnetic waves are mixed to create an irregular waveform that is then sampled to generate a random bitstream. Some part of the bitstream is fed back to the system for influencing the future frequencies of the sourcing waves, making it a chaotic system. The circuit-level support for this TRNG is the TAF-DPS (Time-Average-Frequency Direct Period Synthesis) technology. It can be digitally implemented, making the TRNG a portable IP. The merits of this TRNG include no need of special device, no post-processing, free of bias, programmable throughput, and hard-to-recognize spectrum. Those features make the TRNG suitable for a large array of applications, particularly for security in cyberspace. This TRNG is validated by a silicon chip on a 180 nm process, also on a FPGA.

A true random number generator (TRNG) which is based on interaction among frequency sources is proposed in this work. Unlike all other TRNGs which generate random number series from either harvesting physical noises or utilizing structure defect and manufacturing imperfection, this TRNG generates its randomness through the interaction of multiple signal sources, each with its unique frequency. This method is enabled by the excellent frequency-generation-capability of the Time-Average-Frequency Direct Period Synthesis (TAF-DPS). This type of TRNG has the advantages of low cost, low power and robustness against process, voltage and temperature (PVT) variations, environmental noises and malicious attacks. The all-digital nature also makes it implementation-friendly and process-portable. Furthermore, it is highly programmable that makes it flexible for various applications. In this work, an implementation on FPGA is demonstrated and the resultant random data streams have passed all NIST tests.

Frequency source is one of the foundational elements in electronics. It is used to derive clock signal that establishes the sense of time inside electronic system. An important type of frequency source is the one whose frequency can be adjusted through external control, such as VCXO and DCXO. This type of frequency-adjustable source is useful for many applications such as Doppler radar, frequency modulation, data transmission, telemetry, and telecommunication among others. Frequency adjustability and frequency stability are two requirements that contradict each other. The solution is usually a compromise among factors of performance, power, cost and size. Time-Average-Frequency Direct Period Synthesis (TAF-DPS) is an emerging frequency synthesis technique that provides a new perspective on solving this problem. In this work, a TAF-DPS based DCXO architecture is presented. The architecture is proven with an implementation on FPGA. Its frequency granularity is achieved at 0.02 ppb/step, monotonicity is mathematically guaranteed, tuning range is virtually unlimited. The linearity within a 1% range of 26 MHz is measured as 0.005%.

Time-average-frequency (TAF) is a novel concept proposed in 2008 for constructing clock signal. TAF direct period synthesis (TAF-DPS) is an emerging frequency synthesis technique based on TAF. Its distinguished features are small frequency granularity and fast frequency switching, achieved simultaneously for a given design. Furthermore, its output frequency is monotonically changed with a digital control word. Those features make it suitable digitally controlled oscillator (DCO). In this paper, a TAF-DPS DCO is created entirely from digital cells. Using it as the core, a 100% digital TAF frequency-locked loop (TAF-FLL) is constructed. Unlike all established FLL and PLL architectures, TAF-FLL's output is in TAF instead of conventional frequency. This fact impacts the design from at least two directions. First, it blurs the boundary between integer- and fractional-N. Second, the issues of output jitter and the loop design are independent of each other and can be treated separately. This novel all-digital architecture has been implemented in field-programmable gate array for verifying the principle. It is the first case of building frequency control loop on TAF. The purpose of this TAF-FLL is to drive digital circuits, for digital-oriented applications.

Time-Average-Frequency Direct Period Synthesis (TAF-DPS) is an emerging frequency synthesis technique. It is built upon the concept of Time-Average-Frequency (TAF). Its distinguishing characteristics are small frequency granularity and fast frequency switching. These features make TAF-DPS an ideal on-chip frequency generator. In this paper, a TAF-DPS circuit is constructed using digital approach of HDL coding and synthesis. It is then mapped to FPGA. Using this full digital TAF-DPS as a tool, several innovative examples in application level are demonstrated. The aim of this work is to demonstrate that this low design effort and compact frequency synthesizer is a handy and powerful tool for engineers to “play with frequency” and subsequently innovate in their high level IoT applications.

Direct period synthesis is a technique of using a base time unit and the time-average-frequency concept to synthesize clock frequency. Its distinguished capabilities include generating frequencies in very fine step and switching frequency in very fast speed. In this paper, the principle of fine frequency generation is presented. Using data collected from two 55-nm CMOS chips, experimental evidence of sub-ppm (0.04 ppm at finest) frequency resolution at 27 MHz, 1.5 GHz, and 2.4 GHz is provided. This feature of fine frequency resolution is very important in digital communication, especially for plesiochronous and heterochronous systems. It is a circuit level enabler for system level innovation. In the last part of this paper, several important applications of using these capabilities are explored.

Frequency synthesis is one of the most important and most actively researched subjects in the field of VLSI mixed-signal circuit design. Among the existing techniques in this area, Fractional-N architecture is a widely used one for generating frequencies which are not integer multiple of the input reference frequency. Flying-Adder architecture is an emerging technique which is based on a new concept, Time-Average-Frequency, to generate frequencies. This paper presents an in-depth analysis and comparison between the two methods.

A frequency synthesizer architecture with a wide tuning range and reduced fractional spurs is presented. The proposed topology includes a Σ-Δ fractional-N synthesizer and an integer Flying-Adder architecture. Compared to the conventional Σ-Δ fractional-N frequency synthesizer, this approach has much wider tuning range. Compared to the fractional Flying-Adder frequency synthesizer, the proposed approach can achieve the same frequency resolution with reduced fractional spurs and alleviates the constraints on the adder design in the Flying-Adder architecture.

The Flying Adder (FA) architecture is one of the latest developments in the area of on-chip frequency synthesis. It has two operating modes: integer-FA mode and fractional FA mode. In the fractional FA mode, a concept of Time-Average-Frequency is used to synthesize certain frequencies that cannot be easily obtained using traditional methods. The issue of using Time-Average-Frequency to drive digital systems has been studied in previous publications by the authors. In this paper, we investigate the impact of using Time-Average-Frequency based clock signals to drive systems with embedded Digital-to-Analog Converters (DAC).

The "Flying-Adder" architecture is a frequency and phase synthesis technique that is based on a voltage-controlled oscillator (VCO) of multiple delay stages. Since the invention of this architecture, various improvements have been made during many implementations of this technique. One of the remaining issues is to reduce the number of delay stages inside the VCO for the benefit of low power consumption and easy design/layout implementation. This paper presents a modified version of the architecture, by utilizing the scalability presented by Xiu and You, 2002, to achieve this goal. The modified architecture can also be used to improve the number of synthesizable frequencies. The tradeoff for this architecture of reduced-delay-stage VCO is the circuit speed.

Most of today's digital designs, from small-scale digital block designs to system-on-chip (SoC) designs, are based on "synchronous" design principle. Clock is the most important issue in these designs. Frequency and phase synthesis is closely related to the clock generation. A frequency and phase synthesis technique based on phase-locked loop is proposed in that delivers high performance, easy integration, and high stability. However, there are problems associated with this architecture, such as: 1) its highest deliverable frequency is limited by the speed of the accumulator and 2) the phase synthesis circuitry will not work well in certain ranges (dead zone) and in certain conditions (dual stability). This paper presents an improved architecture that addresses these problems. The new frequency synthesis circuitry has scalability for higher output frequency. It also has an internal node whose frequency is twice that of output signal. When duty cycle is not a concern, this signal can be used directly as clock source. The new phase synthesis circuitry is free of "dead zone" and "dual stability." The improved architecture has better performance, is simpler to implement, and is easier to understand.