The letter presents an improved algorithm for computation of general integer-order Hankel transforms, which is back-projection based. The original algorithm breaks the Hankel transform into an inverse fast Fourier transform and a discrete summation involving trigonometric terms (which is more computationally intensive). In this work, by varying the number of terms of the discrete summation with the transform order, the number of trigonometric computations and multiplications can be reduced drastically, which leads to overall computational complexity improvement. To be precise, the time complexity constant is reduced so much that our algorithm is faster than the state-of-the-art, while being O(N2). The algorithm has been simulated in MATLAB and a performance improvement of 6.04x in the discrete summation step (average case) over the original algorithm has been obtained. Finally, computational error of our proposed algorithm has been obtained, which is better than the baseline algorithm, and is comparable to the state-ofthe-art.

It is known that the zero redundancy sparse arrays (ZRSA) explore the concept of sum and difference coarray (SDC). Both ZRSA-I and ZRSA-II are attractive options for the direction-of-arrival (DOA) estimation. The main property of these arrays is that they attempt to minimize the redundancy of lags between the sum coarray and the difference coarray. In this work, the performance of the ZRSA configurations is further improved in both degrees of freedom (DOF) and mutual coupling perspectives. In fact, the proposed arrays obtain the highest DOF among the state-of-the-art arrays. To perform that, the elements of ZRSA-II are shifted by a specific translation factor so that the overlapping of the sum coarray lags and the difference coarray lags further decrease. To reduce the mutual coupling, the elements of the array are placed in strategic locations. Simulation results validate the superiority of the proposed arrays over the other existing arrays.

In this work, we propose some novel coprime array configurations for real-valued sources, which will achieve more degrees-of-freedom (DOF) than the other existing coprime arrays when the array is moved only by half wavelength. We know that for real-valued sources, the properties of the difference and sum coarray (DSCA) of the synthetic array (SA) can be explored. The sensing environment is assumed to remain unchanged during the array motion. Here, we carry out a detailed analysis of the DSCA of SA of the proposed arrays. We also provide the mathematical expressions of the number of uniform and unique DOF. The optimization of each of the arrays is then carried out for a given number of sensors so that the DSCA of SA achieves the maximum uniform DOF. We perform all the required simulations to prove the superiority of the proposed coprime arrays.

This work proposes a novel k-times extended coprime array for direction-of-arrival (DOA) estimation that achieves more consecutive degrees-of-freedom (DOF) than the existing k-times extended coprime array with the same number of sensors. If M and N are the parameters of the coprime array, it will be proved that the increase in consecutive DOF of the proposed k-times extended coprime array is O(MN) over the existing k-times extended coprime array. We carry out the analysis of the proposed array considering N even and N odd. The closed-form expressions of the number of consecutive DOF are provided for both cases. Spatial smoothing MUltiple SIgnal Classification (MUSIC) is used to estimate the directions of the sources. All the required simulations are carried out to prove the superiority of the proposed coprime array over the existing coprime arrays.

In this letter, a novel nested array is proposed which not only increases the degrees of freedom (DOF) but also reduces the mutual coupling that occurs in the general nested array structure by moving the original array only half wavelength. Here we deal with real-valued sources like AM or BPSK whereby we can explore the property of the sum coarray along with the difference coarray of the synthetic array (SA). It is assumed that the sensing environment does not change over the array motion of half wavelength. First, we develop the novel nested array and prove that the sum difference coarray (SDCA) of SA is hole-free up to a certain number. Then we provide closed-form expressions for the number of unique and consecutive lags of the SDCA of SA. We also optimize the array for a given number of sensors. Simulation results show the superiority of the proposed array over other existing arrays.

Cellular Automata (CA) is attractive for high-speed VLSI implementation due to modularity, cascadability, and locality of interconnections confined to neighboring logic cells. However, this outcome is not easily transferable to tree-structured CA, since the neighbors having half and double the index value of the current CA cell under question can be sufficiently distanced apart on the FPGA floor. Challenges to meet throughput requirements, seamlessly translate algorithmic modifications for changing application specifications to gate level architectures and to address reliability challenges of semiconductor chips are ever increasing. Thus, a proper design framework assisting automation of synthesizable, delay-optimized VLSI architecture descriptions facilitating testability is desirable. In this article, we have automated the generation of hardware description of tree-structured CA that includes a built-in scan path realized with zero area and delay overhead. The scan path facilitates seeding the CA, state modification, and fault localization on the FPGA fabric. Three placement algorithms were proposed to ensure maximum physical adjacency amongst neighboring CA cells, arranged in a multi-columnar fashion on the FPGA grid. Our proposed architectures outperform implementations arising out of standard placers and behavioral designs, existing tree mapping strategies, and state-of-the-art FPGA centric error detection architectures in area and speed.

Random number generation is integral to information security in IoT based cyber-physical systems. One such recent scheme of random number generation was proposed in [1] called Mageto, which is based on the design principles of cellular automata (CA). CA are characterized as finite state machines (FSMs) which evolve in discrete time steps. In hardware, their architecture remains modular and cascadable, which is ideal for amicable mapping onto FPGA primitives, leading to a speed-area efficient realization [2], [3]. Fault localization and in-system testing of FPGAs are now assuming substantial importance [4]. Exploring the utilization ratio of the configured primitives is often essential for supplementing an original FPGA implementation with testable logic without appreciable hardware overhead and critical path delay, by adopting careful optimization practices. Primitive instantiation is one such technique to directly instantiate an FPGA primitive into a design through appropriate logic configuration. We believe that VLSI implementation of Mageto has never been discussed before, which we choose to address in this paper. Our proposed primitive instantiation based architectures for Mageto, whose design description generation has been automated, outperform the relatively high level behavioral implementations with respect to area (logic slices) and speed.

VLSI implementation of Cellular Automata (CAs) has gained importance owing to its features which guarantee parallelism, locality and structural regularity. In this work, we have addressed the design challenges pertaining to an implementation optimized for speed, of tree-structured linear CA architectures on Field Programmable Gate Array (FPGA) with built-in scan paths. Scan based design facilitates state initialization, helps to escape from any graveyard state, or figure out faulty locations (if any) on which the circuit is mapped. Our design automation platform generates synthesizable circuit descriptions of tree-structured CA on FPGA, and appends scan functionality without additional logic or speed overhead. Placement algorithms governing the map of CA cell nodes on the FPGA slices have been proposed to ensure maximum physical proximity among CA cells sharing neighborhood dependencies. This is done to exploit the VLSI amenable features such as physical adjacency of the neighboring nodes participating in the next state (NS) computation of each other. The ultimate implementation leads to minimum spacing of linear order between CA neighbours. The NS logic of each CA cell inclusive of scan multiplexing, owing to restricted neighborhood size, is realized using a single Look-Up Table. Our architectures outperform behavioral implementations realized with higher levels of design style abstraction.

In recent years, several approximate adders have been proposed which are targeted for energy-efficient system design specific to error-tolerant applications. An approximate least significant bit (LSB) adder (ALA) is one such class of adder which is composed of two adder segments: one accurate most significant adder segment and one LSB adder segment approximated with inexact adder components. Error metrics such as mean error distance (MED), mean square error distance (MSED), and worst case error (WCE) have been used widely in existing studies to characterize and compare various approximate adders. In this article, we propose three independent algorithms to compute exact values of MED, MSED, and WCE, respectively, for an ALA. The algorithms are based on an iterative computation of intermediate parameters from least significant subadder block to the most significant sub-adder block constituting the ALA. The simulation results show that for 16-bit ALAs, the proposed MED and MSED computation algorithms are, respectively, about 2.4 × 103and 2.6 × 103times faster than Monte Carlo (MC) simulation with 216 samples. Similarly, WCE computation method is 10.4 × 103times faster compared to the MC simulation with 216 samples.

This brief proposes robust adaptive filtering algorithms and their VLSI architectures for sparse system identification under impulsive noise. Several robust algorithms are derived by combining error nonlinear adaptive filtering algorithms with proportionate adaptation. We make a comparative study of the derived algorithms and their VLSI architectures in terms of convergence rate and hardware complexity to show that the hardware overhead is negligible for the achieved improvement in robustness.

In error-tolerant applications, approximate adders have been exploited extensively to achieve energy efficient system designs. Mean error distance is one of the important error metrics used as a performance measure of approximate adders. In this work, a fast and efficient methodology is proposed to determine the exact mean error distance in approximate lower significant bit adders. A detailed description of the proposed algorithm along with an example has been demonstrated in this paper. Experimental analysis shows that the proposed method performs better than existing Monte Carlo simulation approach both in terms of accuracy and execution time.

Scan based error detection architectures for hybrid, carry-free radix-2 and radix-4 addition operations using redundant arithmetic are presented in this paper. Such addition operations have been chosen as representative examples as they are free from carry propagation delay and are ideal from the viewpoint of technology mapping of the logic elements onto the FPGA slices. The architectures have been conceived following the design paradigm of target FPGA specific primitive instantiation coupled with location constraints, without any degradation in the speed of circuit operation as compared to the original circuit implementation without the scan operation. Our architectures also comfortably outperform the existing state-of-the-art error detection architectures in terms of speed and consumes less area.

This paper presents a framework based on the logarithmic number system to implement adaptive filters with error nonlinearities in hardware. The framework is demonstrated through pipelined implementations of two recently proposed adaptive filtering algorithms based on logarithmic cost, namely, least mean logarithmic square (LMLS) and least logarithmic absolute difference (LLAD). To the best of our knowledge, the proposed architectures are the first attempts to implement both LMLS and LLAD algorithms in hardware. We derive error computing algorithms to realize the nonlinear error functions for LMLS and LLAD and map them onto hardware. We also propose a novel variable-α scheme to enhance the original LMLS algorithm and prove its robustness and suitability for VLSI implementations in practical applications. Detailed bit width and error analysis are carried out for the proposed VLSI fixed point implementations. Postlayout implementation results show that with an additional multiplier over conventional least mean square (LMS), 7-dB improvement in steady-state mean square deviation performance can be achieved and with the proposed variable-α scheme, 12-dB improvement can be achieved without compromising the convergence. We will show that LMLS can potentially replace LMS in practical applications, by demonstrating a proof-of-concept by extending the framework to transform domain adaptive filters.

This paper presents an adaptive encoding framework for the reduction of transition activity in high-capacitance off-chip data buses, since power dissipation associated with those buses can be significant for high-speed communication. The technique relies on the observation of data characteristics over fixed window sizes and formation of cluster with bit lines having highly correlated switching patterns. The proposed method utilizes redundancy in space and time to prevent loss of information while retrieving data. We present analytical and experimental analyses, which demonstrate the activity reduction of our encoding scheme for various data. The extra power cost due to the encoder and decoder circuitry along with redundancy is offset due to reduced number of off-chip transitions.

In this paper, we have proposed a new defect tolerant technique by adding redundancy at transistor level, where each transistor is replaced by three transistors placed in a special way such that reliability of the whole structure increases. The new triple-transistor redundancy technique offers a good reliability at lower area and delay overheads compared to most of the popular static fault tolerant techniques and can be used in designing various fault tolerant digital architectures to increase their reliabilities.

This paper describes a sampled analog architecture for computing 2D DCT of an 8 /spl times/ 8 image block using switched capacitor principle, with capacitance switching. The input sample stream is applied to a bank of capacitors and multiplied by all the deduced 2D DCT coefficients simultaneously using capacitor ratios. These capacitors are switched concurrently with the help of a switching matrix, to realize switched capacitor integrators for performing necessary addition/subtraction. The complexities of the circuitous two-step 2D DCT involving two separate 1D DCTs have been removed. Proposed architecture is regular, flexible and can be used as building block for real-time image and video compression, with the same accuracy as its digital counterpart.

This paper presents a class of pipelined CORDIC architectures for the LMS-based transversal adaptive filter. For this, an alternate formulation of the LMS algorithm is considered, obtained by expressing the mean square error as a convex function of a set of angle variables that are monotonically related to the filter tap weights. The proposed architectures employ microlevel pipelining and are adjustable to strike tradeoffs between throughput efficiency vis-a-vis hardware complexity.