Although the advent of microprocessors has put considerable computing power in the hands of large numbers of users, there is still an important group who have yet to benefit fully from large scale integration. As a step in the direction of rectifying this situation, a highly flexible chip set is being designed, with a view to reducing the cost of a powerful floating point processor by a factor of about 4. Processing speed will be up to twice that of an equivalent unit built from MSI devices, before allowance is made for savings on wiring delays. It will be possible to construct a unit satisfying all published standards, proposed and existing (de facto), as well as permitting a number of extensions not specifically in these standards. At a cost between 100 and 150 ICs, and with a floating-point add time of around 120nS, the proposed unit is cost-effective compared to currently available coprocessors.

MU6-G is a high performance machine useful for general or scientific applications. Its order code and architecture are designed to be sympathetic to the needs of the operating system and to both the compilation and execution of programs written in high level languages and to support a word size suitable for high precision scientific computations. Advanced technology, coupled with simplicity of design, is used to achieve a high and more readily predictable performance. Innovative features include the unique organisation of the virtual memory mapping hardware and the use of a combined operand and instruction buffer-store, accessed using virtual addresses. Fault diagnosis is aided by the inclusion of a microprocessor based diagnostic controller which has read/write access to all bistable devices in the machine and has control of the system clock. The paper includes a description of the various functional units and gives estimates of expected performance.

A multicomputer system is described incorporating an exchange which can connect up to 12 units. A description of the overall architecture is followed by a detailed discussion of the exchange design. This includes a storage transfer unit which has a maximum throughput of 89 Mbytes/s. A review of the timing and technology, and error analysis conclude the paper.

A consequence of the pre-addressed fixed-length data block format which the Atlas magnetic tape system uses is that tapes with this layout have to be provided from ‘new’ tapes before the system can even operate. To avoid the necessity of building expensive and elaborate off-line equipment, small modifications were included in the design of the basic Atlas tape system to provide this necessary facility. The process is performed using Atlas itself, but because of the computer's time-sharing techniques only a small fraction of the computer's capability is used up. The paper provides a factual description of the tape testing and addressing facilities, explaining the reasons for the major decisions involved in the design.

After a brief survey of the basic Atlas machine, the paper describes an automatic system which in principle can be applied to any combination of two storage systems so that the combination can be regarded by the machine user as a single level. The actual system described relates to a fast core store-drum combination. The effect of the system on instruction times is illustrated, and the tape transfer system is also introduced since it fits basically in through the same hardware. The scheme incorporates a ``learning'' program, a technique which can be of greater importance in future computers.