EDBT 2026 Demo / reviewers in the wild / expert
Sieji Kimura
dblp:53/2667
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 1983
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 96% Integrated circuit design · 4% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.0 | 2 | 1983 | An Automatic Routing Scheme for General Cell LSI · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983 SHARPS: A hierarchical layout system for VLSI · DAC 1981 |
Electronic design automation › physical design › routing
detailed routing |
0.0 | 1 | 1983 | An Automatic Routing Scheme for General Cell LSI · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983 |
Electronic design automation › physical design › routing
global routing |
0.0 | 1 | 1983 | An Automatic Routing Scheme for General Cell LSI · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983 |
Electronic design automation › physical design
routing |
0.0 | 1 | 1983 | An Automatic Routing Scheme for General Cell LSI · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983 |
Electronic design automation › physical design › layout analysis
hierarchical layout analysis |
0.0 | 1 | 1981 | SHARPS: A hierarchical layout system for VLSI · DAC 1981 |
Electronic design automation › physical design
layout system |
0.0 | 1 | 1981 | SHARPS: A hierarchical layout system for VLSI · DAC 1981 |
Integrated circuit design
VLSI design |
0.0 | 1 | 1981 | SHARPS: A hierarchical layout system for VLSI · DAC 1981 |
Methods — techniques the papers use, named apart from their topics
net ordering · 0.0grid-free routing · 0.0hierarchical layout · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1983 | An Automatic Routing Scheme for General Cell LSIabstractAn automatic routing scheme intended dedicatedly for general cell LSI is described, which is constructed of a number of algorithms such as for net ordering, global routing, and detailed routing. This scheme is distinctive in that channel constraint loops are broken automatically at the stage of global routing, and a grid-free routing scheme is employed at the state of detailed routing. The routing program based on this scheme has been incorporated into a design system for LSI which is at work in practice. A part of implementation results are also shown. Sieji Kimura, Noboru Kubo, Toru Chiba, Ikuo Nishioka |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 1981 | SHARPS: A hierarchical layout system for VLSI
Toru Chiba, Noboru Okuda, Takashi Kambe, Ikuo Nishioka, Tsuneo Inufushi, Sieji Kimura |
DAC | 6 |