International audience

This paper explores the application of reinforcement learning algorithms to the problem of calibrating and optimizing the performance of an integrated millimeter-wave (mmW) power amplifier (PA). The proposed calibration algorithm is aimed at compensating performance degradation while optimizing power efficiency, by finding the optimum values of a set of on-chip tuning knobs. The developed calibration solution is based on a multiagent deep reinforcement learning algorithm, in which a number of reinforcement learning agents learn to collaborate in order to optimize the complete set of specifications of the circuit under calibration. The proposed technique is validated based on post-layout simulation results of a tunable 60 GHz PA case study implemented in STMicroelectronics 55 nm CMOS technology.

This work presents a novel Single Capacitively Coupled (SCC) ring Voltage-Controlled Oscillator (VCO) designed for wideband N-path systems. It reduces the number of capacitors by half compared to the Double Capacitively Coupled (DCC) design, potentially requiring less silicon area while maintaining improved phase noise performance compared to the pseudo differential ring VCO, and with less power consumption than the DCC design. The proposed SCC VCO, tunable from 0.3 to 3.0 GHz, achieves the lowest power consumption among the state-of-the-art designs compared, consuming just 0.48 mW at 3 GHz, with a phase noise of -76.5 dBc/Hz at 1 MHz offset. Consequently, the figure of merit (FOM) remains modest at -147 dBc/Hz, comparable to other designs but leaving room for improvement. The analysis reveals that improper configuration may lead to unwanted oscillation modes of the three VCOs analyzed, making a startup circuit essential for stable operation. These results position the SCC ring VCO as a promising candidate for low-power, high-performance applications.

Due to their continuous nature across all the inversion regions of MOS transistors, charge-based models are a promising analytical tool for preliminary design sizing that brings the advantages of simplicity and accuracy. These models allows for the efficient exploration of a design space while reducing the computational burden associated to complete compact models. In this paper, a method to analyze the dynamic and frequency performances of a single-ended inverter-based ring oscillators is presented. The proposed analysis is based on the time-domain evaluation of the loading currents, as well as of the input and output voltages of the ring oscillator’s constituent inverters, using the Euler method. The novelty of this approach is the use of a 5-parameter charge-based model that considers short-channel effects. The proposed analysis is tested on a practical implementation in 28nm FD-SOI CMOS technology and the results, including the maximum achievable frequency and dynamic efficiency are compared to those obtained using the UTSOI2 model.

In this study, a harmonic-rejection N-path mixer is designed, implemented, calibrated, and measured. The proposed mixer features a wide bandwidth suitable for low-power multi-standard RF front-end receivers while keeping low complexity by opting for only 5 paths rather than 10 and only one stage to perform harmonic rejection up to the$7^{th}$local oscillator (LO) harmonic. This work employs a calibration strategy to prevent mismatches due to the fabrication process from affecting the system performance. The 0.17-1.2-GHz RF front-end mixer is fabricated in a 28-nm FDSOI technology. Measurements show a harmonic rejection higher than 45 dB for the$3^{rd}$,$5^{th}$, and$7^{th}$LO harmonics, 13 dB gain, 13.3 dB NF, −3.5 dBm in-band IIP3. The total power consumption is only 22 mW for a surface area of$0.62\times 0.22~mm^{2}$.

This article proposes a general approach to accurately model the N-path filters and mixers, with the double purpose of bringing a better insight in the frequency transposition phenomena and opening the door towards a more general discussion concerning NPF-NPM and their outstanding properties as passive circuits. Thanks to a Fourier transform analysis, some mathematical equations are rigorously derived for both filtering and mixing voltage gains. The analysis is compared with ideal simulations for various sets of parameters: source impedance$R_{a}$, load impedance$R_{L}$, switch resistance$R_{sw}$, capacitive path$C_{L}$. Some error curves are extracted validating the initial hypotheses for the model in a given range of capacitances values. As a proof of concept, it is shown that the model complies with the measurements results with very good accuracy. The error is less than 10.5% on the two first harmonics prediction.

This work presents a survey based on more than 200 published papers related to sub-6 GHz wideband LNAs [1]. It investigates the trends with respect to the technology node. Moreover, it proposes a comparison between the most used topologies regarding their main performance metrics such as the gain, bandwidth, noise figure, power consumption and linearity. Based on this study, analytical predictions can be verified and appropriate architectures targeting a given set of specifications can be easily selected. The analysis highlights also the performance improvements and design trade-offs of design enhanced solutions such as noise cancelling and gm-boosting architectures.

This paper presents a simple and efficient methodology for LNA design which uses the inversion level of the transistor as a design parameter in order to optimize the energy efficiency. The method uses a simple but accurate 7 parameter-based model valid in all regions of operation and allows an accurate preliminary sizing based on an analytical study. The proposed model describes the main short-channel effects in advanced technologies and allows an analytical evaluation of the LNA nonlinearity. A use case using a 28 nm FD-SOI technology is proposed to reflect that the methodology is well suited for designs at weak to moderate inversion level in an advanced technology for which simulation-based studies are often used for early sizing.

This paper presents an innovative integrated load-pull bench at 160 GHz. The proposed system, which is designed in a 55-nm BiCMOS technology, is tailored to deal with all of the measurement functions including signal generation, shaping, and magnitude and phase measurement. This system will allow precise characterization of Devices-Under-Test (DUTs) (i.e., circuits and/or devices) when integrated together with the DUT. In addition, the proposed system could also be envisioned as a System-on-Chip (SoC) that, when reported into an RF probe, could serve as a test bench for any integrated circuit.

This article presents a matrix-based model suitable for millimeter-wave (mm-wave) distributed amplifier (DA) design, based on four-port chain (ABCD) formalism. Using this model, an algorithmic design methodology for DA, built upon a loss-compensation technique, is also provided that maximizes its bandwidth (BW) for a given flatness goal. The design approach provides fast and accurate design space exploration (DSE) plots that enable one to examine the tradeoffs between gain, BW, power consumption ($\mathrm {P}_{\mathrm {DC}}$), and the size and number of Gm-cells, and arrive at the optimum desired design. Its benefit is demonstrated by means of a computer-automated design (CAutoD) example where 55-nm CMOS STMicroelectronics (ST) process is used and DAs with BWs$\ge80$GHz were desired to be sized; reporting 216 feasible DA options to explore from. The global optimum DA amplifying frequencies up to 100 GHz was then implemented as a circuit prototype. The measured DA provided 6.7-dB power gain while requiring a power consumption ($\mathrm {P}_{\mathrm {DC}}$) of 30 mW from a 1.2-V supply. The chip occupied a total area of 0.83 mm2. Compared to state-of-the-art FET-based small-signal DAs, the fabricated circuit reports the highest gain-bandwidth product (GBP) per$\mathrm {P}_{\mathrm {DC}}$(${\mathrm {GBP}} \mathord {\left /{ {\vphantom {{\mathrm {GBP}} \mathrm {P}_{\mathrm {DC}}}} }\right. } \mathrm {P}_{\mathrm {DC}}$) of 6.01 GHz/mW while being power-efficient.

In this paper, the design of a 77.3 GHz Standing-Wave oscillator (SWO) is presented. The proposed SWO relies on the distribution of varactors along an asymmetrical slow-wave coplanar stripline, which enables the improvement of the quality factor of the tunable resonator, resulting in superior performance in terms of phase noise and DC-to-RF efficiency. The design methodology, based on the use of analytical models and abaci, is presented in detail and applied to a design in a 55-nm CMOS technology. With a core consumption of 15.1 mW, the proposed SWO operates from 76.09 GHz to 78.60 GHz and presents a phase noise of -115.1 dBc/Hz at 10 MHz offset, leading to a Figure of Merit (FOM) of -181 dBc/Hz. The DC-to-RF efficiency obtained is 3.1%.

This paper presents an innovative Through-Load element aimed at characterization applications at mm-wave frequencies. The proposed structure can behave as a Through connection or as a 50-Ω load depending on a DC control voltage. Among other potential applications, this system can be used to implement a transfer switch or an attenuator. A demonstrator was fabricated and measured in the STM 55-nm BiCMOS technology. Over a wide bandwidth, from 55 GHz up to 170 GHz, experimental measurements demonstrate a maximum 1.6-dB of insertion loss when behaving as a Through connection and a minimum 14-dB of insertion loss when behaving as a 50-Ω load. In both cases, the return loss is better than 10 dB. The insertion loss at 90 GHz is 0.6 dB for the Through connection and 20 dB for the 50-Ω load connection.

The test of analog, mixed-signal and RF (AMS-RF) circuits is still considered as a matter of human creativity, and although many attempts have been made towards their automation, no accepted and complete solution is yet available. Indeed, capturing the design knowledge of an experienced analog designer is one of the key challenges faced by the Electronic Design Automation (EDA) community. In this paper we explore the use of causal inference tools in the context of AMS-RF design and test with the goal of defining a methodology for uncovering the root causes of performance variation in these systems. We believe that such an analysis can be a promising first step for future EDA algorithms for AMS-RF systems.

Integrated millimeter-wave (mm-wave) circuits fabricated in current nanometric processes are especially sensitive to process variations. This issue produces shifts in the circuit performance that may significantly reduce the fabrication yield. In this line, per-die characterization and trimming are usually required for mm-wave integrated circuits, but this is an expensive and time-consuming task to be performed at the production line. Embedded calibration for mm-wave circuits is an appealing alternative to enhance yield that may overcome some of these issues. In this work we present a two-stage 60 GHz power amplifier (PA), designed in STMicroelectronics 55 nm CMOS technology, that features a one-shot calibration procedure for process variation compensation based on non-intrusive process monitors. We present the design of a tuning knob based on variable decoupling cells which have been implemented within the PA for calibration purposes. The proposed one-shot calibration procedure reads the output of the embedded process monitors and then relies on a machine learning regression model to find the best configuration of the tuning knobs for optimizing the performance of the circuit and enhance fabrication yield.

The functional test of millimeter-wave (mm-wave) circuitry in the production line is a challenging task that requires costly dedicated test equipment and long test times. Machine learning indirect test offers an appealing alternative to standard mm-wave functional test by replacing the direct measurement of the circuit performances by a set of indirect measurements, usually called signatures. Machine learning regression algorithms are then used to map signatures and performances. In this work, we present a generic and automated methodology for finding an appropriate set of indirect measurements and assisting the designer with the necessary Design-for-Test circuit modifications. In order to avoid complex design modifications of mm-wave circuitry, the proposed strategy is targeted at generating a set of non-intrusive indirect measurements using process variation sensors not connected to the Device Under Test (DUT). The proposed methodology is demonstrated on a 60 GHz Power Amplifier designed in STMicroelectronics 55 nm BiCMOS technology.

Beam-forming techniques using phased arrays are one of the most promising solutions for the practical implementation of future high-data-rate point-to-point communication protocols. The functionality of phased arrays is based on the use of phase shifters that should provide an accurate and controllable phase difference between the different paths of the array. However, the integration of phase shifters in current nanometric technologies is prone to imperfections that may affect the intended phase shift and degrade the performance of the antenna array. This requires extensive testing and calibration and represents a bottleneck in the production line of these system. In this work, we propose a simple Oscillation-Based Test technique that may be suitable for Built-In Self-Test applications of phase shifters. The technique is demonstrated on a Reflection-Type Phase Shifter implemented in a 55 nm BiCMOS technology. Electromagnetic and electrical simulation results show the feasibility of the proposed technique.

In this paper, we propose a low-power technique, called RF power gating, which consists in varying the active time ratio (ATR) of the RF front end at a symbol time scale. This technique is especially well suited to adapt the power consumption of the receiver to the performance needs without changing its architecture. The effect of this technique on the bit error rate (BER) performances is studied for a basic estimator in the specific case of minimum-shift keying signaling. A system-level energy model is also derived and discussed to estimate precisely the power reduction based on the characteristics and the power consumption of each block. This model allows highlighting the different contributors of the power reduction. The BER results and the energy model are finally merged to determine the best ATR meeting the design constraints. Applying this technique to the IEEE 802.15.4 standard, this paper shows that an ATR of 20% is a good tradeoff to meet the packet error rate constraint while maximizing the energy reduction ratio. Using typical block power consumptions, an energy reduction ratio around 20% can be reached. Even better energy reduction ratios (~60%) are also achievable when most of the blocks are power-gated.

In this paper, the impact on the bit error rate (BER) of the periodic non-uniform sampling implied by a power-gated analog-to-digital converter (ADC) is addressed in the specific case of a binary CPFSK receiver. Analytical and simulated lower bounds of the BER in an additive white Gaussian noise channel for several phase-based estimators are presented and discussed together with their dependency on the sampling synchronization. The main results are summarized in a practical abacus for Minimum Shift-Keying (MSK) modulation. Finally, the proposed techniques are evaluated against the IEEE 802.15.4 specification in MSK mode and lead to an active time ratio of the ADC of only 10% or less. Application of the proposed technique to a more competitive IEEE 802.15.4 compliant architecture available in the literature is also presented.