This paper presents an energy-efficient low-noise dynamic comparator with a passive charge-pump pre-amplifier (CPP). We demonstrate the effectiveness of a passive pre-amplifier, cascaded to a dynamic comparator, to reduce input referred noise (IRN) of the comparator by a factor of pre-amplifier gain. Furthermore, the passive pre-amplifier, originating from a switched-capacitor amplifier, consumes only switching power, making it less burdensome to add it to the dynamic comparator. The proposed dynamic comparator, designed in a 180-nm CMOS process, achieves 37.1 µV of IRN, 817 fJ of energy per conversion under a 1.2-V supply, and a sampling frequency of 80 kHz. This results in a figure-of-merit of 1.12 nJ·µV2.

This paper presents a galvanic-coupled body channel communication (GC-BCC) transceiver (TRX) system with serpentine-interconnection electrodes for applications in joint replacement surgeries, such as total knee replacement (TKR). The proposed system consists of a GC-BCC transmitter (TX) implanted inside the body and an external receiver (RX). Implanted devices with high stiffness may cause tissue damage or compromise long-term stability due to the inherent curvature and elasticity of the human body. Given these characteristics of the human body, implantable devices should feature flexible and stretchable structures that conform to the body’s contours and minimize such risks. To address this requirement, we propose a serpentine-interconnection electrode pair, which provides mechanical compliance and can replace the conventional straight-interconnection interface. This interconnection enables reliable signal transmission in the MHz band, demonstrating its suitability for both implantable TX and external RX in medical applications. The GC-BCC TX and RX are fabricated using 0.18 µm BCD and 0.18 µm CMOS processes, respectively, achieving a data rate of 20 Mb/s with a bit error rate (BER) of less than 10-6. The TX and RX chips consume an active area of 3.2 mm2and 2.5 mm2and consume a power of 675 µW and 4.32 mW, respectively. The performance of the proposed system is validated through ex-vivo experiments using 10-mm thick porcine tissue.

This paper presents a low input-referred-noise (IRN) discrete-time (DT) delta-sigma modulator (DSM) for precise biopotential-signal acquisition. The proposed structure utilizes a 1st-order input-impedance-boosted kT/C-noise-cancellation integrator combined with a 2nd-order noise-shaping SAR (NS-SAR). The proposed integrator cancels the kT/C noise generated during the sampling and integrating phases by using feedback capacitors for the cancellation loop while boosting the input impedance. This novel integrator can utilize smaller capacitors for sampling and integration than the standard design without any performance degradation. A single amplifier in the integrator is reused for sampling, kT/C noise cancellation, and integration to reduce power consumption. The NS-SAR is utilized instead of an amplifier-based multistage integrator structure to attain high resolution while maintaining low power consumption. The prototype IC, simulated using a 65-nm CMOS process, achieves a 90.5-dB SNDR across a 1-Hz-to-1-kHz bandwidth with a 300-mVPPinput, yielding a 99.8-nV/$\sqrt {{\text{Hz}}} $ IRN and a FoMSNDRof 173.4 dB. These results indicate that the proposed DSM can properly acquire biopotential signals from both muscular and cardiac sources.

This paper presents a time-multiplexed neural recording readout IC (ROIC) for interfacing a high-density microelectrode array (MEA) with integrated switches. Time-domain multiplexing (TDM) allows multiple electrodes to share an analog front-end (AFE) and ADC to save chip area. The design features an input impedance (ZIN) boosting technique using dual positive feedback loops (DPFLs) to cancel internal and external parasitic capacitances across multiple channels using shared DPFL capacitors. Thus, the effective area and number of capacitors to be trimmed for the DPFL technique are also reduced by the multiplexing ratio. The system is implemented in a 180nm CMOS process and uses a chopped capacitively coupled instrumentation amplifier (CCIA) for a fixed gain and low noise, followed by a windowed integration sampling amplifier to reduce the system’s noise equivalent bandwidth and provide programmable gain. The neural recording ROIC occupies an active area of 0.124mm2/ch and consumes 8.81μW/ch. The sampling rate is 20kHz/ch with a simulated input-referred noise of 5.95μVrms from 1Hz to 10kHz. The DPFL capacitors are fully shared across channels and help boost ZINto 840MΩ, demonstrating the effectiveness and suitability of the DPFL ZIN-boosting technique for TDM chopped CCIA AFEs.

This work presents a compact, self-powered pressure sensor based on a triboelectric nanogenerator (TENG), which is developed for total knee replacement (TKR) implants. Unlike conventional bulky and inefficient systems with separate attenuators and signal processing units, this design seamlessly integrates a pressure sensor within an energy-efficient energy harvesting (EH) circuit. The system features a bidirectional, high-voltage (HV) four-input buck converter with a newly proposed HV protector, enhancing EH efficiency across four different input voltages. The converter achieves a maximum end-to-end efficiency of 79.21%. Additionally, the pressure-sensing circuits offer accurate readouts by sampling the HV open-circuit voltages (VOC) from TENGs using a VOCsampler without the need for an attenuator. Compared to state-of-the-art solutions, this work not only achieves competitive energy harvesting performance but also introduces, for the first time, a fully integrated pressure-sensing function.

Despite the energy efficiency of memory-centric deep neural network (DNN) computations, the nonlinearities inherent in existing processing-in-memory (PIM) architectures cause severe accuracy drops. These imperfections necessitate additional methods to correct inaccurate vector-matrix multiplication (VMM) results. To address this issue without modifying DNN weights, we first propose an input sparsity-based error compensation method. This approach dynamically corrects accumulated errors along the column direction of the non-volatile memory (NVM) array using pre-collected errors and input characteristics. We then present a new PIM architecture along with the proposed compensation scheme by slightly modifying the existing analog-to-digital converter (ADC) or adding a few extra rows to the NVM array. Experimental results show that the proposed work mitigates the nonlinear effects of various emerging memory cells, achieving near-ideal DNN accuracy with negligible hardware overheads.

A hybrid high-voltage regulating charge pump is proposed for point-of-care electrokinetic concentration chip applications. The hybrid charge pump is composed of three cascaded sub-pumps. High efficiency, minimized area, wide output current range, and high regulated output voltage are achieved by selecting charge pump architectures that provide high voltage conversion gain with less number of stages. The proposed charge pump is designed and fabricated in 180 nm BCD process. Simulation results show that the proposed system provides a maximum efficiency of 48.26%, while providing a maximum output voltage of 65 V.

This paper proposes an accelerometer readout integrated circuit (IC) that supports micro-electromechanical systems (MEMS) piezoresistive accelerometers designed for ultrahigh-G measurements. The IC utilizes an adaptive gain path and shock detector to address circuit saturation and settling issues when shock signals are injected. This enables the use of a capacitive coupling structure that mitigates the offsets resulted from sensor mismatches. Additionally, the capacitive coupling allows to employ different supply voltages for the MEMS sensor and the IC. Thus, the IC can use a much lower supply voltage for low power consumption while the MEMS sensor can use a high supply voltage for better output sensitivity. By bypassing a gain stage for lower overall channel gain during the shock signals, the system can ensure the acquisition of accurate signal immediately after the shock signal. The IC was fabricated in 180nm CMOS technology, consuming 1.02 mW from a 1.8V supply voltage. Measurement results show a 85% and 89% enhancement in the common-mode offset and a gain error for a 1-ms shock signal when the proposed adaptive gain is used. The IC with a MEMS piezoresistive accelerometer is also validated by a 50 kG shock survival test.

The measurement of small variation of the bioZ having a substantially large baseline impedance is a great challenge, requiring a wide dynamic range (DR) and a high signal-to-noise ratio (SNR). This paper presents a new impedance measurement architecture based on Δ-ΔΣ modulator with capacitive-feedback baseline cancellation. The readout front-end (RFE) of the integrated circuit (IC) is configured with a first-order Δ-ΔΣ modulator and a feedback capacitive digital-to-analog converter (CDAC) that minimize the power consumption. The front-stage Δ-modulation allows to achieve a wide input DR of 30 kΩ by eliminating the large static baseline impedance with no static current consumption. It also mitigates the input-dependent noise characteristic of the current balancing instrumentation amplifier (CBIA) significantly. The current generator (CG) generates a square wave for the excitation current with a current magnitude ranging from 5 μApkto 100 μApkover a frequency range from 1 kHz to 1024 kHz. The chopping and dynamic element matching (DEM) techniques are adopted in the bandgap reference (BGR), CG, and current-DAC (IDAC) to mitigate their flicker noises, which dominate the signal bandwidth (<10 Hz). The proposed IC designed in a 180-nm CMOS process consumes only 7.64 μW for the I path of the RFE, achieving a maximum SNR of 97.7 dB.

This paper presents a high-throughput impedance readout IC with a novel synchronous cyclic integration technique using a scalable capacitive transimpedance stage. The proposed technique removes the need for the low pass filter (LPF) in the readout chain and performs the I/Q demodulation within a single cycle. Fabricated in a 180-nm CMOS process, the proposed IC consumes 50 μW from a 1.2-V supply. It can measure impedances over a frequency of 100 Hz to 100 kHz with an accuracy of 99.7% and can achieve a throughput of 50 kSps at 100 kHz input frequency.

This paper presents a 72-channel resistive-sensor interface integrated circuit (IC). The proposed IC includes 8 sensor oscillators and 8 time-to-digital converters (TDCs), and each set of a sensor oscillator and a TDC is time-multiplexed to measure from 9 sensors. Consequently, it attains impressive energy efficiency of 310 pJ per channel. Employing a time-domain interface approach, the IC directly converts sensor resistance into time, extending its measurement capabilities up to 10 MΩ. It also takes advantage of a high-energy-efficiency phase-locked loop (PLL), resulting in a high signal-to-quantization-noise ratio (SQNR) that reaches the intrinsic signal-to-noise ratio (SNR) of the sensor oscillator. This results in an effective number of bits (ENOB) of 9.3 bits when 310 pJ is consumed for each channel. The ENOB can be adjusted through external FPGA control, and the maximum ENOB achieved is 14.1 with an oversampling ratio (OSR) of 256. The proposed IC, designed and fabricated in a 180-nm CMOS process with an active area of 0.015mm2, consumes only 15.07 μW per channel, resulting in a channel-specific Walden figure of merit (FoM) of 0.48 pJ per conversion step. Furthermore, by adjusting the OSR, the IC achieves an outstanding Schreier FoM of 159.8 dB in scenarios requiring high resolution.

This study introduces a partially reconfigurable system-on-chip (SoC) platform leveraging dynamic resource management facilitated by a dynamic reconfigurable control processor (DRCP). By addressing the inherent reconfiguration time overheads of reconfigurable SoCs, the study demonstrates performance improvements through a runtime resource management strategy. The introduced management scheme effectively reduces the frequency of reconfigurations, thus lessening the associated overheads and increasing the operational efficiency of the SoC platform, which is designed to support on-chip multi-tenancy. Utilizing DRCP for dedicated resource management, the proposed SoC platform exhibited substantial reductions in reconfiguration times. When the partially reconfigurable SoC platform employed four partial regions (PRs), the reconfiguration counts decreased by 37.6%. Furthermore, upon extending the PRs to eight, there was a notable reduction in reconfiguration counts, achieving a decrease of 47.0%.

This paper presents a low-noise, low-power biopotential recording IC with programmable gain and a reconfigurable number of channels. The analog front end (AFE) with tunable gain from 20 dB to 54 dB can select the number of channels and combination of channels for reconfigurable signal acquisition capability. The proposed hybrid DC-servo loop is employed for fast electrode DC offset (EDO) cancellation up to 240 mV within 10 ms. Designed in a 0.18-μm CMOS process, the proposed IC achieves input-referred noise (IRN) of 1.12 μVrms at the highest gain mode. The overall system achieves 66.35-dB SNDR with the successive approximation register (SAR) analogto-digital converter (ADC) and consumes 5.74 μW with 0.40 mm2 area per channel.

This paper presents a ΔΣ-modulator-based reconfigurable multimodal sensor interface integrated circuit (IC), offering a novel approach to the multimodal measurement of voltage, capacitive, and current signals. A direct-conversion structure is employed in the multimodal sensor interface, and its reconfigurable ΔΣ modulation scheme ensures compact die area, high energy efficiency, and enhanced dynamic range. Fabricated in a 180-nm CMOS process, the multimodal sensor interface achieves measured dynamic ranges of 70.6 dB, 97.8 dB, and 60.0 dB for voltage, capacitance, and current modes, with measured power consumptions of 22.2 μW, 23.0 μW, and 37.7 μW, respectively. The proposed system demonstrates significant improvements in the dynamic range relative to power consumption compared to other state-of-the-art multimodal sensor interface IC designs.

This paper presents a neural recording integrated circuit (IC) with a DC-coupled VCO-based continuous-time ΔΣ modulator with a novel input transistor ΔΣ digital-to-analog converter (DAC) technique. The input transistor operating as a transconductor is implemented in the form of a transistor DAC (TR-DAC) consisting of multiple transistors, which enables the ΔΣ operation according to the output digital code. Notably, this topology isolates the input from the feedback loop, resulting in exceptionally high input impedance. Furthermore, the input transistor itself functions as a ΔΣ DAC, eliminating the need for additional passive or active DAC components. Consequently, the proposed design significantly reduces area consumption, enabling its application to future scalable brain-machine-interface (BMI) systems. The proposed IC designed in a 0.18-µm CMOS process consumes only 4.7 µW with a bandwidth of 5.12 kHz. Thanks to its DC-coupling characteristics and small input parasitic capacitance, the design achieves a high input impedance of 1.26 GΩ. Furthermore, the chip occupies a compact area of 0.054 mm2per channel, while the input TR-DAC used as a ΔΣ DAC occupies only 0.008 mm2.

This paper presents a novel high-throughput impedance measurement integrated circuit (IC) with baseline cancellation for neural EIT applications. The proposed technique uses a peak detector to obtain impedance magnitude every cycle. After taking the peak, the peak detector is reset to a DC baseline voltage. And, the signal swinging between the amplitude and the reset baseline is further amplified, allowing to measure small impedance variations even with a large baseline. The proposed IC fabricated in a 180-nm standard CMOS process can measure impedance variations of >0.1% baseline can be measured, while achieving high throughput of 100 kS/s at 100 kHz input frequency. Scalable design allows the proposed IC to support a wide frequency range from 100 Hz to 100 kHz with a power consumption from 31 μW to 39 μW from a 1.2-V supply.

Recent advancements in brain-computer interface (BCI) technology for steady-state visual evoked potential (SSVEP)-based target identification have shifted from traditional linear algebra (LA) techniques to more sophisticated neural network (NN) approaches, driven by their increased accuracy and consistent performance across different subjects. However, adopting NN-based algorithms has introduced complexities in wearable BCI systems, mainly due to their extensive parameter sets that demand significant memory capacity. Moreover, the computational intensity of these models requires reevaluating hardware architectures. Additionally, the advent of Transformer-based models has further advanced the state of the art, providing even higher accuracy and reduced variability in cross-subject performance, placing greater demands on hardware resources. This paper provides an overview of recent algorithmic progress in SSVEP-based target identification. Also, it proposes considerations for the hardware architecture needed to efficiently support the computation of cutting-edge Transformer-based models in wearable BCIs from the perspective of algorithm-hardware co-design.

In analog-mixed-signal (AMS) compute-in-memory (CIM) systems, the two’s-complement (2SC) format provides better area efficiency than the sign-and-magnitude (SNM) one. However, the 2SC format exacerbates the challenges of AMS-CIM systems, suffering from significant DNN accuracy drop under process variations and high computation currents from activating multiple WLs. In the 2SC format, ‘0’ and ‘1’ are nearly balanced for all logical-order bits, unlike ‘0’-skewed higher-order bits in the SNM format. Consequently, the 2SC-based AMS-CIM systems have much more on-cells than the SNM-based counterpart, deteriorating the above challenges. We propose Skew-CIM, a software-hardware co-design technique to relax these challenges. Our proposed weight skewing (WESK) breaks the ‘0’ and ‘1’ balance at the software level. The potential accuracy drops resulting from WESK are successfully compensated by retraining DNNs. The offsets caused by WESK can be easily corrected using online hardware-level processing. Our Skew-CIM technique can be applied to most AMS-CIM systems with memories showing large on-off cell current ratios. As an example, we use it in a custom-designed 8T-SRAM-based CIM device, demonstrating a significant reduction in the DNN classification error by 7.6 times compared to the 2SC-based AMS-CIM without our Skew-CIM technique. Furthermore, our Skew-CIM markedly enhances energy efficiency by up to 39.9%, outperforming conventional SNM-based AMS-CIM systems.

We present an energy-efficient, scalable neural stim-ulation IC with adaptive dynamic voltage switching, which can be applied to cochlear implant (CI) systems. The stimulation IC generates three different voltage outputs by operating a single-inductor multiple-output (SIMO) boost converter, while an adaptive dynamic voltage switching (ADVS) block selects an appropriate supply voltage for each stimulation channel among those SIMO outputs. The SIMO boost converter is designed to operate over a wide range of its input, which is the rectifier output of the wirelessly powered CI system. The ADVS control as well as the stimulation amplitude control are performed remotely by an external sound processor (SP) of the CI system in real time. For the ADVS operation, the compliance voltage of each stimulation channel is monitored to be used as an input signal for switching to the appropriate supply voltage for the corresponding stimulation channel. The dynamic voltage switching operation is carried out in sub-us, The stimulation IC with ADVS is implemented using a 180-nm BCD process, and its operation and performance are verified through post-layout simulations. When applying a real audio input using decoded data from a prototype SP, the proposed stimulation IC with ADVS demonstrates 36.6% energy saving compared to the conventional stimulation IC.

A super-high-resolution capacitance-to-digital converter (CDC) capable of reaching sub-aF capacitance resolution has been proposed. The CDC employs a continuous-time (CT) low-noise capacitance-to-voltage converter (CVC) followed by a high linearity bandpass$\Delta\Sigma$ADC$(\text{BP}-\Delta\Sigma \mathrm{M})$without frequency demodulation. By avoiding demodulation and utilizing a narrow-band sensing technique, the proposed CDC achieves a sub-aF capacitance resolution while expanding the input capacitance range through a coarse C-DAC calibration loop. The proposed circuit has been implemented in a$0.35-\mu \mathrm{m}$CMOS process with a 3.3 V power supply voltage. The CDC shows a capacitance resolution of 0.98$\text{aF}_{\text{rms}}$, with a capacitance range of 3.1 pF, while consuming 4.16 mW.

A batteryless electrochemical sensing system IC for miniaturized wearable sensor nodes is presented. A battery-powered hub node transmits the power and control signal required for the operation of sensor nodes through a human body. The sensor data acquired by sensor nodes are transmitted to the hub node, again through a body channel, using frequency modulation (FM). The intra-body power and data transfer leads to batteryless sensor node operation, and the direct-FM-based sensor interface using a current-controlled oscillator (26.8 and 44.9 kHz/$\mu\mathrm{A}$) simplifies sensor node hardware, which enables miniaturized wearable sensor nodes. By adding a proper multiplexing scheme among sensor nodes, the proposed system can be extended to a further advanced system consisting of distributed wearable sensor nodes.

This paper presents the inverter-based pseudo-differential reconfigurable pixel array. For monitoring multi-modal neural activity, the pixel array can change its recording configuration between voltage-and current-recording modes. During the voltage-recording mode, the pixel is configured in the capacitively-coupled instrumentation amplifier (CCIA), which is designed to occupy minimal chip area. During the current-recording mode, the complementary diode-connected load (CDCL) is used in conjunction with the CCIA to filter the input offset current and amplify the current signal. To conduct high-density neural recording, we employ the inverter-based structure for the CCIA and use its parasitic capacitance between the gate and drain terminals as the feedback capacitor, thus reducing the input capacitor of the CCIA. Thanks to the use of CDCL, the current recording is conducted without a significant increase in the design area. The proposed array, implemented in a 180-nm CMOS process, achieves the input noise of $5.86~\mu \mathrm{V}_{\mathrm{rms}}$ and 18.17 pA$_{\mathbf{rms}}$ for voltage-and current-recording modes over 10-kHz bandwidth, respectively.

Recently, there is increasing demand for energy-efficient signal processing in wearable visual-stimuli-based brain-computer interface (V-BCI) devices. For the better accuracy and the reduced latency of the V-BCI system, the target identification (TI) algorithm that analyzes brain signals is being advanced, and the importance of an energy-efficient accelerating chip that processes various linear algebra operations constituting the TI algorithms is growing. In this paper, we propose a domain-specific reconfigurable array processor (RAP) with a dynamically reconfigurable and scalable array including 5-heterogeneous processing elements (PEs) for the energy-efficient acceleration of basic linear algebra subprograms (BLAS) and matrix decompositions. The system-on-chip (SoC), including the proposed RAP, was fabricated in 130-nm CMOS technology with an area of 16.87-mm2 and measured at 1.0 V 90 MHz. The RAP achieved an information transfer rate (ITR) of 139.9-bits/min and a TI accuracy of 95.4% on a fabricated chip through an optimized TI algorithm and scalable array processing. In addition, the RAP has$16.8\times $higher TI energy efficiency than prior work and achieved an energy efficiency of 2144.2-bits/min/mW for information transfer processing rate with the proposed TI algorithm. The RAP supports a greater variety of linear algebra operations and data sizes with hardware reconfiguration than the prior accelerators.

This paper presents a 46 nF/10$\text{M}\Omega $-range, digital-intensive, reconfigurable RC-to-digital converter (R2CDC) that can readout multiple C and R sensors in a time-interleaved fashion. Ratio-metric conversion using swing-boosted period-modulation (SB-PM) front-end by the R2CDC results in 114 aFrms/$0.37 \Omega _{\text {rms}}$resolutions and a worst-case temperature-drift of 64.2 ppm/°C over −40 to 125°C. Femto-farad capacitances can be sensed with a relative code-deviation less than 0.16 % even when parasitics vary 30 times the baseline. Implemented in a$0.18 ~\mu \text{m}$standard CMOS process, the R2CDC consumes 140$\mu \text{A}$from a 1 V supply, occupying an active area of$0.175 ~\mu \text{m} ^{\mathrm{ 2}}$.

This paper presents an impedance-measurement integrated circuit (IC) that extends the input frequency range to 10 MHz at low power consumption. The proposed IC directly measures the magnitude and phase of the target impedance while adopting a reference resistor, which is connected in series with the target impedance, to obviate the nonideal delays that may be introduced by the voltage-controlled current source and the receiver's signal processing paths. On the receiver side of the IC, a frequency shift is performed by a chopper in front of the first-stage instrumentation amplifier (IA). The chopper down- converts the frequency of the incoming signal, which ranges to 10 MHz, to a common intermediate frequency of 10 kHz. As a result, the requirements on the IA bandwidth and the comparator delay are greatly relaxed, leading to a significant power saving. Furthermore, this technique improves the phase accuracy because the time interval corresponding to the phase at a high frequency increases at the down-converted frequency. Finally, the auto-zeroing technique is used to cancel out the comparator offset, thus reducing the magnitude and phase errors. The proposed IC designed in a 180-nm CMOS process consumes only 544 μW for a frequency range from 100 Hz to 10 MHz with the maximum magnitude and phase errors of 1.0% and 1.8°, respectively.

Recently, indoor air quality is an important issue for human health and high concentrations of toxic Volatile Organic Compounds (VOCs) gases such as BTEX (Benzene, Toluene, Ethylbenzene, and Xylene) are very harmful to our respiratory system and metabolism. To detect BTEX gases at indoors, Metal Oxide (MOx) sensors are widely used because of their low-cost and high sensitivity. MOx sensors are easily affected by temperature and humidity, hence it is difficult to detect BTEX gases accurately without additional calibration process. In this paper, we present the calibration system for heterogeneous MOx sensor array where machine learning (ML)-based techniques, Linear Regression (LR), Non-Linear Curve Fitting (NLCF), and Artificial Neural Network (ANN), are exploited to reduce the impact of temperature and humidity. For the performance evaluation, we have setup the gas concentration measurement system and recorded the sensor outputs from Temperature-Cycled Operation (TCO) responses of five heterogenous MOx sensors. The proposed calibration system with ANN-based calibration system shows the reduction of gas sensors variation due to temperature and humidity 73% on average, and presents maximum 92% reduction for benzene, 75% for toluene, 83% for ethylbenzene, and 91% for xylene gases, respectively.

This paper presents a multimodal neural recording system incorporating reconfigurable neural recording front-ends to improve hardware availability. The proposed neural recording front-end utilizing the reconfigurable signal conveyor based on the folded-current- mirror structure is configured to process either voltage or current input signal, depending on the targeted experiment scenario, given experiment setup, and varying status of the recording environment. Thus, out of the total number of recording channels, how many channels are used for voltage and current recording can be set as desired, which maximizes the flexibility of the experiment and the usefulness of the recording system. The implemented system is successfully applied to the in vivo recording experiment conducted in the hippocampus area of a mouse brain. The neural recording front-end achieves input-referred noise performances of 2.4 μVrmsand 5.19 pArmsin the voltage and current recording modes, respectively. The power consumed by each recording channel is 5.718 μW, and only 54 nW is used to operate the reconfigurable signal conveyor.

We present a 67-pJ/bit 435-MHz modulator for 16 quadrature amplitude modulation with a fast and low- energy start-up for ultra-low-power wireless medical capsule endoscopy application. For a fast start-up, an auto-calibrated transient DC error correction is proposed to minimize the envelope error at the modulator output node occurring right after the initiation of the start-up process. Once the DC error correction is optimized through the calibration procedure, start-up energy of 50 pJ and start-up time of 18 ns are achieved, which enable symbol-level duty cycling. Implemented in a 180-nm CMOS process, the modulator performs 40-Mbps data transmission with -5-dBm output power while consuming 2.66 mW from a 1-V supply.

This paper presents a miniature electromagnetic (EM) sensor node for wireless surgical navigation systems. The sensor node measures the intensity of the EM field originated from the EM field generator placed at the predefined position and determines the position and orientation of the object where the sensor node is attached. The wireless electromagnetic sensor node performs analog and digital signal processing as well as wireless communication. The EM field signal from the generator is detected by the LC resonator circuit, and then amplified and filtered in the analog signal processing subsystem. This analog signal is converted to the digital data, and discrete-Fourier-transform analysis is performed in the digital signal processing subsystem. The analysis results are then transferred to the base station by using wireless communication. The developed sensor node is 8.84 cm3in volume while exhibiting the accuracy of 99.58% and 99.92% for position and orientation sensing, respectively.

In this paper, the feasibility of the intra-body power transfer is verified and an area-efficient rectifier with threshold voltage cancellation for intra-body power transfer is proposed. Through the measurement, the optimum power transmission frequency is determined as 1 MHz. Since the transmission voltage gain is sufficiently high (about 0.3) and nearly constant over a wide range of the load resistance, the intra-body power transfer works well even with the nonlinear and varying input impedance of the rectifier that is placed right after the receiving electrode. The proposed area-efficient rectifier cancels the threshold voltage by using a diode-connected device with a dynamically biased current source. It achieves a considerably smaller area of 65 μm × 30 μm than the area consumed by other designs reported previously. The overall power conversion efficiency (PCE) and voltage conversion ratio (VCR) are also improved. It achieves 84.4% of PCE and 85.6% of VCR with 1-V input voltage and 40-kΩ load.

This paper presents an ultra-low-noise differential relaxation oscillator implemented in a 0.18-pm standard CMOS process. The proposed oscillator having output frequency of 10.5 MHz achieves 162.1 dBc/Hz FOM at 100 kHz offset and 157.7 dBc/Hz FOM at 1kHz offset by employing a swing-boosting scheme. It also achieves 9.86 psrms period jitter corresponding to 0.01% relative jitter which is five times lower than that of the previous state-of-the-art work.

This paper presents a galvanic coupling communication (GCC) receiver for bionic arms. The detachability of the bionic arms results in various changes such as contact impedance variation and electrode misalignment. Its dynamic usage conditions may lead to contact with metallic objects. Moreover, the GCC has an inherent drawback of narrow channel bandwidth, which limits the communication speed. In this work, we demonstrate that the GCC can offer robust operation under varying channel conditions by using HFSS simulations. In addition, by applying a cascaded continuous-time linear equalizer, the proposed receiver widens the bandwidth from 1 MHz to 60 MHz. Implemented in 0.18-um CMOS process, a 30-Mbps GCC receiver operates successfully for bionic arms with robustness against channel condition variations while following body safety guidelines and consuming 650 uW.

We propose a sinusoidal signal generator (SSG) using a constant gain finite impulse response (FIR) filter for measuring impedance spectrum from 1-kHz to 2.048-MHz range. A simple digital-to-analog converter (DAC) using eight unit resistors generates differential stepwise signals and the FIR filter attenuates close-in harmonics of the stepwise signals using its inherent nulls. A continuous-time (CT) low-pass filter (LPF) attenuates high-order harmonics of the FIR filter's output. The fabricated SSG achieved the total harmonic distortion less than 0.2% up to 10th harmonic using a simple DAC and low oversampling ratio of 8. Since our SSG adopts a passive type of CT LPF and a constant gain FIR filter which does not require any gain compensation circuit, the fabricated SSG consumed 5.1 mW which is about 30% of our previous SSG.

This paper presents a current-mode neural/muscular stimulator with an exponentially decaying stimulation current. The use of exponentially decaying current makes the voltage on the stimulating electrode constant during the stimulation, which eliminates the headroom and increases the power efficiency. A simple exponentially decaying current generator is proposed based on Taylor series approximation and implemented in a 16-channel prototype stimulator IC. The prototype IC is fabricated in a 0.18-μm CMOS process with high-voltage LDMOS option, occupying a core area of 1.65 mm × 1.65 mm. The stimulator is tested with different loads, which mimics the electrode impedances, and the measured results show that maximum stimulation power efficiency of 95.9% can be achieved at the output stage of the stimulator. Depending on the electrode impedance and stimulation current, the power efficiency can be improved by nearly 10% at the output stage, compared to traditional constant-current stimulator.

In this design contest, the design methodology leading to a high performance Millimeter-wave amplifier in 0.13 μm SiGe BiCMOS is elaborated. Equivalent circuit models of the utilized cascode shielding structure are developed to assist the amplifier design. Meanwhile, final layouts of the passive connections are verified by 3D electromagnetic simulation in ANSYS HFSS. The implemented amplifier obtained a gain more than 45 dB in band, which is the gain record of silicon-based amplifiers in W-band.

Hysteretic control is widely adopted in the power management units (PMUs) for modern electronic devices due to their simple and stable control architecture, as well as the fast load transient response. However, the switching frequency of a traditional hysteretic converter is not fixed. It changes with operating condition and component aging, and hence brings in electro-magnetic interference (EMI) problems and multiphase interleaving difficulties. In this work, a hysteretic buck converter with frequency-locking capability is presented, where the switching frequency is adjusted by tuning the hysteretic window. In addition, the current-mode hysteretic control in this work utilizes a simple feedback network, which consists of only passive components and yet provides significant improvement on output voltage regulation. To achieve good reliability at high temperature and high voltage, the proposed buck converter has been fabricated in a 1μm SOI process with a chip area of 6mm2. Experimental results measured at 1MHz fixed switching frequency with 12V-to-5V voltage conversion and 0.9A load current shows a peak efficiency of 91%.

The digital TCXO (DTCXO) has been studied extensively because of its high frequency accuracy and rapid start-up time. The value of compensation capacitance used in the DTCXO is stored in ROM or calculated by computing circuit. In this work, ROM and computing circuit are integrated together to obtain the merit of both schemes; accurate value and high resolution of compensation capacitance, respectively. The DTCXO contains a temperature sensor, A/D converter, controller, EEPROM, capacitor bank, and oscillator. The oscillation frequency can be pulled from /spl plusmn/25 ppm to the required frequency with sub-ppm accuracy. The maximum power consumption of the total chip is 6.6 mW at 3.3 V. The chip, die size of 9mm/sup 2/, is fabricated by a 0.5 /spl mu/m CMOS technology.

We propose a new high speed and low power SOI inverter that can operate with efficient body-bias control and free supply voltage. The performance of the proposed circuit is evaluated by both the BSIM3SOI circuit simulator and the ATLAS device simulator, and then compared with other reported SOI circuits. The proposed circuit is shown to have excellent characteristics. At the supply voltage of 1.5V, the proposed circuit operates 27% faster than the conventional SOI circuit with the same power dissipation.