Design margining is used to account for design uncertainties in the measurement of performance, and thereby ensures that actual manufactured parts will operate in within predicted bounds. As process and environmental variations become increasingly severe and complex in nanometer process technology, design margining overheads have increased correspondingly. This paper describes the types of process and environmental variations, their impact on performance, and the traditional design margining process used to account for these uncertainties. We consider statistical timing (SSTA) in the context of its ability to reduce timing margins through more accurate modeling of variations, and quantify potential benefits of SSTA for setup and hold time margin reduction. Combining SSTA with complementary techniques for systematic variation-aware and voltage-variation-aware timing provides meaningful design margin reduction. We introduce the concept of activity based operating condition as a supporting construct for variation-aware STA flows

Clock skew is becoming increasingly difficult to control due to variations. Link based non-tree clock distribution is a cost-effective technique for reducing clock skew variations. However, previous works based on this technique were limited to unbuffered clock networks and neglected spatial correlations in the experimental validation. In this work, we overcome these shortcomings and make the link based non-tree approach feasible for realistic designs. The short circuit risk and multi-driver delay issues in buffered non-tree clock networks are investigated. Our approach is validated with SPICE based Monte Carlo simulations, considering spatial correlations among variations. The experimental results show that our approach can reduce the maximal skew by 47%, improve the skew yield from 15% to 73% on average with a decrease on the total wire and buffer capacitance.

We present a flow for effective high performance datapath design, and describe the results of this flow on a high-performance chip. This structured custom design flow combines custom logic design techniques with a timing-driven cell-based layout flow that is tuned specifically for datapath.