Process variations and atomic-level fluctuations increasingly pose challenges to the design and analysis of integrated circuits by introducing variability. Although several approaches have been proposed to deal with the inherent statistical nature of circuit design, we consider them incomplete with two important aspects often being insufficiently addressed: 1) non-Gaussian distributions and 2) highly correlated parameters. To address these points, we propose a fully multivariate and non-Gaussian approach based on an arbitrary model. A subset of the model parameters is treated as a multidimensional random variable, which is represented by a combination of generalized lambda distributions and Spearman rank correlation matrices-a very general approach with nearly arbitrary freedom in distribution shapes and parameter correlations. In our application scenarios, we show that such a model is able to fully and accurately capture variability in device compact models and standard cell performance models. Finally, we present adapted analysis methods making use of these models in circuit simulations and in efficient gate level analyses of digital circuits with high accuracy.

Analog behavioral models are widely used to reduce the complexity in hierarchical analog circuit design and verification. In the presence of process variations and atomic-level fluctuations, however, these models have to be extended to take variability into account. In this paper, we present a probabilistic solution that treats the behavioral model coefficients as multidimensional random variables and supports non-Gaussian as well as correlated parameters. A voltage divider and a bandgap voltage reference demonstrate the capabilities of our modeling approach in terms of accuracy and efficiency.

Variability continues to pose challenges to integrated circuit design. With statistical static timing analysis and high-yield estimation methods, solutions to particular problems exist, but they do not allow a common view on performance variability including potentially correlated and non-Gaussian parameter distributions. In this paper, we present a probabilistic approach for variability modeling as an alternative: model parameters are treated as multi-dimensional random variables. Such a fully mul-tivariate statistical description formally accounts for correlations and non-Gaussian random components. Statistical characterization and model application are introduced for standard cells and gate-level digital circuits. Example analyses of circuitry in a 28 nm industrial technology illustrate the capabilities of our modeling approach.

It is well known that random fluctuations in integrated circuit manufacturing introduce variations in circuit performance. While a lot of effort has been spent on circuit variability, fitting performance parameter distributions has not been extensively examined. Our work analyzes whether the Generalized Lambda Distribution suits approximating circuit performance characteristics. We focus on statistical standard cell characterization as an important step towards statistical gate-level and system-level analyses. Our results show that the Generalized Lambda Distribution is not applicable to raw leakage power data. However, timing data and dynamic power consumption may be approximated well. The high characterization effort has to be overcome to achieve industrial application.

Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects on power and delay times at chip level is Monte Carlo Simulation, which can be very accurate but time consuming if applied to transistor-level models. We present an alternative approach, namely a statistical gate-level simulation flow, based on parameter sensitivities and a generated VHDL cell model. This solution provides a good speed/accuracy tradeoff by using the event-driven digital simulation domain together with an extended consideration of signal slope times directly in the cell model. The designer gets a fast and accurate overview about the statistical behavior of power consumption and timing of the circuit depending on the manufacturing variations. The paper shortly illustrates the general flow from cell characterization to the model structure and presents first simulation results.

Statistical analysis is generally seen as the next EDA technology for timing and power sign-off. Research into this field has seen significant activity started about five years ago. Recently, interest appears to have fallen off somewhat. Also, while a lot of focus has been put on research fundamentals, extremely few applications in industry have been reported so far. Therefore, a group including Infineon Technologies as a leading semiconductor IDM and various universities and research institutes, as well as an EDA provider has tackled key challenges to enable statistical design in industry in a publicly funded project called ldquoSigma65rdquo. Sigma65 strives to provide key foundations to allow a change from traditional deterministic design methods to future design methods driven by statistical considerations. The project starts with statistical modeling and optimization of library components and ranges to statistical techniques for designing ICs on gate level and higher levels. In this paper, we present some results of this project, demonstrating how the interaction between industrial perspective, research institutions and EDA provider enables solutions which are applicable already in the near future. After an overview of the industrial perspective of the current situation in dealing with variations recent results on both statistical timing and power analysis will be given. In addition, recent research advances on fast yield estimation concerning parametric timing yield will be given.

This paper proposes a first attempt at describing statistical variation in system level models using SystemC-AMS. A statistical package of C++ functions for the use in SystemC-AMS is introduced. The method is based on the standard SAE J 2748.

Since the standardization in 1999 the hardware description language VHDL-AMS is widely used for the modeling of digital, analog, and mixed-signal systems. On the one hand, the powerful language constructs allow a very flexible creation of user-defined models. On the other hand, it is possible to define simulation problems with correct syntax but without a solution. From a mathematical point of view some reasons of such problems are discussed and rules are established that may help to avoid these difficulties.