Mixed analog and digital mode simulators have been available for accurate /spl alpha/-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. In this paper, we describe a gate-level transient fault simulation environment which has been developed based on realistic fault models. Although the environment was developed for /spl alpha/-particle-induced transient faults, the methodology can be used for any transient fault which can be modeled as a transient pulse of some width. The simulation environment uses a gate level timing fault simulator as well as a zero-delay parallel fault simulator. The timing fault simulator uses logic level models of the actual transient fault phenomenon and latch operation to accurately propagate the fault effects to the latch outputs, after which point the zero-delay parallel fault simulator is used to speed up the simulation without any loss in accuracy. The environment is demonstrated on a set of ISCAS-89 sequential benchmark circuits.

Previous work on radiation hardening has focused on designing memory elements to tolerate direct hits by high energy particles. The study of latch designs to tolerate high energy particle induced transient pulses arising in the combinational part of the circuit and traveling to the inputs of DFFs has been, ignored. In this work, we look at ways to slow down the input stage of latches by inserting resistances to tolerate transient pulses. Fault injection experiments indicates that most of the transient pulses can be tolerated with 7.5 ns penalty in performance, at least for the ISCAS-89 benchmark circuits. In circuits for critical systems, this penalty may be acceptable. Furthermore, this is not the best case penalty since the DFF can be individually optimized for the circuit and the transient pulse width can be somewhat shortened through redesign. Therefore, this is a viable approach for tolerating transient pulses in VLSI circuits used in critical systems.>

Systems designed for reliability must be validated through simulations. However, traditional SPICE like simulators or even mixed-mode simulators are too slow for the task of simulating the effects of /spl alpha/-particle hits on relatively large circuits. Gate-level simulators offer tremendous speedup over these electrical level simulators, but they are only as good as the model which captures the /spl alpha/-particle effect at the logic level. The goal of this research is to develop a computationally efficient model which captures the behavior of the /spl alpha/-particle at the logic level. This model can then be used in a gate-level timing simulator to propagate the /spl alpha/-particle effects to the latches and the outputs of the circuit under simulation. We have developed a closed form solution to approximate the logic pulse waveform resulting from /spl alpha/-particle hits. As is presented in the paper, the model tracks the data from SPICE simulations remarkably well.>