We consider the problem of high-dimensional channel estimation in fast time-varying millimeter-wave MIMO systems with a hybrid architecture. By exploiting the low-rank and sparsity properties of the channel matrix, we propose a two-phase compressed sensing framework consisting of observation matrix completion and channel matrix sparse recovery, respectively. First, we formulate the observation matrix completion problem as a low-rank matrix completion (LRMC) problem and develop a robust rank-one matrix completion (R1MC) algorithm that enables the matrix and its rank to iteratively update. This approach achieves high-precision completion of the observation matrix and explicit rank estimation without prior knowledge. Second, we devise a rank-aware batch orthogonal matching pursuit (OMP) method for achieving low-latency sparse channel recovery. To handle abrupt rank changes caused by user mobility, we establish a discrete-time autoregressive (AR) model that leverages the temporal rank correlation between continuous-time instances to obtain a complete observation matrix capable of perceiving rank changes for more accurate channel estimates. Simulation results confirm the effectiveness of the proposed channel estimation frame and demonstrate that our algorithms achieve state-of-the-art performance in low-rank matrix recovery with theoretical guarantees.

Currently, untrusted third-party entities are increasingly involved in various stages of IC design and manufacturing, posing a significant threat to the reliability and security of SoCs due to the presence of hardware Trojans (HTs). In this paper, gate-level HT detection methods based on graph neural networks (GNNs) are established to overcome the defects of existing machine learning, which makes it difficult to characterize circuit connection relationships. We introduce harmonic centrality in the feature engineering of gate-level HT detection, which reflects the positional information of nodes and their adjacent nodes in the graph, thereby enhancing the quality of feature engineering. We use the golden section weight optimization algorithm to configure penalty weights to alleviate the problem of extreme data imbalance. In the SAED database, GraphSAGE-LSTM model obtained a TPR of 88.06% and an average F1 score of 90.95%. In the combined HT netlist of LEDA datasets, GraphSAGE-POOL model obtains a TPR of 88.50% and the best F1 score of 92.17%. In sequential HT netlist, GraphSAGE-LSTM model performs optimally, with a TPR of 98.25% and an average F1 score of 98.59%. Compared to existing detection models, the F1 score is enhanced by 8.86% and 2.48% on combined and sequential HT datasets, respectively.

The existing hardware Trojan (HT) detection technology usually relies on the golden reference model. With the continuous improvement of circuit integration, the detection accuracy of traditional methods such as side-channel analysis has declined. Methods based on testability and switch probability analysis have shown high detection accuracy. However, these techniques have a limited detection scope and are generally ineffective at identifying HT where the Sandia controllability/observability analysis program (SCOAP) values or switch probabilities are similar to those of normal signals. Against this backdrop, this article proposes a detection method based on graph neural networks (GNNs), which can achieve HT detection at the register transfer level (RTL) without the golden reference model. First, the RTL code is transformed into a data flow graph (DFG), and node feature extraction and node label marking are carried out during the transformation process. To mitigate the impact of insufficient initial features on the GNN model performance, the node feature vector used in this article comprises 37-D node types and 6-D structural features such as the minimum distance from the primary input (PI) and primary output (PO), in-degree, and out-degree. Subsequently, several GNN models are built for node classification tasks. The best model achieves an average of 99.1% recall and 96.7% F1-score on the open-source dataset on the Trust-Hub platform. Compared to the state-of-the-art detection results at RTL, the F1-score in this article has increased by an average of 3.8%.

Presents corrections to the paper, (Corrections to “GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features”).

Abstract Human action recognition based on graph convolutional networks (GCNs) is one of the hotspots in computer vision. However, previous methods generally rely on handcrafted graph, which limits the effectiveness of the model in characterising the connections between indirectly connected joints. The limitation leads to weakened connections when joints are separated by long distances. To address the above issue, the authors propose a skeleton simplification method which aims to reduce the number of joints and the distance between joints by merging adjacent joints into simplified joints. Group convolutional block is devised to extract the internal features of the simplified joints. Additionally, the authors enhance the method by introducing multi‐scale modelling, which maps inputs into sequences across various levels of simplification. Combining with spatial temporal graph convolution, a multi‐scale skeleton simplification GCN for skeleton‐based action recognition (M3S‐GCN) is proposed for fusing multi‐scale skeleton sequences and modelling the connections between joints. Finally, M3S‐GCN is evaluated on five benchmarks of NTU RGB+D 60 (C‐Sub, C‐View), NTU RGB+D 120 (X‐Sub, X‐Set) and NW‐UCLA datasets. Experimental results show that the authors’ M3S‐GCN achieves state‐of‐the‐art performance with the accuracies of 93.0%, 97.0% and 91.2% on C‐Sub, C‐View and X‐Set benchmarks, which validates the effectiveness of the method.

Branch prediction structures are increasingly used in space processors due to their crucial role in improving processor performance. Due to radiation effects such as Single Event Upset (SEU) causing system failures, it is necessary to provide protection techniques for branch prediction modules against complex spatial environments. In this paper, we proposed a simple, efficient, low-power, and fault-tolerant design scheme for L0 BTB consisting of a master-slave and a check-decision module. The strategy sets up the L0 BTB structure as a master-slave structure and adds an error check to detect single-bit errors. Experimental results show that we achieve 100% fault tolerance without a loss hit rate. The increase in resource usage is 1.1x, and the path delay increases by 8.1%, superior to other methods. The L0 BTB is a fully-associative structure and multiple entries are accessed simultaneously, which introduces significant power consumption. We added a low-power design for the master-slave module to reduce the query power consumption by 65.9%. In addition, we also applied the scheme to the RAS module. The experimental results demonstrate that our approach is an efficient, generic, fault-tolerant design scheme that can be deployed to different register files.

High-throughput single-cell RNA sequencing (scRNA-seq) data processing pipelines integrate multiple modules to transform raw scRNA-seq data to gene expression matrices, including barcode processing, sequence quality control, genome alignment and transcript quantification. With the rapid growth in data volume, the speed of scRNA-seq data processing pipeline has become a major bottleneck to large-scale scRNA-seq studies. We present scSparkXMBD1(denoted as scSpark), a cloud computing based scRNA-seq data processing pipeline. By leveraging the in-memory computing capability of Apache Spark, scSpark significantly improves the processing speed of scRNA-seq data, and achieves around 5-20 times faster than the state-of-the-art processing pipelines under the same CPU core consumption. In addition, thanks to the inherent scalability of Spark in a cloud computing environment, scSpark can further reduce the processing time for a typical scRNA-seq dataset (e.g., 640 million reads) from hours to minutes when multiple computer nodes (e.g., 16) are used. Biological evaluation also confirmed that the results generated by scSpark are highly consistent with existing scRNA-seq data processing pipelines.1XMBD refers to Xiamen Big Data, which is a biomedical open software initiative in the National Institute for Data Science in Health and Medicine, Xiamen University, China

The mitigation of single-event upset (SEU) in SRAM-based field-programmable gate array (FPGA) is increasingly important as utilization and demand for SRAM-based FPGA dramatically increased in radiation environments such as space. As D flip-flop (DFF) and memory [including block random-access memory (BRAM) and configuration random-access memory (CRAM)] are constituted as the key elements in an FPGA, it is fundamentally necessary to develop radiation hardening techniques targeted for enhanced reliability of DFF and memory. A novel SEU hardened memory design for FPGA is proposed with capabilities of multibit upset protection. We further developed two prototype FPGA chips, one with SEU and the other without SEU hardening for comparison. The FPGA chips are fabricated in a standard 0.13-$\mu \text{m}$CMOS process and have a volume of three million equivalent logic gates. In terms of SEU cross section, CRAM in the hardened FPGA design is about four orders of magnitude lower than in the unhardened FPGA design, while BRAM demonstrates a reduction by three orders of magnitude. On the conditions of linear energy transfer being up to 14 MeV$\cdot$cm2/mg, no SEU errors were observed from DFF in the hardened FPGA design.

As the feature size shrinks to the nanometer scale, SRAM-based FPGAs are increasingly vulnerable to soft errors. Checkpointing is an effective fault recovery technique that can restore the faulty system to its previous fault free state. Since the function of the system needs to be suspended during checkpoint saving and checkpoint restoring, so the Mean Time to Repair (MTTR) of the system is critical to the system performance. In this work, we propose a hierarchical hardware checkpointing (HHC) technique that contains a high-speed on-chip checkpoint and a low-speed off-chip checkpoint to accelerate fault recovery for SRAM-based FPGAs. Most of single event effect (SEE) faults can be recovered by the high-speed on-chip checkpoint, which significantly reduces the MTTR of the system. The memory resource occupation of the on-chip checkpoint is low because HHC only stores the logic states of user bits and check information for configuration bits. Experimental results show that, compared with traditional off-chip checkpoint strategies, the proposed technique can reduce the MTTR of the system by 94.30%. In addition, the memory resource occupation is 11.11% of FPGAs, a little high but can be further optimized.

As the feature size and threshold voltage reduce, leakage power dissipation becomes an important concern in SRAM-based FPGAs. This work focuses on reducing the leakage power in routing resources, and more specifically, the leakage power dissipated in the used part of FPGA device, which is known as the active leakage power. We observe that the leakage power in off-path transistors takes up most of the active leakage power in multiplexers that control routing, and strongly depends on Hamming distance between the state of the on-path input and the states of the off-path inputs. Hence, an off-path leakage power aware routing algorithm is proposed to minimize Hamming distance between the state of on-path input and the states of off-path inputs for each multiplexer. Experimental results on MCNC benchmark circuits show that, compared with the baseline VPR technique, the proposed off-path leakage aware routing algorithm can reduce active leakage power in routing resources by 16.79%, and the increment of critical-path delay is only 1.06%.

As the feature size of FPGA shrinks to nanometers, SRAM-based FPGAs are more vulnerable to soft errors. During logic synthesis, reliability of the design can be improved by introducing logic masking effect. In this work, we observe that there are a lot of not-fully occupied look-up tables (LUTs) after logic synthesis. Hence, we propose a functional equivalent class based soft error mitigation scheme to exploit free LUT entries in the circuit. The proposed technique replaces not fully-occupied LUTs with corresponding functional equivalent classes, which can improve the reliability while preserve the functionality of the design. Experimental results show that, compared with the baseline ABC mapper, the proposed technique can reduce the soft error rate by 21%, and the critical-path delay increase is only 4.25%.