EDBT 2026 Demo / reviewers in the wild / expert
Douglas A. Stuart
dblp:53/5596
· DBLP profile ↗
6ranked-venue papers
4as first author
0since 2021 · last 2001
0009-0002-5979-3976ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 4 · 2 first-authorSoftware engineering, systems software and programming languages · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Theoretical computer science
3 papers |
Automated reasoning and model checking · 97% Logic in computer science · 3% | |
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Embedded and real-time systems · 72% Distributed systems · 15% Electronic design automation · 13% |
Topics — the 9 heaviest of 10, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Automated reasoning and model checking › hardware verification
simulation-based verification |
0.0 | 1 | 2001 | Simulation-Verification: Biting at the State Explosion Problem · IEEE Trans. Software Eng. 2001 |
Automated reasoning and model checking › model checking
state space explosion |
0.0 | 1 | 2001 | Simulation-Verification: Biting at the State Explosion Problem · IEEE Trans. Software Eng. 2001 |
Embedded and real-time systems › real-time programming languages
modechart |
0.0 | 2 | 1995 | Compiling Modechart Specifications · RTSS 1995 Implementing a Verifier for Real-Time Systems · RTSS 1990 |
Distributed systems
formal specification |
0.0 | 1 | 1991 | Clairvoyance, Capricious Timing Faults, Causality, and Real-Time Specifications · RTSS 1991 |
Electronic design automation › hardware verification and test
formal verification |
0.0 | 1 | 1990 | Implementing a Verifier for Real-Time Systems · RTSS 1990 |
Automated reasoning and model checking
real-time verification |
0.0 | 1 | 1988 | A Method for Verifying Properties of Modechart Specifications · RTSS 1988 |
Embedded and real-time systems
synchronous programming |
0.0 | 1 | 1995 | Compiling Modechart Specifications · RTSS 1995 |
Logic in computer science
temporal logic |
0.0 | 1 | 1991 | Clairvoyance, Capricious Timing Faults, Causality, and Real-Time Specifications · RTSS 1991 |
Program verification › reactive system verification
real-time system verification |
0.0 | 1 | 1990 | Implementing a Verifier for Real-Time Systems · RTSS 1990 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.1verification · 0.1compilation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2001 | Simulation-Verification: Biting at the State Explosion ProblemabstractSimulation and verification are two conventional techniques for the analysis of specifications of real-time systems. While simulation is relatively inexpensive in terms of execution time, it only validates the behavior of a system for one particular computation path. On the other hand, verification provides guarantees over the entire set of computation paths of a system, but is, in general, very expensive due to the state-space explosion problem. We introduce a new technique: simulation-verification combines the best of both worlds by synthesizing an intermediate analysis method. This method uses simulation to limit the generation of a computation graph to that set of computations consistent with the simulation. This limited computation graph, called a simulation-verification graph, can be one or more orders of magnitude smaller than the full computation graph. A tool, XSVT, is described which implements simulation-verification graphs. Three paradigms for using the new technique are proposed. The paper illustrates the application of the proposed technique via an example of a robot controller for a manufacturing assembly line. Douglas A. Stuart, Monica Brockmeyer, Aloysius K. Mok, Farnam Jahanian |
IEEE Trans. Software Eng. | 1 |
| 1996 | A Methodology and Support Tools for Analysis of Real-Time SpecificationsabstractAs software control of time-critical functions in embedded systems becomes more common, a means for the precise specification of their behavior and formal methods for analyzing system requirements become increasingly important. Modechart is a graphical specification language introduced to meet this need. The main focus of this paper is on methods and supporting tools for representing and reasoning about properties of time-critical systems specified in Modechart. The paper describes a verification methodology which takes advantage of the structuring inherent in a Modechart specification to determine whether a system specification satisfies the required properties. The paper also describes the implementation of a mechanical verifier, based on the proposed approach, which has been recently integrated as part of the Modechart Toolset prototype development environment from the Naval Research Lab [7]. Douglas A. Stuart, Aloysius K. Mok, Farnam Jahanian |
Int. J. Softw. Eng. Knowl. Eng. | 1 |
| 1995 | Compiling Modechart SpecificationsabstractThe Modechart specification language is a formalism for the specification of real-time systems. A toolset for specification, analysis and simulation for Modechart specifications exists for supporting the design and construction of real-time systems. This paper introduces a new tool in the toolset: a compiler for a class of Modechart specifications, namely, that of deterministic system specifications, extended by a subclass of the non-deterministic system specifications. The object code that the compiler generates is in ESTEREL, a member of the synchronous family of programming languages for real-time systems. We discuss a broad approach to the implementation of timing specifications, providing a range of implementation options, from the basic time step unrolling of states in ESTEREL, to the use of system timers. The compiler presented herein allows the specifier to obtain a correct implementation of a Modechart program, including timing constraints. Carlos Puchol, Aloysius K. Mok, Douglas A. Stuart |
RTSS | 3 |
| 1991 | Clairvoyance, Capricious Timing Faults, Causality, and Real-Time SpecificationsabstractThe authors examine the issues of satisfiability, clairvoyance, the demonstrable existence of timing faults, and event causality, all in the context of formal methods for real-time systems. Representative languages and logics are introduced to illustrate the points. The authors introduce SRSL, a simplified specification language used to illustrate the issues involved. They examine these issues in a particular specification language, Modechart. An action-free subset of Modechart is shown to be satisfiable and to obviate the need for clairvoyance. A technique for eliminating nonlinearizable computations from a specification language is shown. The usefulness of the ideas is illustrated by their use in a Modechart simulator.> Douglas A. Stuart, Paul C. Clements |
RTSS | 1 |
| 1990 | Implementing a Verifier for Real-Time SystemsabstractThe SARTOR project has as one of its goals the development of an environment for the development of correct real-time systems. Modechart is a specification language for real-time systems developed as part of this project. Verify4 is an implementation of a verifier for certain classes of properties of systems specified using Modechart. The author describes the program Verify4 and addresses implementation issues surrounding three of the key algorithms used in the program.> Douglas A. Stuart |
RTSS | 1 |
| 1988 | A Method for Verifying Properties of Modechart Specifications
Farnam Jahanian, Douglas A. Stuart |
RTSS | 2 |