Summary Various functional units (FUs) have been designed in modern embedded processors to perform different functions when running an application. Traditionally, compilers did not take this characteristic into account to reduce the temperature of a processor during execution. For many applications, the occurrences of different instructions are not the same after they are compiled. As a consequence, the temperature of the processor is very high, arising from the major heating contribution of the special structure of the active functional unit, and thus, the system will suffer severe damage. Consequently, to remedy this hurdle, this paper provides a solution by shifting the loading from heavy‐loading FUs to light‐loading FUs. Our approach first identifies all the FUs that can exchange the loading among themselves and then presents a thermal model for these exchangeable FUs to estimate the temperature impact on shifting loading. Finally, the loading shifting has been performed by transforming code under the consideration of limited performance loss without hardware cost. The result shows that our approach can reduce the temperature to a small cost of performance degradation and code expansion. Copyright © 2014 John Wiley & Sons, Ltd.

SUMMARY The popularity of multimedia applications made them a major theme in embedded systems. The key component for supporting multimedia application well is embedded processor. Thus, we have designed and implemented an embedded processor, called UniDual processor, to achieve this objective. Its key features are the integration of instructions of reduced instruction set computers (RISCs) and digital signal processors (DSPs) as well as the support of special instruction set and shared‐based clustered register architecture. However, an important issue of UniDual that remains open is how to efficiently allocate registers. In this paper, we present a scheduling and instruction transformation approach to resolve the aforementioned issue. The proposed approach schedules instructions and then transforms overlapped instructions into RISC and DSP instructions by taking communication overhead and hardware limitations into account. Compared with the greedy approach, the evaluation shows that our work is relatively effective in performance and code size reduction. Copyright © 2012 John Wiley & Sons, Ltd.

As power density increases with high technology, the high temperature has threatened the system performance, reliability, and even system safety. Development of a thermal management method to reduce hotspot and to balance the temperature distribution has become an important issue. Therefore, dynamic thermal management (DTM) has emerged as an effective technique for guaranteeing thermal safety. It has been getting more popular for its low cost and flexibility. In this paper, we propose a proactive thermal management scheme on the Criti-core platform, in advance using thermal-aware thread scheduling to avoid high temperature. In addition, we using thread migration mechanism when core reach a critical threshold, to increase the reliability of the system.

In analog layout design, the accuracy of capacitance ratios correlates closely with both the matching properties among the ratioed capacitors and the induced parasitics due to interconnecting wires. However, most of the previous works only emphasized the matching properties of a common-centroid placement, but ignored the induced parasitics after it is routed. This paper addresses the parasitic issue in addition to device matching during common-centroid capacitor layout generation. To effectively minimize the routing-induced parasitics, a novel common-centroid placement style, distributed connected unit capacitors, is presented. Based on the placement style, the ratioed capacitor layout generation flow and algorithms are proposed to simultaneously optimize the matching properties of a common-centroid placement and minimize the induced parasitics. Experimental results show that the proposed approach can greatly reduce area, wirelength, and routing-induced parasitics, and guarantee the best matching quality after routing.

SUMMARY Simultaneous multithreading (SMT) processors can exploit thread‐level parallelism and at the same time exploit instruction‐level parallelism for multiple‐issue, dynamically scheduled processors. As they have been widely used in embedded systems, reducing their highest temperature has become very important. According to our observation, the register file is always one of the hottest parts of an embedded system. Thus, we present a smart scheduling that can cool an SMT processor effectively by controlling the temperatures of its register files without causing significant performance loss. The proposed approach is fourfold, thus allowing an operating system to dynamically adjust the running workloads based on the temperature threshold and the real‐time constraint. Our experiment was performed on the M‐Sim and HotSpot simulators to evaluate the power of functional units and the temperature impact for SMT processors. In contrast with the round‐robin scheduling, the proposed approach can reduce thermal emergency time by 16.1 and 9.38% of the integer register file and the floating point register file, respectively. Moreover, the proposed approach only degrades performance by 8.8%, which is better than the 22.1% of the throttling approach. Copyright © 2011 John Wiley & Sons, Ltd.

Various functional units (FUs) have been designed in modern embedded processors to perform different functions when running an application. For many applications the occurrences of different instructions are not the same after they are compiled. As a consequence, the temperature of the processor is very high arising from the major heating contribution of the special structure active functional unit and thus the system will suffer severe damage. Thus, to remedy this hurdle, this paper provides a solution by shifting the loading from heavy-loading FUs to light-loading FUs. Our approach first identifies all FUs that can exchange the loading among them and then presents a thermal model for these exchangeable FUs to estimate the temperature impact on shifting loading. Finally, the loading shifting has been performed by transforming code under the consideration of limited performance loss without hardware cost. The result shows that our approach can reduce the temperature at the small cost of performance degradation and code expansion.

With the rapid increase of multimedia technology [1], [2], the support of network traffic has become an important issue. Thus many protocols have been developed to address this issue in different network layers such as Real Time Streaming Protocol (RTSP) [3], Smooth Streaming [4] in application layer, and Real time Protocol (RTP) in transport layer. The common characteristic of these protocols is the requirement of data smoothing to support modern application like intelligent home and vehicular network. In addition, smart phone and wireless sensor network(WSN) [5] do not support all protocols, indeed, they may only support Transmission Control Protocol(TCP) or User Data gram Protocol(UDP). This implies that the network bandwidth will nor be good enough to play high quality multimedia streaming and support complicated network structure. In this paper, we present a smooth data streaming approach on application layer to reduce packet retransmission and improve performance. The proposed approach can provide smooth data streaming and reduce response time with the aid of data caching or data compression without increase the complexity of network protocol. In order to decrease the development complexity arising from UDP, instead, we implement the proposed approach based on TCP. We also analyze the impact of this work and discuss challenges in TCP in this paper. The result shows that the proposed approach can stabilize smooth data transmission and improve performance by 20% to 35% for benchmarks.

Virtualization has been widely adopted on servers for various purposes such as server consolidation, cloud computing, and so on. Recent years, the trend spreads on embedded systems, although it once seemed to be an impractical idea because of the limited capability of embedded processors. To further lower the overhead of adopting virtualization on embedded systems, we design an optimization technique, called inline emulation, to reduce the cost spending on paravirtualizing operating systems. Inline emulation can also be used in various virtualization environments to increase the performance of emulating privileged instructions. We implement inline emulation for ARMv5 architecture and evaluate in Android Emulator. The result shows it runs much faster, up to 7.4 times, than the common Para virtualization technique for cache-related operations and suggests that it not only lowers the development cost but also increases system responsiveness.

Conditional execution is an important ISA feature of the ARM series of processors. Every instruction can be made to execute conditionally, that is, it is treated as a NOP if the condition is not met. The advantage of conditional execution is that it can maintain high performance while reducing hardware complexity since it can avoid introducing pipeline bubbles even when no branch prediction units are needed. However, conditional execution takes up precious instruction space as conditions are encoded into a 4-bit condition code selector on every 32-bit ARM instruction. Besides, only small percentages of instructions are actually conditionalized in modern embedded applications, and conditional execution might not even lead to performance improvement on modern embedded processors. This paper proposes to trade conditional execution for more ISA registers on ARM processors, and the 4-bit condition field will be used to encode the extra registers. GCC has been ported to generate ARM code with the new instruction format and experimental results have shown that performance can be improved by 6% on average for Media Bench II benchmarks when the number of ISA registers is extended from 16 to 32.

This article proposes an alternative yet effective way of constructing a multiplatform binary translator, by converting a retargetable compiler into a binary translator. The rationale is that a retargetable compiler usually parses source programs into an Intermediate Representation (IR), and then translates IR into object code of different targets after performing analysis and optimizations. Specifically, the mechanism of code generation for multiple platforms from IR is already in place, and the missing link of building a multiplatform binary translator is a tool to transform binary programs back into IR. In order to fill in this missing link, this article presents a tool, called thedisIRer. Just as a translator from machine language to assembly language is called a disassembler, a tool that translates executable binary programs to IR is called here a disIRer. The unique feature of this approach is that the retargetability of the binary translator is inherited directly from the retargetable compiler. A prototype multiplatform binary translator has been implemented upon GCC (the GNU Compiler Collection). DisIRer first converts binary programs back into GCC IR (Intermediate Representation), and afterward the GCC backend translates the IR to target binary programs of specified platforms. Experimental results show that x86 binary programs can be translated by this technique into ARM and Alpha binaries with reasonable code density and quality.

In multicore environment, using multiple threads is a common useful approach to improve application performance. Nevertheless, even in many simple applications, the performance might degrade when the number of threads increases. Users usually impute this phenomenon to the overhead of creation or termination of threads. However, in our observation, the more significant effect is the dispatching of threads. We discuss the problems on using threads, and present a novel user dispatching mechanism (UDispatch) that provides controllability in user space to improve application performance. Since user threads cannot directly control system resources, a virtual device is adopted between user space and operating system for portability and efficiency instead of adding new system calls through kernel modification. We also experiment UDispatch through multithreading multimedia applications. The results show that a skipline application speeds up to 111.3% and 111.6% on a 4-core machine and an 8-core machine, respectively, and an optimized H.264/AVC decoder speeds up to 18.4% on a 4-core machine.

For the success of an SoC design, a design platform and some key design technologies are needed. For this purpose, a research project in "Technology Development Program for Academia" was granted recently in Taiwan to develop the following technologies toward a high-performance low-power SoC design platform. First, a soft intellectual property (soft IP) and related RTOS, compiler, and integrated design environment (IDE) software of an Advanced Taiwan VLTW DSP Processor Core, which can be used as the Star IP of an SoC design platform, will be developed. Second, low-power and low-voltage digital and mixed-signal circuit design technologies will be developed based on the advanced MTCMOS process. Third, some key multimedia and communication soft or hard IPs will be developed. The developed advanced key technologies can be used as the technology driver to facilitate the design of SoC-based products, and they will also help to enhance the design capability of the Taiwan SoC industry. In this paper, we introduce the research project and focus on architecture and software technologies developing in one of the subitems.

In this paper, we address the issues of partitioning sparse arrays whose non-zero elements are distributed non-uniformly. We consider inference schemes for Fortran 90 array intrinsics so that the non-zero structure of the output array can be deduced from the non-zero structures of the input arrays. Experiments are conducted to measure the effectiveness of our method with the Harwell-Boeing sparse matrix collection. We also demonstrate that, given the sparsity structures of the source arrays and with the help of our inference schemes, one can predict the performance differences among a collection of equivalent Fortran 90 code for sample on-line analytical processing (OLAP). The experiments are performed on an IBM SP2 cluster with the library support of our sparse array intrinsics.

In our recent work, we have been working on providing parallel sparse supports for array intrinsics of Fortran 90. Our supporting library uses a two-level design. In the low-level routines, it requires the input sparse matrices to be specified with compression/distribution schemes for array functions. In the high-level representations, sparse array functions are overloaded with Fortran 90 array intrinsic interfaces so that programmers need not be concerned about low-level details. This raises a very interesting optimization problem in the strategies to transform high-level representations to low-level routines by automatic selections and supplies of distribution and compression schemes for sparse arrays. We propose solutions to this optimization problem. The optimization problem is shown to be NP-hard. We develop a heuristic algorithm based on annotated program graphs, and the algorithm is shown to be practical. Experimental results on an IBM SP-2 show that the selection algorithms are effective in improving the performances of application programs that use sparse data sets.

Fortran 90 provides a rich set of array intrinsic functions. They form a rich source of parallelism and play an increasingly important role in automatic support of data parallel programming. However, there is no such support if these intrinsic functions are applied to sparse data sets. We address this open gap by presenting an efficient library for parallel sparse computations with Fortran 90 array intrinsic operations. Our method provides both compression schemes and distribution schemes on distributed memory environments applicable to higherdimensional sparse arrays. Sparse programs can be expressed concisely using array expressions, and parallelized with the help of our library. Preliminary experimental results on an IBM SP2 workstation cluster show that our approach is promising in supporting efficient sparse matrix computations on both sequential and distributed memory environments. 1 Introduction An increasing number of programming languages, such as APL, Fortran 90, High Perfor...

We present a generic matrix class facility in Java and an on-going project for a runtime environment with continuous compilation aiming to support automatic parallelization of sparse computation on distributed environments. Our package comes with a collection of matrix classes with a uniform interface for operations on dense and sparse matrices. These matrix operations are implemented both for sequential and parallel executions on distributed memory environments. In our environment, a program such as the conjugate gradient solver is written by users using high-level generic matrix notations in Java. At runtime the generic notations are mapped to specific implementations. Our approach is particularly useful for optimizing sparse computation for distributed environments because, with the help of profiling information and a cost model, it can automatically select suitable compression and distribution schemes according to access patterns of the programs and non-zero structures of the matrices. Our testbed is currently based on Java and PVM on an IBM SP2 workstation cluster. Preliminary experimental results show that our approach is promising in speeding up sparse matrix computations on distributed memory environments. © 1997 John Wiley & Sons, Ltd.