In this paper, we study two different ON-chip power delivery schemes, namely, fully integrated voltage regulator (FIVR) and low-dropout regulator (LDO), and analyze their effect on total system power under process variation, assuming a realistic dynamic voltage-frequency scaling (DVFS) system. The impact of different task scheduling algorithms on the overall system power was also analyzed. We find that in a hypothetical 256-core processor, under a per-core DVFS assumption, the FIVR-based power delivery consumes 20% less power than the LDO-based one for a 50% throughput. However, as the number of cores in the processor reduces, the difference in power consumption between the FIVR-based and LDO-based power delivery schemes becomes smaller. For example, in the case of a 16-core processor with per-core DVFS capability, FIVR-based design was found to consume about the same power as the LDO-based design.

There are situations in a computing system where incoming information needs to be compared with a piece of stored data to locate the matching entry, e.g., cache tag array lookup and translation look-aside buffer matching. If the stored data is protected with error-correcting codes (ECC) for reliability reason, the previous solution is to access the stored information, decode and correct if necessary before it is used to compare with the incoming data. The decoding and correcting step increases the total access time, which is often critical. In this paper, we propose a method to improve the compare latency for information encoded with ECC. We use the cache tag array look-up as an example, and results show that 30% gate count reduction and 12% latency reduction are achieved.

TSV-based 3D chip stacking and integration technology was proposed more than twelve years ago. Since then the concept has gained tremendous traction with significant advances in the technology and planned system prototypes. The IP portfolio in 3D process, circuits, architectures, test and assembly peaked in year 2006. Today, multiple foundries offer a TSV process for 3DICs. Many design teams in academia and industry have been working towards a convincing 3D prototype that will demonstrate form factor reduction, heterogeneous integration and higher performance. However, the commercial success of true 3DICs has been limited to DRAM stacking.This presentation will introduce technology scaling trends and new challenges. We are at an I/O inflection point due to Tera-scale computing needs. The tutorial will describe the implication to memory bandwidth and present various options. 3DICs provide an excellent alternative to address the memory bandwidth issue by providing a large near-processor memory. In this presentation we will discuss architecture, floorplanning, power routing, IO circuits, test and assembly of a large prototype processor-memory 3DIC designed for Tera-scale applications. The presentation will conclude with a discussion on test, power delivery and thermal management issues related to 3D integration.

Traditional processors are designed to guarantee error-free operation under worst-case (1) device & interconnect parameter variations resulting from less than ideal manufacturing process control; (2) static & erratic defects; (3) operating environments such as temperature excursions and voltage droops; (4) critical path activation and path delay degradations due to multiple inputs switching simultaneously in gates containing transistor stacks, or signal coupling from neighboring lines in interconnect paths; (5) speed degradation over the operating lifetime due to transistor aging under voltage, temperature & current stress; (6) early-life failures due to latent defect accelerations; and (7) soft error due to cosmic rays and alpha particle impacts. The voltage-frequency settings for all processors are set based on these infrequently encountered worst-case considerations, even though under typical conditions voltage can be pushed down further or frequency increased without causing errors for most of the processors, thus limiting both energy efficiency and performance in scaled CMOS technologies.

Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically refreshed to retain data. Like SRAM, eDRAM is susceptible to device variations, which play a role in determining refresh time for eDRAM cells. Refresh power potentially represents a large fraction of overall system power, particularly during low-power states when the CPU is idle. Future designs need to reduce cache power without incurring the high cost of flushing cache data when entering low-power states. In this paper, we show the significant impact of variations on refresh time and cache power consumption for large eDRAM caches. We propose Hi-ECC, a technique that incorporates multi-bit error-correcting codes to significantly reduce refresh rate. Multi-bit error-correcting codes usually have a complex decoder design and high storage cost. Hi-ECC avoids the decoder complexity by using strong ECC codes to identify and disable sections of the cache with multi-bit failures, while providing efficient single-bit error correction for the common case. Hi-ECC includes additional optimizations that allow us to amortize the storage cost of the code over large data words, providing the benefit of multi-bit correction at same storage cost as a single-bit error-correcting (SECDED) code (2 % overhead). Our proposal achieves a 93 % reduction in refresh power vs. a baseline eDRAM cache without error correcting capability, and a 66 % reduction in refresh power vs. a system using SECDED codes.

SRAM arrays using differential sensing (DS) and single-ended sensing (SE) are designed and fabricated in a test chip and their power and performance behaviors are studied in this paper. Sense amplifier offset (DC condition), which is one of the main criterion to determine the required bit-line differential, is measured. A novel SE scheme is proposed to overcome the delay degradation due to large bit line leakage in scaled technology. With marginal switching power savings, the SE array is 56% slower than the DS array in 90 nm technology with a single high-Vt at 350 mV. The difference narrows down to 30% in low-Vt case. Using asymmetric cells, instead of symmetric cells, in single-ended large signal arrays improves delay by 3%, while the power consumption remains approximately the same.

The state dependence of leakage can be exploited to obtain modest leakage savings in complementary metal-oxide-semiconductor (CMOS) circuits. However, one can modify circuits considering state dependence and achieve larger savings. We identify a low-leakage state and insert leakage-control transistors only where needed. Leakage levels are on the order of 35% to 90% lower than those obtained by state dependence alone. Using a modified standard-cell-design flow, area overhead for combinational logic was found to be on the order of 18%. The proposed technique minimizes performance impact, does not require multiple-threshold voltages, and supports a standard-cell-design flow.

In this paper, we present a noise-tolerant high-performance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and are more suitable for low voltage applications because of better noise margins. Skewed logic and its variations have been compared with Domino logic in terms of delay, power, and dynamic noise margin. A design methodology for skewed CMOS pipelined circuits has been developed. To demonstrate the applicability of the proposed logic style, 0.35 /spl mu/m 5.56 ns CMOS 16/spl times/16 bit multipliers have been designed using skewed logic circuits and fabricated through MOSIS. Measurement results show that the multiplier only consumed a power of 195 mW due to its low clock load.

A dynamic noise model is developed and applied to analyze the noise immunity of precharge-evaluate circuits. Considering that the primary source of noise-injection in the circuit is cross-talk, a simple metric represented as voltage-time product can be used to quantify the dynamic noise-margin. This is verified by HSPICE simulation on DOMINO gates. A tool is also developed to obtain static and dynamic noise-margins at various points in the circuit. Dynamic noise-margins are translated into maximum allowable coupling capacitances between the pairs of nets for precharge-evaluate logic circuits. An accurate estimate of dynamic noise-margin and coupling coefficient bounds will allow improvement of the circuits in terms of robustness.

In this paper, we present a noise-immune high-performance static circuit family called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and they are more suitable for low voltage applications because of better noise margins. Skewed logic and its variations have been compared with Domino logic in terms of delay, power and dynamic noise immunity. Comparison between skewed and Domino circuits on a 0.25µm 700 MHz 16 × 16 bits pipelined multiplier shows superior properties of skewed circuits over Domino in terms of clock power dissipation and peak current consumption.

Article Free Access Share on Leakage control with efficient use of transistor stacks in single threshold CMOS Authors: Mark C. Johnson Rose-Hulman Institute of Technology, 5500 Wabash Avenue, Terre Haute, IN Rose-Hulman Institute of Technology, 5500 Wabash Avenue, Terre Haute, INView Profile , Dinesh Somasekhar Purdue University, 1285 EE Building, West Lafayette, IN Purdue University, 1285 EE Building, West Lafayette, INView Profile , Kaushik Roy Purdue University, 1285 EE Building, West Lafayette, IN Purdue University, 1285 EE Building, West Lafayette, INView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 442–445https://doi.org/10.1145/309847.309976Published:01 June 1999Publication History 24citation620DownloadsMetricsTotal Citations24Total Downloads620Last 12 Months40Last 6 weeks3 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

This paper presents several new array multiplier architectures for reducing switching activity in general digital signal processing (DSP) applications. A cellular structure is described which can be used to obtain any array multiplier suitable for a given application. The switching activity at the output nodes of the cells in this structure is analyzed and compared with a tree multiplier based on 4:2 compressors. It is shown that the relative improvement in power is a function of statistical properties of the signal and most structures out-perform all others for specific signal conditions. It is also shown that selection of appropriate array architecture can give up to 49% reduction in switching activity compared to a tree multiplier, and more than 3 times less switching activity compared to the widely used least-significant-bit-first array multiplier for commonly occurring situations. We also outline applications of the proposed structures to the areas of low power quantization, reconfigurable computing and high-level synthesis for low power.

Subthreshold leakage current in deep submicron MOS transistors is becoming a significant contributor to power dissipation in CMOS circuits as threshold voltages and channel lengths are reduced. Consequently, estimation of leakage current and identification of minimum and maximum leakage conditions are becoming important, especially in low power applications. In this paper we outline methods for estimating leakage at the circuit level and then propose heuristic and exact algorithms to accomplish the same task for random combinational logic. In most cases the heuristic is found to obtain bounds on leakage that are close and often identical to bounds determined by a complete branch and bound search. Methods are also demonstrated to show how estimation accuracy can be traded off against execution time. The proposed algorithms have potential application in power management applications or quiescent current (I/sub D/DQ) testing if one wished to control leakage by application of appropriate input vectors. For a variety of benchmark circuits, leakage was found to vary by as much as a factor of six over the space of possible input vectors.

This paper describes a test method which relies on the actual observation of supply current (I/sub DD/) waveforms. The method can be used to supplement the standard I/sub DDQ/ test method and it can be easily applied to dynamic and low V/sub DD/, low V/sub T/ CMOS circuits. The method allows us to detect faults which may not be detected by I/sub DDQ/ test methods, and is sensitive enough to detect potential faults, which do not manifest themselves as functional errors. A simple built-in current sensor, which proves to be adequate in verifying the feasibility of using the I/sub DD/ waveforms analysis is proposed to safely observe the current waveforms without significantly changing the waveforms.

This paper presents a low voltage differential current switch logic (LVDCSL) gate capable of achieving high performance for large fan-in gates. High fan-in is enabled by using a large height predischarged N-channel metal-oxide-semiconductor (NMOS) trees. The power penalty of an increased number of internal nodes in the gate is mitigated by restricting their voltage swings. The salient features of this low-voltage DCSL family are high speed for high fan-in large stack height NMOS trees, low power due to restricted internal voltage swings, simple interface to static complementary metal-oxide-semiconductor (CMOS), and a latching nature which locks out inputs once outputs are evaluated. Results show that LVDCSL is capable of working at under 2 V in a 0.35% CMOS process while being faster than comparable Domino gates. At the same time total power consumption is reduced. LVDCSL achieves 40% delay improvement and 22% power reduction in comparison with dual rail Domino gates for 8 bit carry look-ahead circuits. Results for the critical path of an adder reveal that the complexity afforded by the gate, effectively decreases the number of logic levels and leads to improved performance.

In this paper we present a robust Diflerential Current Switch Logic gate suitable for low VDD, low power operation.Differential Current Switch Logic gates achieue high performance and low power by restricting internal node voltage swings.Traditional DCSL is however highly sensitive to load imbalance because of the presence of a cross coupled inverter pair at the output.In this paper we describe LVDCSL, a low voltage DCSL family which preserves the essentialfeatures of DCSL namely, high speed, low power, restricted internal voltage swings and a latching input stage.However it is much more robust to mismatched output loads, and is capable of working at far lower voltages.In addition spikes in output transitions are greatly reduced simplifying interface to conventional CMOS circuits.Our results show that LVDCSL is capable of working at under 2volts in a 0.35,u CMOS process while being faster than comparable Domino gates.At the same time total power consumption is reduced.LVDCSL achieves 40% delay improvement and 82% power reduction in comparison with Domino gates.

An 8-bit*8-bit signed two's complement pipelined multiplier megacell implemented in 1.6- mu m single-poly, double-metal N-well CMOS is described. It is capable of throughputs of 230,000,000 multiplications/s at a clock frequency of 230 MHz, with a latency of 12 clock cycles. A half-bit level pipelined architecture, and the use of true single-phase clocked circuitry are the key features of this design. Simulation studies indicate that the multiplier dissipates 540 mW at 230 MHz. The multiplier cell has 5176 transistors, with dimensions of 1.5 mm*1.4 mm. This multiplier satisfies the need for very high-throughput multiplier cores required in DSP architectures.>