As the volume of retained data continues to increase, it is important to design primary storage systems that efficiently respond to access requests while also providing strong sustainability by reducing carbon emissions. Just over two decades ago, the Massive Arrays of Idle Disks (MAID) architecture was introduced as an energy-efficient alternative to traditional HDD-based always-on storage, employing aggressive spin-down strategies to reduce power consumption. However, high access latencies and hardware limitations led to its decline. In this work, we propose a tiered SSD+MAID storage model that combines the low-latency advantages of SSDs with the energy and carbon efficiency of a MAID system, thus offering a modern alternative to MAID while achieving lower carbon emissions than all-SSD storage. To assess the sustainability impact of such a tiered storage system, we develop a comprehensive carbon emission model that incorporates access patterns, update behaviors, and HDD spin-up dynamics. This model captures both operational and embodied carbon costs, enabling evaluations of primary storage with sustainability in mind. Through real-world workloads, we evaluate the proposed SSD+MAID system and show that it can provide a good trade-off between performance, price, and sustainability.

The rapid and widespread deployment of Internet of Things (IoT) sensors is limited by issues related to maintenance costs and safe battery disposal. While battery-less systems supported by harvesting ambient energy offer a potential solution, the weakness and instability of ambient energy result in intermittent execution. To provide data consistency, I/O operations are usually performed in the atomic sections, resulting in low-energy efficiency and low-system progress in intermittent systems. To improve application responsiveness and prevent low-energy efficiency due to atomic I/O operations, we propose a framework named FASE, which provides energy isolation assistance to support multiple asynchronous atomic I/O operations in intermittent systems. Our proposal was evaluated on a real platform, and the results show that, compared to state-of-the-art works, our proposed algorithm can increase the rate of completion for latency-sensitive applications by more than 50%.

Resistive random-access memory (ReRAM) offers a potential solution to accelerate the inference of deep neural networks by performing processing-in-memory. However, the peripheral circuits of ReRAM crossbars used to perform arithmetic operations consume significant amounts of power. Based on a power consumption analysis of the ReRAM crossbar circuits, we propose using the dynamic reference voltage scalable analog-to-digital circuits (ADCs) to conduct the dot product operation to enable the reconfigurability of the ReRAM-based neural network (NN) accelerator while maintaining accuracy. We propose a configurable ReRAM-based NN accelerator to provide various degrees of computing granularity with different levels of power consumption, creating a tradeoff between performance and power consumption in the given NN. Next, we develop an energy-efficient inference engine for the configurable ReRAM-based NN accelerator, EIF, to assign the operation unit (OU) size to perform vector-matrix multiplication (VMM) based on the data dependence of the NN. Our evaluation shows that the proposed EIF provided an energy savings of up to 36% over the state-of-the-art ReRAM-based accelerator while maintaining performance without resource duplication.

Battery-less devices offer potential solutions for maintaining sustainable Internet of Things (IoT) networks. However, limited energy harvesting capacity can lead to power failures, limiting the system’s quality of service (QoS) . To improve timely task progress, we present ETIME, a scheduling framework that enables energy-efficient communication for intermittent-powered IoT devices. To maximize energy efficiency while meeting the timely requirements of intermittent systems, we first model the relationship between insufficient harvesting energy and task behavior time. We then propose a method for predicting response times for battery-less devices. Considering both delays from multiple task interference and insufficient system energy, we introduce a dynamic wake-up strategy to improve timely task progress. Additionally, to minimize power consumption from connection components, we propose a dynamic connection interval adjustment to provide energy-efficient communication. The proposed algorithms are implemented in a lightweight operating system on real devices. Experimental results show that our approach can significantly improve progress for timely applications while maintaining task progress.

Resistive random-access memory (ReRAM) has been explored to be a promising solution to accelerate the inference of deep neural networks at the embedded systems by performing computations in memory. To reduce the latency of the neural network, all the pre-trained weights are pre-programmed in ReRAM cells as device resistance for the inference phase. However, the system utilization is decreased by the data dependency of the deployed neural networks and results in low energy efficiency. In this work, we propose a Lazy Engine for providing high utilization and energy-efficient ReRAM-based accelerators. Instead of avoiding idle time by applying ReRAM crossbar duplication, Lazy Engine delays the start time of the vector-matrix multiplication operations, with run-time programming overhead consideration, to reclaim idle time for energy efficiency while improving resource utilization. The experimental results show that Lazy Engine achieves up to 77% and 96% improvement in resource utilization and energy saving compared to state-of-the-art ReRAM-based accelerators.

Modern intelligent devices usually execute multiple neural networks to improve service quality. However, system performance degrades significantly when the working set exceeds the physical memory capability, a phenomenon called memory oversubscription. To support the execution of multiple independent neural networks with limited physical memory, this article explores resource management in GPUs with unified virtual memory and demand paging. We first analyze the relationship between the simultaneous execution of multiple neural networks from streaming multiprocessors (SM) assignment and page fault overhead from memory thrashing. To boost performance by reducing the page fault penalty, we propose a batch-aware resource management approach, BARM, including (1) batch-aware SM resource allocation to increase the batch size and (2) thrashing-preventing memory allocation to eliminate run-time thrashing. The performance of the proposed method was evaluated using a series of workloads, and response latency is reduced significantly over the state-of-the-art page fault prefetcher and batch-aware TLP management. The proposed framework was also implemented on the real platform and evaluated by a case study, and impressive results were obtained.

Modern mobile devices are equipped with heterogeneous multicore processors which integrate asymmetric CPU cores and GPUs. More cores require additional power consumption and produce more heat, which can result in performance degradation due to thermal throttling. To address this issue, this paper proposes a QT-adaptation engine to monitor current temperature and quality of service (QoS), and derives a QoS-temperature model (QT-model) through a run-time learning mechanism (QT-learning) to balance dynamic workloads and dynamic thermal behavior. Based on the derived QT-model, the QT-adaptation engine migrates threads among cores using the proposed critical thread aware scheduler to ensure high QoS, and uses a self-adapting governor to meet the temperature constraint for system robustness. The concept is implemented on a commercial LG Nexus 5× and evaluated using real world applications. Results show the proposed approach increases the frame per second rate by up to 25% compared to other current methods while meeting temperature constraints.

Mobile systems are usually equipped with heterogeneous processors and memories to trade off power and performance. The energy-efficient scheduling of such system is difficulty from two folders: tasks executed on such system with the end-to-end deadline and with varied power consumption from the heterogeneous component. A deadline-aware scheduler is proposed to deal with the performance degradation from memory bandwidth contention. A DVFS governor to manage processors and memory, and the run-time memory overclocking reclaiming are presented to minimize the energy consumption while maintaining the performance. Evaluation results show considerable schedulability and energy conservation using this framework.

Synergistic processing between multiple instruction set architecture (ISA) cores and heat flows in a 3D heterogeneous multicore chip exacerbates the complexity of thermal problems. To satisfy performance and temperature requirements, a thermal size ratio detection method is proposed to control the heat generated by task executions with consideration of synergistic processing. At run-time, a Synthetic Thermal-Efficient Manager (STEM) is proposed to dispatch tasks and thermal sizes to cores and to adjust the heat generated in each core through dynamic voltage and frequency scaling. A schedulability test with a degradation factor from synergistic processing is first derived to guarantee that the timing and thermal constraints are met for all tasks in a 3D heterogeneous-ISA multicore processor. Finally, a series of simulations obtain encouraging performance results for the proposed methodology, and a case study using commercially available technology is performed to validate the practicability of the proposed approach.

Energy efficiency is a critical issue for battery-driven mobile devices. The popularity of mobile games with increasingly sophisticated graphics raises an urgent need for an online power governor for both CPUs and GPUs. This study proposes an adaptive on-line CPU-GPU governor for games on mobile devices to minimize energy consumption. The concept is implemented on a Google Nexus 7 device and evaluated using real world gaming applications (APPs). The results show an energy savings of up to 26% compared to the Performance governor in Linux (include network, screen, and system idle power) while maintaining a stable user experience.

Online energy-efficient real-time task scheduling for a heterogeneous multicore system is complicated because of the synergistic processing between cores and trade-off between energy conservation and schedulability. This paper proposes a multicore energy efficiency ratio for minimizing energy consumption and a bandwidth reservation algorithm for improving quality of service for applications. The performance of the proposed methodology was evaluated using a series of workloads, and encouraging results were obtained.

Dynamic voltage scaling techniques are widely used in multicore embedded systems for energy conservation. The tasks of such systems are synchronized through the mutually exclusive access of shared resources, meaning that some tasks are blocked by other tasks. Thus, the problem of energy-aware real-time task synchronization in multicore systems is compounded by the trade-off between run-time blocking effects and energy minimization. This paper proposes a triple speed algorithm for enabling energy-awareness in existing multicore real-time synchronization protocols. Algorithms are presented to assign the required core frequencies to minimize energy consumption and meet timing constraints by evaluating schedulability tests in existing synchronization protocols extended using the proposed triple speed algorithm. Dynamic slack reclaiming is also discussed for superior run-time energy management. Finally, several extensive experiments and a real-life case study are reported for evaluating the proposed methodology. The results indicate that the triple speed algorithm registered$30$percent savings in energy consumption compared with those of simple extensions of the existing synchronization protocols for single-core systems.

Thermal management is a major design challenge in three-dimensional dynamically partially reconfigurable systems. Unlike three-dimensional integrated circuits, thermal management is more difficult in three-dimensional dynamically partially reconfigurable systems because of the extra heat generated by task reconfiguration. This study proposes an on-line thermal-aware task management scheme to reclaim the run-time thermal slack from low-power tasks, and uses a configurable thermal threshold to achieve a trade-off between the reconfiguration overhead and thermal distribution. The proposed scheme maximizes the tolerable task execution power to better utilize the system and provides a quality of service guarantee under the thermal constraint. This study also evaluates the capability of the proposed methodology using a series of experiments, presenting encouraging results.

Online task scheduling in heterogeneous multicore system-on-a-chip is a challenging problem due to precedence constraints and nonpreemptive task execution in the synergistic processor core. This study first proposes an online heterogeneous dual-core scheduling framework for dynamic workloads with real-time constraints. The general purpose processor core and the synergistic processor core are dedicated to separate schedulers with different scheduling policies, and precedence constraints among tasks are dealt with through interaction between the two schedulers. This framework is also configurable for low priority inversion and high system utilization. We then extend this framework to heterogeneous multicore systems with well-known dispatcher schemas. This paper presents a real case study to show the practicability of the proposed methodology, and presents a series of extensive simulations to obtain comparison studies using different workloads and scheduling algorithms.

In the past decade, energy-efficient real-time task scheduling has been widely explored in the form of various optimization problems. This paper considers energy-efficient real-time task synchronization protocols and the overhead of frequency switching in real systems design. We propose the concept of frequency locking to better manage the cost in frequency switching. To minimize the energy consumption and meet the timing constraints, algorithms are presented to assign tasks base frequencies under existing synchronization protocols which are then extended with the frequency locking concept. Finally, a series of extensive simulations is performed and a real case study is presented to evaluate the proposed methodology and obtain comparison studies using different workloads and protocols.

On-line task scheduling is a very challenging issue for dual-core real-time embedded systems, because to control priority inversion and to manage system utilization are fundamentally at odds with each other. We propose an on-line dual-core scheduling framework for dynamic workloads with real-time constraints. The processor and the co-processor are dedicated to separate schedulers with different scheduling policies, and precedence constraints among tasks are dealt with the interaction between the two schedulers. We have shown that our proposed scheduling can achieve a good balance between high system utilization and stable task response under realistic workloads.

This work is motivated by the rapid increasing of the design complexity of many embedded systems. It aims at the proposing of solutions to resolve the hardware contention issues of non-preemptive processing elements shared among tasks and the cost optimization. A software solution based on the starting time management is proposed to interleave task executions on processing elements. Algorithms are proposed to determine the required processing elements of selected types, when there is no knowledge on the releasing time of any task: When task release orders are known a priori, an optimal algorithm is presented if processing elements have the same cost; otherwise, a pseudo-polynomial-time algorithm based on dynamic programming is presented for optimal solutions. The performance of the algorithms is also evaluated for general cases

In the past decade, energy-efficient real-time task scheduling has been widely explored in terms of various optimization problems. With a very different goal, this paper considers real-time task synchronization protocols with the minimization of energy consumption. We propose the concept of frequency locking and extend the priority ceiling protocol by locking the processor frequency in a restricted way so that the cost in frequency switching is better managed. Algorithms are proposed to assign tasks base frequencies in the minimization of the energy consumption and with the consideration of schedulability tests. The capability of the proposed methodology is evaluated by a series of experiments, for which encouraging results were presented.

In recent years, many modern phased-array radars are built with commercial off-the-shelf components, and the functions of many hardware components are also reimplemented by software modules. In such systems, radar tasks could be modeled as distributed real-time tasks which require end-to-end deadline guarantees and have precedence constraints. Different from most previous work on either algorithms with restrictions in resource utilization or heuristics without analytical ways for schedulability guarantees, the objective of this paper is to propose a joint real-time scheduling algorithm for both transmitter/receiver and signal processor workloads with an analytical framework for offline probabilistic analysis and online admission control. The strength of our approach is verified by analysis results and a series of experiments based on a real phased-array radar for air defense frigates

In recent years, many modern phased array radars are built with commercial-off-the-shelf components, and the functions of many hardware components are also re-implemented by software modules. In such systems, radar tasks could be modelled as distributed real-time tasks, which require end-to-end deadline guarantees and have precedence constraints. Different from most previous work on either algorithms with restrictions in resource utilization or heuristics without analytical ways for schedulability guarantees, the objective of This work is to propose a joint real-time scheduling algorithm for both transmitter/receiver and signal processor workloads with an analytical framework for off-line probabilistic analysis and online admission control. The strength of our approach is verified by analysis results and a series of experiments based on a real phased array radar for air defense frigates [A. G. Huizing et al. (1996)].