A two-stage difference-based estimation method is presented to extract the timing skew of each sub-ADC in time interleaved analog to digital converters (TIADCs). Compared with the previous techniques, such as the correlation-based method, the main advantage is that it greatly reduces the number of multipliers and does not require digital filters. Simulation results of a four-channel TI-ADC behavioral model and experimental results from a commercial 12-bit 3.6-GS/s TI- ADC demonstrate the effectiveness and superiority of the proposed estimation method.

This paper presents an asynchronous 2-then-1 bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). The offset mismatches among the three comparators are background calibrated by quantizing the same residue signal during the last 1-bit cycle. It eliminates the dependence on the signal distribution and utilizes the following sampling phase for the settling of the calibration voltages. An asynchronous timing sequence is also proposed to avoid an external high speed clock generator. A design example of 8-bit 500 MS/s SAR ADC in 40nm CMOS technology is presented. Simulation results show that with Nyquist input, the spurious-free-dynamic-range (SFDR) achieves 62 dB while the effective number of bits (ENOBs) is 7.6 bits.

A dither-based digital background calibration exploiting metastability detector (MD) to correct capacitor mismatch error and gain error in pipelined successive approximation register (SAR) analogue-to-digital converters (ADCs) is proposed. The comparator resolving time is utilized for dither injection only when the residue is in the vicinity of the comparator threshold, thereby minimizing the loss of dynamic range. Besides, the residue amplifier is reused as a delay reference to construct the MD. By executing a dedicated delay- control calibration, the MD realizes a robustness against process, voltage, and temperature (PVT) variations. In addition, this paper also introduces the circuit design of the PVT-tracking MD. The schematic-based simulation results show that the delay- control calibration converges within thousands of decision cycles. The proposed bit-weight calibration is verified in a 14-bit pipelined SAR ADC. Behavioral simulation results show that, with calibration, the signal to noise and distortion ratio (SNDR) is improved from 58.2 to 79.1 dB and spurious-free dynamic range (SFDR) is increased from 64.5 to 97.1 dB.

This paper reports a hybrid noise shaping (NS) successive-approximation registers (SAR) ADC based on incremental sigma-delta modulator (ISDM). The combination of ISDM and NS-SAR ADC achieves the high signal-to-noise ratio (SNR) with a few extra timing and hardware penalty. The reuse of integrator for both ISDM and NS releases the demands of high-resolution multi-input comparator replaced by only a 2-input one, which also helps suppress the noise from comparator and clock to the top plate of capacitor digital-to-analog converter (CDAC) relatively. With the embedded ISDM, the gain of amplifier used in the finite impulse response (FIR) filter for NS is relaxed remarkably, and wider bandwidth (BW) as well as lower oversampling rate (OSR) is realized compared to those traditional NS-SAR ADCs. The proposed hybrid ADC is designed in 40nm CMOS process with a 1.1V supply. It achieves the Signal-to-Noise Distortion Ratio (SNDR) and the Spurious Free Dynamic Range (SFDR) of 82.4dB and 97.1dBc respectively at 80MS/s, with a signal bandwidth (BW) of 5MHz and a total power consumption of 883uW.

A current-reuse Gm-C complex filter is proposed in this paper. The bias current of input transconductor is reused to achieve both the load resistor and the transfer function's imaginary part. Meanwhile, in order to recalibrate the frequency response caused by the PVT effect, source degeneration technique is employed to realize robust effective gm which is proportional to 1/R. To demonstrate the proposed technique featuring good tuning capability and robustness to the process mismatch and variation, a first-order Gm-C complex filter was designed under the standard TSMC65nm CMOS, realizing a center frequency and a -3dB pass-band of 2MHz and 1.2MHz, respectively. The simulated results provide a mean image rejection ratio(IRR) of 16dB and a spurious-free dynamic range(SFDR) of 56.27dB. The Monte Carlo simulation indicates IRR features a minimum standard deviation of 0.426dB compared with the reported works. It has a power dissipation of 28.8μW from 1.2-V supply voltage.

This brief presents a background calibration technique for pipelined successive-approximation-register (pipelined SAR) analog-to-digital converters (ADCs), which resolves the errors from capacitor mismatches and inaccurate interstage gain errors. The dither signal is injected in the capacitor digital-to-analog converter (DAC), while its residue voltage increment is neutralized through paired comparators with opposite polarity offsets, thereby relaxing the design requirement of the residue amplifier. While one of the comparators is generating the residue signal, the other one is detecting the signal range and helping to obtain the bit weights. This brief also introduces the circuit design of paired comparators with opposite offsets. The background calibration technique is verified in a 5b + 8b pipelined SAR ADC. Simulation results show that the spurious-free dynamic range (SFDR) and the signal-to-noise and distortion ratio (SNDR) are improved from 54.5 to 94 dB and 49 to 68.9 dB, respectively. The mean value of the voltage swing increment is 34 mV with noise sources, offset, gain error, and capacitor mismatches.

Hand detection is an essential step to support many tasks including HCI applications. However, detecting various hands robustly under conditions of cluttered backgrounds, motion blur or changing light is still a challenging problem. Recently, object detection methods using CNN models have significantly improved the accuracy of hand detection yet at a high computational expense. In this paper, we propose a light CNN network, which uses a modified MobileNet as the feature extractor in company with the SSD framework to achieve a robust and fast detection of hand location and orientation. The network generates a set of feature maps of various resolutions to detect hands of different sizes. In order to improve the robustness, we also employ a top-down feature fusion architecture that integrates context information across levels of features. For an accurate estimation of hand orientation by CNN, we manage to estimate two orthogonal vectors' projections along the horizontal and vertical axes then recover the size and orientation of a bounding box exactly enclosing the hand. Evaluated on the challenging Oxford hand dataset, our method reaches 83.2% average precision (AP) at 139 FPS on a Nvidia Titan X, outperforming the previous methods both in accuracy and efficiency.

We consider a bistatic radar network that consists of multiple separated radar transmitters and receivers, which are deployed to detect potential attacks at some points of interest (PoIs). To better defend these PoIs, the design of the bistatic radar network is investigated in two stages. First, we study the problem of optimally placing a number of radar transmitters and receivers in the sense of minimizing the maximum distance product between a PoI and its closest transmitter-receiver pair. For this problem, we propose a randomized Voronoi algorithm. Next, given the radars' locations, assuming that the transmitters use fixed and orthogonal frequencies to illuminate signals for interference avoidance, we study the problem of frequency selection for the receivers. Since an intelligent attacker can adaptively change the PoI to attack, the receivers should dynamically adapt their frequencies to cover different subsets of the PoIs. Accordingly, we model the dynamic interactions between the bistatic radar network and the attacker as a repeated security game. Based on their respective information, we propose two learning algorithms for each of them, respectively. We show that if both players follow the modified-regret-matching procedures, the empirical distributions of their actions converge to the set of correlated equilibria.

Event-driven applications in wireless sensor networks feature correlated traffic bursts: after a period of idle time with light traffic loads, multiple sensors that have detected the same event have to transmit large amounts of data simultaneously to sink node or cluster head. The demand for simultaneous data transmission often causes severe collision, which is one of the most significant sources of energy consumption in wireless sensor networks. In this paper, we propose SC-MAC (sender-centric MAC), a new asynchronous duty cycle MAC protocol designed for burst traffic loads. SC-MAC achieves collision-free environment while do not introduce extra overhead. In order to minimize delivery latency in tree structure or other multi-hop networks, SC-MAC also introduces a latency optimization mechanism. We show the performance of SC-MAC through ns-2 simulation and compare it to PW-MAC, the state-of-the-art asynchronous MAC protocol. The simulation results show that SC-MAC significantly minimizes energy consumption and delivery latency.

The improved synchronization algorithm and error controller structure for OFDM system in wireless multimedia sensor networks are presented. The timing and carrier synchronization are acquired by coarse estimate and fine synchronization. The simulation results show that the improved synchronization algorithm performance of timing and carrier synchronization is better than traditional algorithm, merely poorer than Park algorithm. The OFDM synchronizer and error controller are verified on the platform of Altera FPGA. The results validate that each performance of both improved synchronization and error controlling method meets WMSN system requirements better. Timing error is only one sampling point and the frequency offset is 0.25% of sub-carrier frequency interval.

A novel all-digital 50% duty cycle corrector (DCC) is pro- posed in this paper. The DCC features include a delay unit based on precharge logic gates with low delay time and a robust SR latch under process voltage and temperature variations for final edge combination over wide frequency and duty-cycle ranges. The rising edge of the output clock has a constant delay when comparing to the input clock, which makes it easy to cooperate with a delay locked loop. The circuit is fabricated in Chartered 0.18-μm CMOS process. The acceptable input clock frequency ranges from 400 MHz to 2 GHz. The correcting error is ±3.5% at 1 GHz or ±1% at 400 MHz.

This paper studies the secrecy capacity of the multiple input single output (MISO) secrecy channel where a transmitter is communicating to a receiver in the presence of K eavesdroppers. The transmitter is equipped with multiple antennas, while the receiver and all the eavesdroppers each has a single antenna. The transmitter maximizes the communication rate, while concealing the message from all the eavesdroppers. It is known that the maximum achievable secrecy rate is obtained with the optimal transmit covariance matrix that maximizes the minimum difference between the mutual information of the secrecy user channel and those of the eavesdroppers channels. The maximum secrecy rate computation can thus be formulated as a non-convex max-min problem, which cannot be solved efficiently. This paper proposes an efficient algorithm based on quasi-convex programming, which not only leads to the optimal transmit covariance matrix, but also guarantees that it is always rank-one at any search step with finite accuracy. Such a guaranteed rank-one covariance matrix is critical to practical implementations of MISO secrecy transmission beam-forming.