The last progress in the pervasive computing field has led to the distribution of knowledge and computational power in the environment, rather than condensing it in a single, powerful entity. This allows agents to behave like insects in a swarm, that can fulfil a task communicating directly or indirectly among them. Following this vision of ambient intelligence, our work proposes a straightforward solution to coordinate a swarm of robots that have low computational capabilities. All the information and instructions are found in RFID tags that are used as a pervasive memory distributed in the environment. These robots exploit ubiquitous computing to make a formation in space, synchronise with team mates in the same zone, and finally complete a cooperative task. Before implementing the solution in a real scenario, we show the validation of our algorithm in a simulation environment.

This paper presents Geo-Linda, a physically distributed tuple space. Geo-Linda targets ubiquitous computing applications involving the detection of movement patterns of objects and people, such as the meeting of two people or the insertion of a product in a shopping cart, the loading of container in a boat... Existing distributed tuple spaces suffer two main limitations: (1) they cannot detect precisely movement patterns, leading to inconsistencies between the state of applications and the physical world; (2) they cannot detect several kinds of movement patterns. Geo-Linda tackles these two limitations, by introducing a geometric addressing mode and two new reading operations to access the tuple space. In this paper, we illustrate Geo-Linda with several small examples and a full application.

In this article we present an application to navigate through a photo collection, using context. This application proposes two navigation schemes: physical and virtual navigation. Physical navigation permits the user to seamlessly access to photos that were taken near him. Virtual navigation permits the user to virtually explore the surroundings by jumping from one photo to another.This application relies on a definition of context which is based on a notion of proximity. Proximity can be determined according to one or several dimensions. For example, with this definition the user's context can be represented by the photos that were taken near him during a precise period like the Second World War. Such a context permits the user to physically navigate the photo collection nowadays and to get photos of the surroundings that were taken during another time period. Our application offers other services, such as temporal navigation to get different views of a place, route planing or virtually entering into closed buildings.

The paper addresses the issue of improving the performance of memory management for real time Java applications, building upon the Real-Time Specification for Java (RTSJ) from the Real-Time Java Expert Group. In a first step, a thorough analysis of the parameters influencing the performance of memory management together with ways of improvement are presented. The implementation of a memory management solution, which is compliant with the RTSJ and integrating the proposed improvements is then sketched.

Distributed Shared Memory (DSM) architectures are attractive to execute high performance parallel applications. Made up of a large number of components, these architectures have however a high probability of failure. We propose a protocol to tolerate node failures in cache-based DSM architectures. The proposed solution is based on backward error recovery and consists of an extension to the existing coherence protocol to manage data used by processors for the computation and recovery data used for fault tolerance. This approach can be applied to both Cache Only Memory Architectures (COMA) and Shared Virtual Memory (SVM) systems. The implementation of the protocol in a COMA architecture has been evaluated by simulation. The protocol has also been implemented in an SVM system on a network of workstations. Both simulation results and measurements show that our solution is efficient and scalable.

In the light of the increasing throughput of local area networks, Networks Of Workstations (NOWs) which provide a Distributed Shared Memory (DSM) have become a convenient and cheaper alternative to parallel architectures in the framework of parallel scientific applications. However, the probability that a failure occurs in such a system made up of a large number of components must not be neglected, especially for long-running applications. This paper presents the design, implementation and performance evaluation of ICARE, a page-based recoverable DSM implemented on top of an ATM-based NOW running the CHORUS microkernel. ICARE relies on a Backward Error Recovery (BER) mechanism, and provides a way to combine both efficiency and high-availability. The fact that checkpoints are stored in volatile memory provides a low-cost fault-tolerance mechanism, as well as the opportunity to exploit the symbiotic relationship between the data replication implemented in DSM systems and that needed for fault-tolerance. Furthermore, ICARE efficiently implements transparent process rollback recovery. Performance evaluations show the efficiency of the ICARE prototype that implements the proposed algorithms. © 1998 John Wiley & Sons, Ltd.

Due to the increasing number of their components, Scalable Shared Memory Multiprocessors (SSMMs) have a very high probability of experiencing failures. Tolerating node failures therefore becomes very important for these architectures particularly if they must be used for long-running computations. In this paper, we show that the class of Cache Only Memory Architectures (COMA) are good candidates for building fault-tolerant SSMMs. A backward error recovery strategy can be implemented without significant hardware modification to previously proposed COMA by exploiting their standard replication mechanisms and extending the coherence protocol to transparently manage recovery data. Evaluation of the proposed fault-tolerant COMA is based on execution driven simulations using some of the Splash applications. We show that, for the simulated architecture, the performance degradation caused by fault-tolerance mechanisms varies from 5% in the best case to 35% in the worst case. The standard memory behavior is only slightly perturbed. Moreover, results also show that the proposed scheme preserves the architecture scalability and that the memory overhead remains low for parallel applications using mostly shared data.

Recent advances in computing, like high-speed networks and data-compression, make extensible distributed multimedia applications a challenging application-domain of distributed systems. Such applications like VoD (Video on Demand) or real-time conferencing are characterized by QoS (quality of service) requirements which depend on the quality of video and sound transmitted to the client and on the respect of time constraints associated to video and audio data. Much work has been done in order to provide system support aimed at meeting these requirements. However, existing proposals do not integrate the consequence of failure occurrence on the guaranteed QoS. To deal with this issue, we propose a resource reservation model that integrates availability requirements of multimedia services in addition to the QoS constraints introduced above. Our paper details the resulting model together with its integration in a distributed system. In particular we show how the model implementation can be customized in the case of a VoD server.

This paper focuses on the problem of fault tolerance in shared memory multiprocessors, and describes an architecture designed for transparently tolerating processor failures. The Recoverable Shared Memory (RSM) is the novel component of this architecture, providing a hardware supported backward error recovery mechanism which minimizes the propagation of recovery when a processor fails. The RSM permits a shared memory multiprocessor to be constructed using standard caches and cache coherence protocols, and does not require any changes to be made to applications software. The performance of the recovery scheme supported by the RSM is evaluated and compared with other schemes that have been proposed for fault tolerant shared memory multiprocessors. The performance study has been conducted by simulation using address traces collected from real parallel applications.

This paper describes an experiment in the design of a general purpose fault tolerant system, FTM. The main objective of the FTM design was to implement a low-cost fault-tolerant system that could be used on standard workstations. At the operating system level, the authors' goal was to offer fault-tolerance transparency to user applications. In other words, porting an application to FTM need only require compiling the source code without having to modify it. These objectives were achieved using the Mach micro-kernel and a modular set of reliable servers which implement application checkpoints and provide continuous system functions despite machine crashes. At the architectural level, their approach relies on a high-performance stable storage implementation, called stable transactional memory (STM), which can be implemented either by hardware or software. The authors first motivate their design choices, then detail the FTM implementation at both architectural and operating system level. They discuss the reasons for the evolution of their stable memory technology from hardware to software. They evaluate the performance of the FTM prototype. They conclude with lessons learned and give some assessments.

This paper presents the design and implementation of a mechanism aimed at enhancing the performance of distributed object-based applications. This goal as achieved by means of a new algorithm implementing placement of method executions that adapts to processors' load and to objects' characteristics, the latter allowing to approximate the cost of methods' remote execution. The behavior of the proposed placement algorithm is examined by providing performance measures obtained from its integration within a customizable distributed object-based runtime system. In particular, the cost of method executions using our algorithm is compared with the cost resulting from the standard placement technique that consists of executing any method on the storing node of its embedding object.

This paper sketches our experience with the design and implementation of a parallel object-oriented language and it distributed run-time system. The language integrates two original mechanisms for concurrency control: a synchronization mechanism that does not interfere with inheritance nor with subtyping, and a mechanism that serves for managing object groups. Because of the increasing power of interconnection networks, the language's run-time system has been designed for a distributed architecture instead of a single multiprocessor machine. Furthermore, in order to ease the development of correct applications, we have chosen to rely on the run-time system to provide the required efficiency instead of offering the programmer low level primitives to be used for producing efficient code.>

COMAs (Cache Only Memory Architectures) are an interesting class of large scale shared memory multiprocessors. They extend the concepts of cache memories and shared virtual memory by using the local memories of the nodes as large caches for a single shared address space. Due to their large number of components, these architectures are particularly susceptible to hardware failures and so fault tolerance mechanisms have to be introduced to ensure a high availability. In this paper, we propose an implementation of backward error recovery in a COMA which minimizes performance degradation and requires little hardware modifications. This implementation uses the features of a COMA to implement a stable storage abstraction using the standard memories of the architecture. Recovery data are replicated and mixed with current data in node memories both of which are managed in a transparent way using an extended coherence protocol.

The authors address the problem of implementing the CSP (communicating sequential processes) rendezvous within a transactional framework. Instead of implementing a fair nondeterministic choice and assuming the correct functioning of processors and communication media, the authors propose an efficient transactional implementation of the atomic rendezvous in the presence of processor failures in a multiprocessor machine. Both atomicity and efficiency are obtained by using high-speed stable storage devices.>

An active, RAM-based stable storage board is described. The stable storage board is intended to make it relatively fast to access data structures, and contains features to guard against incorrect access from a faulty processor or from an errant program. Basic performance data are presented and potential applications are described.>

Abstract The abstract data type concept appears to be a useful software structuring tool. A project, called ‘Système d'Objets Conservés’, which was developed at the University of Rennes, (France), gave some experience in implementing this concept. The possibility of including abstract data type into a pre‐existing compiler is demonstrated, and desirable properties of the host language are exhibited. Provision of external procedures and data makes some type checking extensions necessary: these features increase software reliability.