This paper presents an extended SIMD form data operation for multi-media signal processing and a performance evaluation of data-driven processor Qv-K1. By appending proposed data-parallel operation mechanism, the number of executed instructions is reduced compared to SIMD. The processing ability of this processor could be increased.

This paper describes the world's first commercial data-driven multimedia processors (DDMPs), developed jointly by Osaka University Kochi University of Technology, and Sharp Corporation. The data-driven principle underlying the structure of these processors was realized in a super-pipelined implementation, which was in turn based on a self-timed clocking scheme. This design made it possible to realize single chip DDMPs capable of executing tens of billions of signal processing operations per second with power consumption as low as 2 W. In terms of operations per watt, the processors exhibit threefold to tenfold improvement over conventional sequential digital signal processors (DSPs). The structure of this paper is as follows: 1) a brief introduction to the data-driven processing principle; 2) a detailed description of elementary modules for the realization of self-timed pipeline microprocessors; and 3) a description of the DDMP's developed thus far in the research project, which has continued for more than a decade. Also outlined here are the numerous advantages, in terms of both function and power consumption, of the self-timed pipeline over its synchronous counterparts. Commercially available DSP-oriented asynchronous data-driven processors and their practical applications to consumer appliances such as digital TV receivers are discussed; some programming examples are provided.

A single-chip data-driven microprocessor with special functions for distributed parallel processing is described. The implemented functions necessary for parallel processing are: relative addressing mode for program memory; efficient test and set operation of arbitrary data in data memory; transparent access of distributed shared memory; and dynamic load distribution among multiprocessors. With this microprocessor, practical parallel processing systems which exploit a wide area of scientific applications can be constructed.>