The primary purpose of this work is to automate selection of key attributes of a test data compression environment such as Embedded Deterministic Test, the first commercial test compression product. Given a test compression setup, the main objective of the proposed approach is to quickly estimate the expected test pattern count, test data volume, and the resultant test application time within the framework of the actual test compression flow when using ATPG-produced test cubes. This way one can mimic a process of test cube merging and anticipate compressibility of the resultant test patterns without resorting to CPU-intensive ATPG runs and solvers of linear equations. The obtained results, reported herein, are compared with actual stuck-at fault test patterns generated by a commercial test compression tool for several industrial designs in order to validate the proposed model. This allows a final tuning of the new scheme to arrive with a fast and accurate test compression advisement method. It can be used, prior to further steps, to devise the key elements of a test compression ecosystem such as the number of input channels and the size of on-chip test data decompressor.

Recent studies of silent data errors (SDEs) in mega-scale datacenters indicate that SDEs are caused by small delay defects that escaped detection by manufacturing tests or occurred during the lifetime of the system. A small delay defect is detected by a test that propagates a transition through one of the longest paths that includes the defect site. Once the path is selected, for every gate or cell on the path, ATPG assigns off-path input values to enable the propagation of a transition through the path. For complex gates, such as AOI and XOR, there are multiple sets of possible assignments (or input stimuli) that the ATPG can use, with substantially different propagation delays. Existing test generation procedures do not consider these differences in propagation delays once a path is selected. We propose a new approach to ATPG for small delay defects, called Timing Verification Test or TVT, that selects the off-path input values to maximize the delay of the path. The tests produced by TVT result in path delays that are significantly higher than those obtained when off-path input values are selected arbitrarily by the ATPG if they are not mandated by the propagation conditions. TVT also considers different PVT corners that affect the selection of the longest paths. Experimental results for an industrial core show that TVT increases the path delays by up to 15.91% for a set of the longest paths needed to detect small cell-aware delay faults at different PVT corners.

On-chip test data decompressors [ 1 ] are the very first devices that have had deployed ring generators [ 2 , 3 ] – high performance linear feedback shift registers (LFSRs) – that quickly proved themselves as versatile solutions capable of outperforming traditional schemes through an unmatched speed of operations and layout-friendly structures [ 4 ]. Given a characteristic (feedback) polynomial, ring generators feature smaller internal fan-outs, shorter propagation paths, and simpler circuit layout and routing than popular and commonly used Fibonacci or Galois LFSRs [ 5 , 6 ] whose long irregular feedback paths may limit the operating speed, cause frequency degradation, and may take up a fair amount of silicon area, especially for polynomials with a large number of terms [ 7 ]. Figure 1 recalls a basic architecture of a 32-bit ring generator with a primitive polynomial h ( x ) = x 32 + x 28 + x 23 + x 20 + x 17 + x 12 + x 8 + x 4 + 1, which causes this ring generator to go through all possible 2 32 – 1 nonzero values before returning to a seed state. Typically, its structure can be created by forming a ring counter, and then by adding feedback taps which correspond to successive terms of a characteristic polynomial. A feedback loop associated with tap x k is made up from k adjacent flip-flops, beginning with the leftmost ones, as shown in the figure. Note that two feedback nets cannot cross each other [ 2 ]. If one uses an appropriate characteristic polynomial, then a ring generator may assume a regular ladder-like structure. An extensive collection of such primitive polynomials is available in [ 8 ]. Since a subset of k adjacent flip-flops can be chosen in different ways as long as the resultant feedback line does not cross any other feedback line, the ring generators offer an appreciable degree of flexibility in shaping their structures.

Nonlinear feedback shift registers (NLFSRs) are well-positioned to play the key role in securing variety of digital ecosystems. They have already been deployed as major building blocks of several hardware stream ciphers, and are expected to become an essential part of hardware roots of trust that protect integrated circuits (ICs) against hardware security threats and mitigate risks associated with an unauthorized access and usage of ICs. In this article, we present two new sets of Galois NLFSRs with maximum and near maximum prime periods, respectively. All reported registers have been identified by virtue of an FPGA-based engine running in parallel around 8000 search processes. This article provides a detailed description of metrics used to characterize output sequences produced by NLFSRs, such as the number of n-tuples each output sequence is comprised of, linear complexity of output sequences, and the total number of different maximum-length sequences obtained by means of simple linear filters driven by the examined registers. This article is accompanied by tables listing all found and never presented before NLFSRs, altogether with their architectural details and the corresponding metrics.

With the biennial doubling of the number of transistors in a given area of silicon, contemporary integrated circuits (IC) are forging more and more often and will continue to forge complex system-on-chip (SoC) designs. Their equally complex manufacturing and in-system tests are now carried out through top-level test data delivery nets that enable fast streaming of test data to, from, and throughout a chip. However, it is essential to apply restrictions mitigating risks associated with unauthorized access and usage of SoCs as well as to protect the test infrastructure against hardware security threats, and thus to prevent leakage of secret information or other sensitive assets while tests are carried out. Existing security IP cores raise concerns related to their complexity in terms of area footprint, performance, power, impact on an SoC integration flow, and testability. This paper presents simple and lightweight, yet effective and scalable, test data stream ciphers (SCs) that can be used to encrypt and decrypt test data employed in tests of SoCs and delivered via Streaming Scan Network (SSN) – a new packetized test data network. A single cipher is comprised of three Galois nonlinear feedback shift registers working in tandem to yield a large number of parallel, cryptographically secure pseudorandom keystreams. A comprehensive evaluation, including NIST statistical test suits, show high efficiency of the proposed ciphers, and is reported herein.

The adverse effects of silent data errors (SDEs) on the operation of large data centers have been reported recently by hyper-scalar companies. SDEs tend to be elusive and are difficult to detect until they affect a particular application after the IC has been deployed in-field. Although the cause of SDEs ranges from manufacturing test escapes and design marginalities to design bugs, experimental data from the industry largely indicate that SDEs can be traced back to timing related issues that become more severe with aging and depend on the operating conditions of process, voltage and temperature (PVT). This paper describes a complete framework for monitoring the timing related issues under different operating conditions for test and functional operation. The framework has three components. The first component is a procedure for the identification of the longest paths that are prone to delay failures under different PVT corners. The second component is a programmable slack monitor design that monitors the changes in path delays within a detection window, and produces an alarm when a path is close to failure, with proximity to failure being a programmable feature. The third component is a procedure that determines the placement of the monitors in the design. Experimental results for an industrial design demonstrate the trade-offs related to the placement of monitors and the scenarios under which the monitors raise alarms.

Additive stream ciphers (SCs) play a host of roles in securing variety of digital ecosystems. In particular, they can encrypt and decrypt test data used in manufacturing and in-system tests of digital integrated circuits (ICs). In this capacity, SCs have become an essential part of instruments that protect ICs against hardware security threats and mitigate risks associated with an unauthorized access and usage of ICs, possibly due to scan chains. However, many IC vendors keep raising concerns attributable to the complexity of existing SCs in terms of area overhead, performance, impact on a design flow, and testability. Here is where this work comes in. It introduces a simple and lightweight, yet effective and scalable, test data stream cipher Lancet developed for the Streaming Scan Network (SSN) technology to decrypt and encrypt the content of the IJTAG communication and the SSN bus. It builds on a hybrid ring generator working in tandem with two nonlinear Galois feedback shift registers to yield a large number of parallel, cryptographically secure pseudorandom keystreams. A comprehensive evaluation, including NIST test suits, show the efficiency of the proposed cipher, and is reported herein.

Recently the semiconductor industry has been alerted by hyperscaler companies reporting impact of field errors in megascale datacenters. They tend to be elusive and very difficult to detect until they affect a particular application several days or months after the IC has been deployed in a fleet. Although the cause of such errors can be manifold, ranging from test escapes and design marginalities to design bugs, there is a consensus across the industry that they usually can be traced back to timing-related issues, as the performance of transistors changes over time or at certain environmental conditions while running specific software workloads. While there is ongoing work to study some of those defects and to explore techniques preventing such post-manufacturing test escapes, it also highlights the need for IC monitoring so that such defects are detected in the field, thereby reducing application failures. The paper demonstrates a successful application of the Streaming Scan Network technology to run in-fleet deterministic scan test on an ultralarge industrial multi-chiplet design at Amazon Web Services (AWS) cloud computing platform. One of the key advantages of the presented technology is its ability to use the same infrastructure to perform both manufacturing and in-field tests. A silicon implementation along with test power analysis are also presented.

VLSI design flows improve design parameters (performance, power, area, and testability) iteratively. Whereas the “shift left” trend implies that changes at the RTL are preferred for improving the design, it is sometimes necessary to make gate-level changes, e.g., because of layout changes or ECO. In an iterative design flow, repeated ATPG to evaluate the testability of a design after design changes have been made creates a bottleneck. The goal of this article is to address this bottleneck considering two-cycle tests for transition faults. The test generation procedure described in third article transforms an LOC test set generated for an earlier version of the design into an LOC test set for a new version without repeating the entire test generation process. To enable the transformation, it is necessary to find a mapping between the inputs and outputs of the earlier and new versions of the design, taking into consideration that RTL resynthesis may produce a new gate-level netlist, with new signal names and different input and output orders. To address two-cycle tests, the mapping is performed over two time frames of the design. Experimental results for industrial circuits with changes made at the RTL as well as gate-level demonstrate significant runtime gains with the test generation procedure described in this article.

Protection of integrated circuits (ICs) against hardware security threats has been tackled by many schemes proposed to mitigate risks associated with an unauthorized access and usage of ICs in general, and intellectual property (IP) cores in particular. Typically, this is accomplished by virtue of hardware roots of trust whose crucial security primitives entail cryptographic hash functions. They provide data integrity services and thus can support the IC authentication protocols employed to counteract potential threats such as untrusted users accessing ICs. However, IC vendors raise concerns regarding the complexity of certain hash functions in terms of area overhead, the impact on the design flow, and testability. These concerns have motivated this work presenting a simple, yet effective, lightweight, scalable cryptographic hash function H2B. It builds on a hybrid ring generator, i.e., an area and time-optimized version of a linearfeedback shift register, which works in tandem with a nonlinear sequential circuitry whose feedback network comprises bent-like functions. A comprehensive evaluation, including test suits from the National Institute of Standards and Technology, shows the feasibility and efficiency of the proposed scheme and is reported herein.

Ring generators are high speed devices formed by transformations that alter the structure of conventional linear feedback shift registers (LFSRs) while preserving a transition function of the original circuits [8]. They feature a reduced number of levels of XOR logic, minimized internal fan-outs, and simplified layout and routing. This paper discusses hybrid ring generators – a new class of lightweight linear finite state machines. While they use the principal design rules of conventional ring generators, the new devices can reduce the number of XOR gates up to seven times compared to conventional rings implementing the same characteristic polynomial. It makes a substantial contribution toward the performance of linear circuits used in a variety of test applications. Several issues related to hybrid ring generators such as designing MISRs, programable PRPGs, or phase shifters are also discussed in the paper along with data providing architectural details of hybrid ring generators for sizes up to 256 bits.

Deterministic in-system tests begin to play an essential role in safety-critical applications, in large data centers, or in monitoring silicon aging, to name just a few. All of these ecosystems require periodic, high-quality tests to assure required test coverage and short test application, especially in designs that must test themselves during system operations. In order for deterministic tests to be in-system applicable, they should compact multimillion-bit test responses with unknown ($\rm X$) values to small signatures. This, in turn, allows for a much faster input-only streaming and a simultaneous reduction of the on-chip-stored test data volume, a system memory, and test time. Typically, the unknown states, whose sources vary from uninitialized memories to unpredictable last-minute timing violations, render signatures unusable. Hence, test response compaction requires some form of protection. This article presents a user-tunable X-masking scheme. It works synergistically with on-chip test compression logic by employing encoded test data to completely filter out unknown values that otherwise might reach a test response compactor, such as a multiple-input signature register or test result sticky bits used by the on-chip compare framework. It makes the proposed scheme a very versatile of its kind. Experimental results obtained for several industrial cores show feasibility and efficiency of the proposed scheme altogether with the actual impact of X-masking on various test-related statistics.

There are many schemes proposed to protect integrated circuits (ICs) against an unauthorized access and usage, or at least to mitigate security risks. They lay foundations for hardware roots of trust whose crucial security primitives are generators of truly random numbers. In particular, such generators are used to yield one-time challenges (nonces) supporting the IC authentication protocols employed to counteract potential threats such as untrusted users accessing ICs. However, IC vendors raise several concerns regarding the complexity of these solutions, both in terms of area overhead, the impact on the design flow, and testability. These concerns have motivated this work presenting a simple, yet effective, all-digital lightweight and self-testable random number generator to produce a nonce. It builds on a generic ring generator architecture, i.e., an area and time optimized version of a linear feedback shift register, driven by a multiple-output ring oscillator. A comprehensive evaluation, based on three statistical test suits from the National Institute of Standards and Technology and BSI, show feasibility and efficiency of the proposed scheme and are reported herein.

Test set compaction is one of the key steps of the postproduction test known to bring down test pattern counts. This, in turn, allows one to reduce the corresponding test data volume, test application time, and hence the cost of testing. This article presents a method that strives to reduce the number of automatic test pattern generation (ATPG)-produced deterministic test patterns to deliver compact test sets. In principle, the new scheme works with a meaningful representation of test patterns by using external and internal necessary assignments (NAs) to determine small groups of potentially compatible faults. These faults are subsequently retargeted by the robust satisfiability (SAT)-based ATPG that produces a single test pattern for the entire group, thus making the resultant test set smaller in size. Experimental results obtained for 12 large industrial cores and stuck-at faults confirm superiority of the proposed scheme over the state-of-the-art test set compaction techniques and are reported herein.

In-system deterministic tests are used in safety-sensitive designs to assure high test coverage, short test time, and low data volume, typically through an input-streaming-only approach that allows a quick test delivery. The output side of the same scheme is, however, inherently vulnerable to unknown (X) states whose sources vary from uninitialized memory elements to the last-minute timing violations. Typically, X values degrade test results and thus test response compaction requires some form of protection. This paper presents two X-masking schemes that complement the primary (or level-A) blocking of unknown values by filtering out those X states that escape the first stage of masking and shall not reach a test response compactor or test result sticky-bits deployed by the on-chip compare framework. Experimental results obtained for eleven industrial designs show feasibility and efficiency of the proposed schemes altogether with actual impact of X-masking on various test-related statistics.

A typical VLSI design flow is iterative, implying that performance, power, area and testability are improved iteratively. With the shift left paradigm, most of the changes made to a design, including to a large extent changes to address testability, occur at the RTL. Test generation is an exception with a gate level netlist being required by ATPG tools. Within an iterative flow, repeated ATPG to reevaluate the testability of a design after its RTL has been changed becomes a bottleneck. To address this bottleneck, the test generation process needs to transform a test set generated for an earlier version of the design into a test set for a new version without repeating the entire test generation process. To enable the transformation, it is necessary to find a mapping between the inputs and outputs of the earlier and new versions of the design. The main contribution of the paper is to compute such a mapping after RTL changes and resynthesis produce a new gate level netlist, where signal names may have changed, new signals may have been introduced, and signals that existed earlier may have been removed. Experimental results for industrial circuits with changes made at the RTL show an average of 5-fold reduction in test generation time.

In-field and in-system deterministic tests begin to play a pivotal role in safety-critical applications (compliant with regulations such as ISO 26262), in large data centers, or in monitoring silicon aging. All of them require periodic, high-quality tests to assure required test coverage and short test time in designs that must test themselves during system operations. In order for deterministic tests to be in-system applicable, they should compact multi-million-bit test responses with unknowns (X) to small signatures. This, in turn, allows for a much faster input-only streaming and reduction of the stored test data volume, a system memory, and test time. Typically, the unknown states, whose sources vary from uninitialized memories to unpredictable last-minute timing violations, render signatures unusable. Hence, test response compaction requires some form of protection. This paper presents a user-tunable X-masking scheme that employs compressed data to completely filter out unknown values that otherwise might reach a test response compactor such as a MISR or test result sticky-bits used by the on-chip compare framework. Experimental results obtained for several industrial cores show feasibility and efficiency of the proposed scheme altogether with actual impact of X-mask-in2 on various test-related statistics.

A hardware root of trust (RoT) is the foundation on which all secure operations of a circuit depend, including those related to DFT. Despite many countermeasures aimed at facing potential threats such as untrusted users accessing a test interface, IC vendors raise several concerns regarding the complexity of such solutions, both in terms of area overhead and the impact on the design flow. These concerns have motivated this work presenting a simple, yet effective, comprehensive and non-intrusive lightweight hardware root of trust to counteract scan-related security threats. It builds on and easily integrates with a Streaming Scan Network (SSN) technology and takes advantage of its inherent data scrambling and packetized test data distribution.

This paper describes a fast test generation process for digital circuits that exhibit extensive structural similarity. The property of structural similarity can be seen in circuits that are subjected to engineering change order (ECO), circuits that are modified during place and route, circuits subjected to retiming, and circuits with multiple similar cores. The goal of the paper is to determine the testability of a circuit (circuit2) given a test set for a structurally similar circuit (circuit1). This is achieved by transforming a test set generated for circuit1 into a test set for circuit2 as efficiently as possible, without repeating the entire test generation process. The process described in the paper starts with a structural analysis of circuit1 and circuit2 to obtain a mapping between their inputs and outputs. The mapping is used for transforming test patterns from circuit1 into test patterns for circuit2. The experiments conducted on industrial designs show an average of more than 10-fold reduction in runtime, compared with running the entire test generation process for circuit2.

Test cost has become a critical issue for large industrial integrated circuits. Various test compression techniques have been adopted in the industry to reduce test cost. However, appropriate input and output channel counts must be selected to utilize the test compression technology best. This paper presents an efficient and effective method to estimate the test pattern counts under different compression configurations for the Embedded Deterministic Test (EDT) compression technique. In searching for the accurate estimation method, we build mathematical models that reveal the internal relationship among different compression configurations. The models are established based on novel theoretical analysis as well as actual experimental data. Accurate estimation of test pattern counts for a wide range of compression configurations can be obtained based on the results of only two ATPG runs. Experimental results on nine industrial circuits show that the average error rate of pattern count estimation is about 5%, with very few outliers. With the proposed method, a test compression designer can easily pick the best input and output channel configuration to fit the design needs.

Contemporary and emergent automotive systems are heavily populated by complex integrated electronics. The number of safety-critical devices used in advanced driver-assistance systems or autonomous vehicles is growing with high-end models containing hundreds of embedded microcontrollers. Achieving functionally safe automotive electronics requires test solutions that might be costly to engineer. Therefore, to address challenges posed by high-quality and long-term reliability requirements, this article presents low-cost test pattern generation schemes for a scan-based hybrid logic BIST of automotive ICs. It may allow one to optimize test coverage and test time during in-system test applications. The first presented technique deploys a seed-flipping PRPG to periodically complement PRPG stages in a methodical tree-traversal manner. The second scheme is based on a seed-sorting approach that allows additional tradeoffs between test data volume and test coverage. As shown in this article, the proposed schemes can be easily integrated with a test compression environment and deployed in different modes of in-system testing, such as key-off, key-on, and periodic (incremental) online tests. Experimental results obtained for automotive designs and reported herein show improvements in test quality over conventional logic BIST schemes.

Test costs for large industrial designs increase rapidly in recent years. On-chip test compression hardware has become a pragmatic technology to cut down the overall test costs by reducing the test data volume. Determining the input and output channel counts of test compression hardware that results in minimum test data volume is thus a critical issue. In this article, efficient methods to estimate test pattern counts for an extensive range of input/output counts are developed. These methods require only a small number of ATPG runs. The estimation results can then be utilized to determine the test data volume for each input/output configuration. The configuration with the estimated lowest test data volume thus can be determined. The pattern count results of each configuration for a design can also be used to determine the best suitable configuration when the design is to be embedded in an SoC system.

Spin-transfer torque magnetoresistive random-access memories (STT-MRAMs) are gradually superseding conventional SRAMs as last-level cache in System-on-Chip designs. Their manufacturing process includes trimming a reference resistance in STT-MRAM modules to reliably determine the logic values of 0 and 1 during read operations. Typically, an on-chip trimming routine consists of multiple runs of a test algorithm with different settings of a trimming port. It may inherently produce a large number of mismatches. Diagnosis of such a sizeable volume of errors by means of existing memory built-in self-test (MBIST) schemes is either infeasible or a time-consuming and expensive process. In this paper, we propose a new memory fault diagnosis scheme capable of handling STT-MRAM-specific error rates in an efficient manner. It relies on a convolutional reduction of memory outputs and continuous shifting of the resultant data to a tester through a few output channels that are typically available in designs using an on-chip test compression technology, such as the embedded deterministic test. It is shown that processing the STT-MRAM output by using a convolutional compactor is a preferable solution for this type of applications, as it provides a high diagnostic resolution while incurring a low hardware overhead over traditional MBIST logic.

Test compaction and the associated test data compression are two key components of the post-production test as they reduce test pattern counts, the resultant test data volume, test application time, and hence the cost of testing. The paper describes a method that strives to reduce the number of ATPG-produced deterministic test patterns to deliver compact test sets. In principle, it is based on a dimensionality reduction paradigm by working with a meaningful representation of test patterns using external and internal necessary assignments to determine small groups of potentially compatible faults. These faults are subsequently retargeted by the robust SAT-based ATPG and its solvers producing a single test pattern for the entire group, thus making the resultant test set smaller in size. Experimental results obtained for several industrial designs and stuck-at faults confirm superiority of the proposed scheme over state-of-the-art test set compaction techniques and are reported herein.

This article describes a defect-oriented test (DOT) approach, which enables a complete physical defect-based automatic test pattern generation (ATPG) for the digital logic area of CMOS-based designs. Total critical area (TCA)-based methods are presented for the generation of needed DOT views to enable the generation of complete DOT-based patterns for detecting all cell-internal and as well all cell-external physical defects. The major aim of these new methods and patterns is to further reduce the defect rate of manufactured ICs, in addition to what is already achieved with traditional and cell-aware test (CAT) fault models. We present test results, including achieved defect rate reduction in defective parts per million (DPPM), from a large 14-nm FinFET design, including a correlation to system-level-test (SLT) fails. For a second, mature 160-nm automotive mixed-signal sensor we present high-volume production test results, again measured in DPPM, and we provide test coverage figures moving away from counting detected faults to calculating detected TCA which is reported as the chip level TCA coverage.

Hybrid test schemes comprising on-chip test compression and logic built-in self-test are expected to play a pivotal role in the design of new integrated circuits and delivering high quality tests. As architectural differences between these two paradigms are gradually blurring, and both schemes efficiently share test logic, they become more vulnerable to unknown (X) states whose sources vary from uninitialized memory elements to unwrapped-for-test analog modules. Typically, X values degrade test results, and thus test response compaction schemes must be duly protected. This article presents maXpress-an X-tolerant tunable compactor deploying a new scan chain selection mechanism capable of completely masking X states, as required by many in-system or one-directional streaming test applications, within redefinable groups of scan chains and designated scan shift cycles. The proposed scheme is also supporting separate observation scan chains that, in contrast to conventional scan, capture faulty effects every shift cycle, while their content is gradually shifted into a compactor shared with the remaining chains. In addition to a new layout-friendly architecture, the article proposes algorithms to automate maXpress control settings based on scan chain selection rules deployed to suppress X states. Experimental results obtained for industrial designs show feasibility and efficiency of the proposed scheme altogether with actual impact of X-masking on a resultant test coverage and test pattern counts.

As cars become increasingly computerized and their safety functions evolve rapidly, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is rising dramatically with high-end models containing hundreds of embedded microcontrollers. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive systems. This article presents a scan-based test scheme optimizing test time and area overhead during manufacturing and in-system test of automotive electronics. The proposed scheme deploys observation test points that capture the faulty effects in every shift cycle into separate observation scan chains. To reduce area overhead, the scheme enables the sharing of flip-flops among control points. It is also shown how test points enhance test coverage (TC) in the presence of cascaded clock gaters. Finally, processing challenges when fault simulating every scan shift cycle to determine TC are addressed. Experimental results obtained for contemporary automotive designs and reported herein show significant improvements in test quality over traditional solutions.

As the use of electronic components grows rapidly in the automotive industry, the number of complex safety-critical devices used in advanced driver assistance systems or autonomous cars is rising with high-end models containing more than 200 embedded microcontrollers. Achieving functionally safe automotive electronics requires test solutions that address challenges posed by high quality and long-term reliability requirements mandated, for example, by the ISO 26262 standard. The paper presents test pattern generation schemes for a scan-based logic BIST optimizing test coverage and test time during in-system test applications for automotive ICs. As a part of overall safety, they help in ensuring reliable operations of vehicle's electronics throughout their lifecycles. The proposed schemes can be deployed in different modes of in-system testing, including key-off, key-on, and periodic (incremental) online tests. Experimental results obtained for automotive designs and reported herein show improvements in test quality over conventional logic BIST schemes.

A novel method to efficiently and accurately prognosticate the pattern count at different input compression ratios with the Embedded Deterministic Test (EDT) compression technology is proposed. With this method the total ATPG run time can be significantly reduced compared to the currently used trial-and-error method.

Over the past two decades, test data compression has become a de facto technology used in large industrial designs to reduce the overall test cost. During DFT planning, it is very important to understand the impact of using different numbers of input/output channels on test coverage, test cycles, and test data volume. In this paper, an efficient method to estimate the test data volume with different input channel counts using the Embedded Deterministic Test (EDT) compression technology is proposed. The results can then be used to quickly determine the scan configuration that results in the least or near least test data volume. With this method, the total ATPG run time can be reduced by a factor of more than 10X compared to the currently used trial-and-error method.

System-on-Chip (SoC) designs are increasingly difficult to test using traditional scan access methods without incurring inefficient test time, high planning effort, and physical design/timing closure challenges. The number of cores keeps growing while chip pin counts available for scan remain constant or decline, limiting the ability to drive cores concurrently. With increasingly commonplace tiling and abutment, the scan distribution hardware must be placed inside the cores, making balanced pipelining when broadcasting to identical cores difficult. optimizing test time requires analyzing all the cores and subsequently changing the test hardware in the cores. Internal shift speed constraints may limit the ability to shift data in and out of the chip at high rates. Differences in pattern counts or scan chain lengths between cores tested in parallel can result in padding and increased test time. SSN is a bus-based scan data distribution architecture designed to address all these challenges. It enables simultaneous testing of any number of cores even with few chip I/Os. It facilitates short test time by enabling high-speed data distribution, by efficiently handling imbalances between cores, and by supporting testing of any number of identical cores with a constant cost. It provides a plug-and-play interface in each core that is well suited for abutted tiles, and simplifies scan timing closure. This paper also compares the test cost and implementation productivity of SSN with those of Intel's Structural Test Fabric.

There is a growing number of integrated circuits that deploy hybrid test schemes combining on-chip test compression with logic BIST, with both techniques working synergistically to deliver high quality tests. As their architectural differences are gradually blurring, and both schemes efficiently share test logic, they become more vulnerable to unknown (X) states whose sources vary from uninitialized memory elements to unwrapped-for-test analog modules. Typically, X values degrade test results, and thus test response compaction schemes must be duly protected. This paper presents maXpress – an X-tolerant programmable compactor deploying a new scan chain selection mechanism capable of completely (as required by many in-system test applications) masking X states within redefinable groups of scan chains and designated scan shift cycles. In addition to the new architecture, the paper proposes an algorithm to automate maXpress control settings based on scan chain selection rules deployed to suppress X states. Experimental results obtained for a variety of industrial designs show feasibility and efficiency of the proposed scheme altogether with actual impact of X-masking on a resultant test coverage and test pattern counts.

As the complexity of industrial integrated circuits continue to increase rapidly, test data compression has now become a de facto technology for large designs to reduce the overall test cost. During the design for test (DFT) planning, it is critical to understand the impact of using different numbers of input/output test channels on test coverage, test cycles, and test data volume. In this paper, two approaches to predict the test pattern counts and test data volumes with different input channel counts are presented, one with the compression tool able to generate channel-scaling patterns and the other without this capability. The results can be used to determine the scan test configuration that results in the smallest or near smallest test data volume. Experiments on industrial circuits show that the average error rates of pattern count prediction for most circuits are less than 10% for both approaches. The error rates of the predicted smallest data volumes are all less than 3.5%. The total ATPG run time can be reduced by a factor of more than 10X compared to the currently used trial-and-error approach.

This paper proposes an innovative design methodology for layout-friendly decompressor used in EDT compression architecture. A segmented decompressor architecture is proposed, in which each segment drives a subset of scan chains. The EDT input channel injectors are carefully selected to maximize the encoding capacity for all scan chains. Experimental results with several large industrial designs demonstrate that using the proposed technology, the routing congestion introduced by EDT decompressor is reduced significantly with negligible impact on test coverage and improved pattern count.

This article presents a next-generation test data compression scheme. It builds on the isometric compression paradigm, but makes it more flexible and elevates encoding efficiency to values unachievable through state-of-the-art sequential compression schemes. Furthermore, its programmable selection of full-toggle scan chains ensures high test coverage and virtually eliminates compression aborts. The presented approach follows from a fundamental observation that among test cube care bits, only a very few have a status of necessary assignments (their locations cannot be changed), whereas the remaining ones have alternative sites. These test cubes are used to form circular test templates which synergistically control a decompressor and guide back ATPG to find assignments yielding highly compressible test patterns. A redesigned low-silicon-area decompressor is also capable of reducing switching rates in scan chains with a new test power control scheme. The experimental results obtained for large industrial designs and other benchmark circuits confirm the superiority of the proposed scheme over existing techniques and are reported herein.

As the automotive industry enters a period of rapid evolution changing the way cars are designed and produced, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is progressively rising with high-end models containing around 120 MCUs. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive electronics. This paper presents Stellar BIST-a next generation compression scheme for in-system automotive test. The proposed solution can work with any sequential test compression. It builds on a finding that certain clusters of test vectors are capable of detecting many random-resistant faults, where a cluster consists of a parent (base) pattern and its transformed derivatives. Stellar BIST involves generating vectors based on simultaneous and multiple complements of scan slices of encodable parent patterns. The multiple complements are also skewed between successive patterns to diversify the resultant tests. The new scheme elevates compression to values unachievable through conventional reseeding-based solutions and provides significant tradeoffs between storage requirements and test application time, critical for in-system automotive applications. The experimental results obtained for industrial designs and different fault models illustrate feasibility of the proposed test scheme and are reported herein.

As cars become increasingly computerized and their safety functions are evolving rapidly, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is progressively rising with high-end models containing more than a hundred embedded microcontrollers. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive electronics. The paper presents a scan-based LBIST scheme optimizing test time and area overhead during in-system test applications for automotive ICs. It ensures highly reliable operations of ICs for the duration of their lifespan. The proposed scheme works with observation test points that capture faulty effects every shift cycle into separate observation scan chains. To reduce area overhead, the scheme takes advantage of a procedure allowing one to share flip-flops among control points. It is also shown how test points can enhance test coverage in the presence of cascaded clock gaters. Finally, processing challenges when fault simulating every scan shift cycle to determine observed faults are addressed. Experimental results obtained for contemporary automotive designs and reported herein show significant improvements in quality of test over traditional BIST schemes.

The semiconductor industry ramping up design capabilities for emerging technologies is facing unprecedented test quality and yield management challenges. To facilitate diagnosis of yield issues and to enable repair processes, an accurate defect isolation is needed with support of more advanced test, diagnostic, and yield analysis tools. Scan remains instrumental in developing more advanced DFT technologies, including logic BIST and on-chip test data compression. Its reliable operations are essential for test pattern bring-up, failure analysis, and yield learning. This paper demonstrates how to re-architect on-chip test data compression environment to enable multiple and repeated scan integrity tests for advanced test procedures, including various forms of stroboscopic electron-beam imaging and laser voltage imaging. The presented approach avoids the repetitive loading of scan chains and therefore reduces significantly test time and may support advanced diagnostic techniques. The new solution has virtually no area overhead, and does not compromise the performance of the original test logic.

Logic built-in self-test (LBIST) is now increasingly used with on-chip test compression as a complementary solution for in-system test, where high quality, low power, low silicon area, and most importantly short test application time are key factors affecting ICs targeted for safety-critical systems. Test points, common in LBIST-ready designs, can help to reduce test time and the overall silicon overhead so that one can get desired test coverage with the minimal number of patterns. Typically, LBIST test points are dysfunctional when enabled in an ATPG-based test compression mode. Similarly, test points used to reduce ATPG pattern counts (PCs) cannot guarantee desired random testability. In this paper, we present a hybrid test point technology designed to reduce deterministic PCs and to improve fault detection likelihood by means of the same minimal set of test points. The hybrid test points are subsequently deployed in a scan-based LBIST scheme addressing stringent test requirements of certain application domains such as the automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage. The new scheme is a combination of pseudorandom test patterns delivered in a test-per-clock fashion through conventional scan chains and per-cycle-driven hybrid observation test points that capture faulty effects every shift cycle into dedicated scan chains. Their content is gradually shifted into a compactor shared with the remaining chains that deliver responses once a test pattern has been shifted-in. Experimental results obtained for industrial designs confirm feasibility of the new schemes, and they are reported herein.

The paper presents a novel test data compression scheme. This low-silicon-area solution builds on the isometric compression paradigm, but makes it more flexible, elevates encoding efficiency to values unachievable through any conventional type of sequential compression, and ensures high test coverage due to programmable selection of full toggle scan chains. The presented approach follows from a fundamental observation that only a few specified positions in test cubes are necessary to detect faults, while the remaining ones have alternative sites. Such test cubes are used to form circular test templates which synergistically control a decompressor and guide ATPG to find assignments yielding highly compressible test cubes. A redesigned decompressor is also capable of reducing switching rates in scan chains with a new test power control scheme. Experimental results obtained for large industrial designs confirm superiority of the proposed scheme over state-of-the-art techniques and are reported herein.

This paper presents DPPM reduction results achieved with new Defect Oriented Test (DOT) methods/patterns applied to designs manufactured in advanced FinFET technologies. Focus of this paper is on Timing-Aware Cell-Aware Test (TA-CAT) patterns targeting small-delay defects of FinFET transistors, and a new DOT method which explicitly targets chip layout dependent cell-neighborhood defects. Test results from traditional Stuck-at/Transition patterns, from traditional CAT patterns, from TA-CAT patterns, and as well from cell-neighborhood patterns, applied to FinFET technology designs, will be presented in this paper. In addition, a correlation to System-Level-Test fails will be discussed.

With the growing number of very complex safety-critical components used in advanced driver assistance systems and autonomous vehicles, integrated circuits in this area must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This, in turn, requires advanced test solutions that have to respond to challenges posed by automotive parts. This paper presents Stellar BIST - a deterministic two-level compression scheme for in-system automotive test. The proposed solution seamlessly integrates with any sequential test compression scheme and takes advantage of the fact that certain clusters of test vectors detect many random-resistant faults where a cluster consists of a parent pattern and its transformed derivatives. Stellar BIST involves generating vectors based on simultaneous and multiple complements of scan slices of encodable parent patterns. The multiple complements are also skewed between successive patterns to diversify the resultant tests. The new scheme elevates compression to values unachievable through conventional reseeding-based solutions and provides significant trade-offs between area and time, critical for in-system automotive applications. Experimental results obtained for large industrial designs with stuck-at and transition faults illustrate feasibility of the proposed test scheme and are reported herein.

This is the extended summary of the PhD thesis on new test point insertion techniques. The thesis provides a comprehensive study of innovative DFT schemes going far beyond traditional logic BIST-based applications of test points. The proposed methods visibly decrease pattern counts, reduce test generation and test application times, and increase test coverage by means of algorithms capable of identifying and resolving conflicts between circuit's internal signals. In particular, it is shown that new test points provide, on the average, 2×-3× increase in test compression for stuck-at, transition and cell-aware patterns. Furthermore, it is demonstrated that test-point-centric DFT logic can be successfully used to lock a circuit or hide its functionality. As a result, this approach improves the overall hardware security against reverse engineering, IC cloning, and IP theft.

This paper presents a new staggered test pattern generation scheme. It produces deterministic stimuli in the course of a test-per-clock-based process by using dedicated capture-per-cycle observation test points. These observation points, once inserted into a design, form dedicated scan chains with the capability of capturing test responses during shift cycles when other regular scan cells are loading test patterns. This new scan infrastructure enables one to generate more compact test patterns, reduce test pattern counts, systematically detect many additional faults, and keep the resultant silicon real-estate at the acceptable level. It appears that original scan cells of a design can provide good observability for staggered test patterns. Thus, capture-per-cycle observation test points are directly inserted at selected scan cells' inputs with a minimal impact on the design. Experimental results obtained for large industrial designs illustrate feasibility of the proposed ATPG and are reported herein.

Growing reverse-engineering attempts to steal or violate a design intellectual property (IP), or to identify the device technology in order to counterfeit integrated circuits (ICs), raise serious concerns in the IC design community. As the information derived from these practices can be used in a number of malicious ways, various active techniques have been proposed and deployed to protect IP, of which logic locking is a vital part. It allows inserting certain gates in a circuit's data path to lock outputs to fixed logic values, if a wrong unlocking key is applied. This paper demonstrates that test points-industry-proven design-for-test technology used primarily to enhance the overall design testability-can also be reused in the mission mode to lock the circuit, and thus to improve the hardware security against IP piracy. In particular, it is shown that test points can facilitate the hiding of design functionality from adversaries. As a result, not only is the overall design testability improved, but also effective protection against piracy through unauthorized excess production and other forms of IP theft is ensured. Experimental results on industrial designs with test points demonstrate that the proposed scheme is effective in achieving a desired degree of hardware obfuscation.

Several hard-to-detect faults occurring in read-only memories require complex test algorithms that make it difficult to perform accurate diagnosis in a reasonable time. The primary reason for this is a multitude of reference signatures that need to be stored and compared against the actual data obtained from a ROM-under-test in order to isolate the failing memory sites. This paper presents techniques that facilitate fault diagnosis when deploying complex test algorithms such as GALPAT or Walking 1/0. The new diagnostic techniques reduce processing time and a tester memory size such that it becomes feasible to identify hard-to-detect faults within a memory BIST infrastructure.

This paper presents a novel low-area scan-based logic built-in self-test (LBIST) scheme that addresses stringent test requirements of certain application domains such as the fast-growing automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage of conventional BIST schemes. Alternatively, one may consider applying a much larger number of vectors within the same time interval. Although the new scheme may resemble traditional BIST logic, it is a combination of pseudorandom test patterns delivered in a test-per-clock fashion through conventional scan chains and per-cycle-driven hybrid test points that creates this new synergistic LBIST paradigm. The hybrid observation points, inserted at the most suitable locations, capture faulty effects every shift cycle into dedicated flip-flops that form separate scan chains. Their content is gradually shifted into a compactor, which is shared with the remaining scan chains that still deliver test responses captured once the entire test pattern has been shifted-in. Experimental results obtained for industrial designs illustrate feasibility of the proposed BIST scheme in terms of test time, test coverage, and area overhead, and they are reported herein.

This paper presents Star-EDT-a novel deterministic test compression scheme. The proposed solution seamlessly integrates with EDT-based compression and takes advantage of two key observations: 1) there exist clusters of test vectors that can detect many random-resistant faults with a cluster comprising a parent pattern and its derivatives obtained through simple transformations and 2) a significant majority of specified positions of ATPG-produced test cubes are typically clustered within a single or, at most, a few scan chains. The Star-EDT approach elevates compression ratios to values typically unachievable through conventional reseeding-based solutions. Experimental results obtained for large industrial designs, including those with a new class of test points aware of ATPG-induced conflicts, illustrate feasibility of the proposed deterministic test scheme and are reported herein. In particular, they confirm that the Star-EDT can act as a valuable form of deterministic BIST.

There is mounting evidence that automatic test pattern generation tools capable of producing tests with high coverage of defects occurring in the large semiconductor nanometer designs unprecedentedly inflate test sets and test application times. A design-for-test technique presented in this paper aims at reducing deterministic pattern counts and test data volume through the insertion of conflict-aware test points. This methodology identifies and resolves conflicts across internal signals allowing test generation to increase the number of faults targeted by a single pattern. This is complemented by a method to minimize silicon area needed to implement conflict-aware test points. The proposed approach takes advantage of the conflict analysis and reuses functional flip-flops as drivers of control points. Experimental results on industrial designs with on-chip test compression demonstrate that the proposed test points are effective in achieving, on average, an additional factor of 2×-4× compression for stuck-at and transition patterns over the best up-to-date results provided by the embedded deterministic test (EDT)-based regular compression.

This paper presents a novel scan-based design for test (DFT) paradigm. Compared with conventional scan, the presented approach either significantly reduces test application time while preserving high fault coverage or allows applying a much larger number of vectors within the same time interval. An equally important factor is the toggling activity during test-with this scheme, it remains similar to that of the mission mode. Several techniques are introduced that allow integration of the proposed scheme with the state-of-the-art test generation and application methods. In particular, the new scheme uses redesigned scan cells to dynamically configure scan chains into different modes of operation for use with the underlying test-per-clock principle. The experimental results obtained for large and complex industrial application-specific IC designs illustrate the feasibility of the proposed test scheme despite additional costs and efforts entailed in consolidating architectural changes and operations across a DFT flow.

Recent reverse-engineering attempts to steal a competitive design intellectual property (IP) or to identify the device technology in order to counterfeit integrated circuits (ICs) have raised serious concerns in the IC design community. This paper demonstrates that test points - industry-proven design-for-test technology used to enhance the overall design testability - can also be deployed in the mission mode to obfuscate the circuit's structure, and thus to improve the hardware security against reverse engineering, IC cloning, and IP theft. In particular, it is shown how test points can facilitate the hiding of design functionality from adversaries. As a result, not only the overall design testability is improved, but also effective protection against reverse engineering and other forms of attacks is ensured.

Typically IDDQ measurement based tests are used to detect transistor-stuck-on (TSON) faults in digital CMOS circuits. As the minimum feature sizes of digital VLSI circuits are reduced and the magnitudes of static current of VLSI chips increase, detection of TSON faults using IDDQ measurements is becoming difficult if not impossible. For this reason voltage based tests, called logic tests in this work, are being investigated. In this work we propose generation of logic tests based on Boolean functions implemented by the gates in CMOS digital logic circuits. We also show that, when available, the tests proposed in this work should be preferred over earlier proposed IDDQ based tests. Experimental results on ISCAS-89 and ITC'99 benchmark circuits demonstrate the effectiveness of the proposed logic tests.

Conflict-aware test points, introduced recently, facilitate significant reductions in deterministic test pattern counts. However, dedicated flip-flops driving control points increase test logic area. This paper presents a method to minimize silicon area needed to implement conflict-aware test points by reusing functional flip-flops as drivers of control points. Conflict analysis is applied during the test point selection process, and ATPG verification is run for every potential candidate. Experimental results show that functional flip-flops can be reused as drivers for more than 90% of the control points with the average of 5% penalty in pattern count increase as compared to methods using only dedicated flip-flops. After replacing dedicated flip-flops with functional flip-flops, conflict-aware test points can still achieve remarkable pattern count reductions.

Logic built-in self-test (LBIST), originally introduced for board, system, and in-field tests, is now being increasingly used with on-chip test compression. This hybrid approach allows LBIST to become a complementary solution for in-system test, where high quality, low power, low silicon area, and most importantly short test application time are key factors affecting ICs that are targeted for safety-critical and automotive systems. Test points are common in BIST-ready designs where they play a key role in reducing both test application time given a test coverage goal and the overall silicon overhead so that one can get a desired coverage with the minimal number of patterns. Unfortunately, these test points are typically dysfunctional when enabled in an ATPG-based test compression mode. Similarly, test points used to reduce ATPG-based test pattern counts cannot guarantee desired random testability. Incompatibility of both types of test points has motivated research presented in this paper. We present a novel hybrid test point technology designed to both reduce deterministic pattern counts and improve fault detection likelihood by means of the same minimal set of test points. Experimental results obtained for large industrial designs illustrate feasibility of the proposed hybrid test points and are reported herein.

Detecting the defects inside the CMOS cells, especially the stuck-open faults, has gained a lot of attentions in recent years. It had been shown the test set generated by using the transition fault model is not sufficient to detect the stuck-open faults. In this paper, we propose an enhanced transition fault model, named cell transition, to improve the quality of the transition test set on detecting the stuck-open faults inside the CMOS cells. The fault sites targeted by the proposed model are placed at the cell boundary in order to keep the fault population similar to the transition fault model. Experimental results demonstrate the cell transition test set detects more stuck-open faults than the transition test set while the test coverage achieved for the transition faults is close to that obtained by the transition test set. Moreover, the number of generated tests is slightly higher than the transition test set.

This paper presents a novel scan-based DFT paradigm. Compared to conventional scan, the presented approach either significantly reduces test application time while preserving high fault coverage, or allows applying much larger number of vectors within the same time interval. An equally important factor is the power dissipated during test - with the new scheme it remains similar to that of the mission mode. Several techniques are introduced that allow easy integration of the proposed scheme with the state-of-the-art test generation and application methods. In particular, the new scheme uses redesigned scan cells to dynamically configure scan chains into different modes of operation for use with the underlying test-per-clock principle. Experimental results obtained for large and complex industrial ASIC designs illustrate feasibility of the proposed test schemes and are reported herein.

This paper presents a new method to design digital circuits for low pattern counts, one of the key factors shaping cost-effective VLSI test schemes. The method identifies the largest conflicts between internal signals that prevent efficient test compaction in ATPG. These locations are modified by inserting conflict-reducing test points (CRTP) to significantly reduce the ATPG-produced pattern counts. Experimental results obtained for large industrial designs with on-chip test compression demonstrate, on average, 3x -- 4x reduction in stuck-at and transition patterns and 3x shorter ATPG times.

The introduction of FinFET technology has accelerated the adoption of patterns that target cell internal defects such as cell-aware tests. Even though cell-aware tests can replace stuck-at and transition patterns from the screening point of view, we have to address the increase in test data volume. This combined with the growing gate counts enabled by new technology nodes is driving the need for even greater compression levels. In this paper, we present a novel test points technology designed to reduce deterministic pattern counts for cell-aware tests. The technology is based on identification and resolution of conflicts across internal signals allowing ATPG to significantly increase the number of faults targeted by a single pattern. Experimental results on a number of industrial designs with test compression demonstrate that the proposed test points are effective in achieving, on average, a 3×–4× multiplicative increase in compression for 1-cycle and 2-cycle cell-aware patterns.

The paper presents a novel deterministic built-in self-test (BIST) scheme. The proposed solution seamlessly integrates with on-chip EDT-based decompression logic and takes advantage of two key observations: (1) specified positions of ATPG-produced test cubes are typically clustered within a single or a few scan chains for a small number of successive scan shift cycles, (2) only a small fraction of the specified positions are necessary to detect a fault, and most of the remaining ones have several alternatives that can be obtained by inverting preselected scan slices (all scan cells within a given cycle). The proposed approach elevates compression ratios to values typically unachievable through conventional reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed logic BIST scheme and are reported herein.

Provides an abstract for each of the presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings.

This paper introduces a novel test data compression scheme, which is primarily devised for low-power test applications. It is based on a fundamental observation that in addition to low test cube fill rates, a very few specified bits, necessary to detect a fault, are actually irreplaceable, whereas the remaining ones can be placed in alternative locations (scan cells). The former assignments are used to create residual test cubes and, subsequently, test templates. They control a power-aware decompressor and guide automatic test pattern generation to produce highly compressible test patterns through finding alternative assignments. The proposed approach reduces, in a user-controlled manner, scan shift-in switching rates with minimal hardware modifications. It also elevates compression ratios to values typically unachievable through conventional low-power reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

This paper presents several techniques employed to resolve problems surfacing when applying scan bandwidth management to large industrial multicore system-on-chip (SoC) designs with embedded test data compression. These designs pose significant challenges to the channel management scheme, flow, and tools. This paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with embedded deterministic test-based test data compression. The same solutions allow efficient handling of physical constraints in realistic applications. Finally, state-of-the-art SoC test scheduling algorithms are rearchitected accordingly by making provisions for: 1) setting up time-effective test configurations; 2) optimization of SoC pin partitions; 3) allocation of core-level channels based on scan data volume; and 4) more flexible core-wise usage of automatic test equipment channel resources. A detailed case study is illustrated herein with a variety of experiments allowing one to learn how to tradeoff different architectures and test-related factors.

This paper describes a low-power (LP) programmable generator capable of producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the best-to-date built-in self-test (BIST)-based pseudorandom test pattern generators. It is comprised of a linear finite state machine (a linear feedback shift register or a ring generator) driving an appropriate phase shifter, and it comes with a number of features allowing this device to produce binary sequences with preselected toggling (PRESTO) activity. We introduce a method to automatically select several controls of the generator offering easy and precise tuning. The same technique is subsequently employed to deterministically guide the generator toward test sequences with improved fault-coverage-to-pattern-count ratios. Furthermore, this paper proposes an LP test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the PRESTO-based logic BIST (LBIST) infrastructure. The proposed hybrid scheme efficiently combines test compression with LBIST, where both techniques can work synergistically to deliver high quality tests. Experimental results obtained for industrial designs illustrate the feasibility of the proposed test schemes and are reported herein.

This paper introduces a low-power test compression scheme that can also be used in a conventional BIST environment. The key contribution is an observation that simple broadcasting of a constant value to predetermined subsets of scan chains allows visible reductions of both toggling rates and pattern counts provided these subsets can be regrouped when feeding scan chains with either decompressed test patterns or pseudorandom vectors. While the proposed solution requires minimal modifications of the existing scan gating logic, its synergistic use with test compression algorithms yields a low scan load switching activity, reduced test time, and less intensive traffic of control data. Consequently, the proposed scheme helps to resolve problems related to test power dissipation and elevated test durations.

The paper presents a high-speed serial interface between external tester and Embedded Deterministic Test (EDT) compression logic hosted by SoC designs. With only a single bidirectional link, the system is capable of feeding distributed heterogeneous cores with hundreds of test channels. Moreover, it synergistically supports EDT bandwidth management to improve the overall test performance. A detailed study indicates a high potential of the serial EDT approach to handle large multicore SoC designs by deploying only a single serial interface and completing the entire test for stuck-at faults in less than one second. Experiments conducted with the help of FPGA -- based evaluation platform confirm feasibility and a high effectiveness of the proposed solution.

On-chip test compression has quickly established itself as one of the mainstream design-for-test (DFT) methodologies. It assumes that a tester delivers test patterns in a compressed form, and on-chip decompressors expand them into actual data loaded into scan chains. This paper presents a new and comprehensive method to boost performance of sequential test compression and ATPG operations. The approach is primarily aimed at reducing CPU time associated with generating and compressing test patterns. It prevents ATPG from assigning specified values to many inputs in order to cut down a time-consuming backtracking process needed to resolve conflicts leading to compression aborts. The proposed scheme efficiently combines test compression constraints with ATPG. Experimental results obtained for industrial designs illustrate feasibility of the proposed scheme and are reported herein.

In the paper, two methods of ensuring high quality of the memory built-in self-test tools are presented. The described ideas illustrate general methods and are applicable to any commercial memory BIST tool. The first solution describes controller emulation in order to validate each step of the real controller's operations. The second approach presents a way to determine the test algorithms' fault coverage by means of the memory fault simulator. The experimental results show functional benefits and effectiveness of the proposed solutions.

High quality is an absolute necessity for automotive designs. This paper describes an approach to improve the overall defect coverage for CMOS-based high quality automotive designs. We present results from a cell-aware (CA) characterization flow for 216 cells, the pattern generation flow for a 130nm smart power design, and high-volume production test results achieved after testing multimillion parts. The idea behind CA tests is to detect cell-internal (CI) bridges, opens, leaking and high resistive transistor defects which are undetected with state-of-the-art tests. The production test results have shown that the CA tests detect various failing parts during a first wafer sort test which still resulted into unique failing parts after a second wafer sort test done at a different temperature and with additional tests. The obtained results encouraged us to continue this work beyond this paper to run further experiments with the final goal to eliminate the stuck-at (SA) and transition delay (TR) test by simultaneously improving the quality with CA tests which are a superset of SA and TR tests.

This paper presents a test data volume (TDV) reduction method for designs utilizing extremely high compression configurations, and it enables reducing the pin count interfacing with the Automatic Test Equipment. Based on the encoding requirements for every test cube, the proposed test compression method changes the number of shift cycles used to load the test stimuli dynamically. No additional pins or modification of the existing scan chains is needed, making the proposed method work seamlessly with existing sequential linear decompressors. Experimental results obtained for industrial designs demonstrate the effectiveness of the proposed method at reducing TDV in high compression configurations.

The paper presents a novel test data compression scheme. The invention follows from a fundamental observation that in a typical test cube only a small portion of the specified positions are necessary to detect a fault, and most of the remaining ones have many alternatives. The necessary assignments are used to form test templates which both control a decompressor to guarantee the necessary assignments and guide ATPG to find alternative assignments to produce highly compressible test cubes. The proposed approach synergistically elevates compression ratios to values typically unachievable through conventional reseeding-based solutions. It also reduces, in a user-controlled manner, switching rates in scan chains with minimal hardware modification. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

In-field testing of SoC devices is increasingly important to face the dependability requirements of several application domains. Different solutions can be devised and adopted. We summarize the main solutions currently adopted by industry, identify the most critical open issues, and discuss important future trends.

This paper describes the new cell-aware test (CAT) approach, which enables a transistor-level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect rate of manufactured ICs, including FinFET technologies. We present results from a defect-oriented CAT fault model generation for 1,940 standard library cells, as well as the application of CAT to several industrial designs. We present high volume production test results from a 32 nm notebook processor and from a 350 nm automotive design, including the achieved defect rate reduction in defective-parts-per-million. We also present CAT diagnosis and physical failure analysis results from one failing part and give an outlook for using the functionality for quickly ramping up the yield in advanced technology nodes.

Due to a production error, an incorrect figure was used for Fig. 8 on p. 1781 in the above paper (ibid., vol. 32, no. 11, pp. 1776-1786, Nov. 2013). The correct figure is presented here.

In this work we consider ATPG methods tailored to BIST ready designs to improve compression of external tests for such designs. Proposed ATPG reduces external test set sizes and test data volumes by 24% in comparison to that obtained by a state of the art commercial ATPG for BIST ready designs.

This paper describes a new programmable low power test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the existing logic BIST infrastructure. The proposed hybrid scheme efficiently combines test compression with logic BIST, where both techniques can work synergistically to deliver high quality test. Experimental results obtained for industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

The paper discusses practical issues involved in applying scan bandwidth management to large industrial system-on-chip (SoC) designs deploying embedded test data compression. These designs pose significant challenges to the channel bandwidth management methodology itself, flow, and tools. The paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with EDT-based test data compression. Moreover, some recently proposed SoC test scheduling algorithms are refined accordingly by making provision for (1) setting up test configurations minimizing test time, (2) optimization of SoC pin allocation based on scan data volume, and (3) handling physical constraints in realistic applications. Detailed presentation of a case study is illustrated with a variety of experiments that allow one to learn how to tradeoff different architectures and test scheduling.

New methods are proposed to guide line justification and fault propagation in test generation procedures to derive compact test sets. Experiments on several industrial designs yielded, on average, 24% reduction in test set sizes.

Through-silicon vias (TSVs) are crucial elements of 3-D bonded integrated circuits. Since they connect different layers of 3-D stacks, their proper operation is an essential prerequisite for the system function. This paper describes a procedure for deriving fault diagnosis test sequences to identify single and multiple defective TSVs. Additional experimental results obtained for pseudorandom patterns illustrate feasibility and robustness of the proposed test schemes in terms of their detection and diagnostic capabilities and are reported herein.

Devices manufactured in 20 nm and smaller geometry technologies will potentially be very large by today's standards, they will also have new characteristics implied by things like process variability and adoption of FinFET transistors. The industry has cumulatively adopted more and more sophisticated fault models that use timing as well as layout information. There is a growing body of experimental data showing it is still insufficient. The next area of focus will be the quality of test. Cell-aware test is one of the most promising approaches developed over the last five years aimed at improving the quality of test while maintaining the efficiency of gate-level approach. This approach combines two levels of abstraction to provide trade-offs between accuracy and efficiency. The first step creates the cell-aware test library models. It starts with standard cell libraries and performs layout extraction. Realistic defects (bridges and opens) are injected into the SPICE netlist, and analog fault simulation is performed to determine the conditions under which the defects are detected. Those conditions are aggregated to create a compact and efficient representation of the libraries for ATPG done at the gate-level. Generation of library views for cell-aware test is performed only once for a given standard cell library. The final cell-aware ATPG generates the high quality test patterns based on the cell-aware library views. This guarantees that the investment in gate-level ATPG infrastructure could be efficiently utilized. The technology has been used on a number of high-volume industrial designs. The experimental data show a significant increase of defect coverage and the corresponding improvement of defect rate.

This paper presents novel methods of reducing test time and enhancing test compression for system-on-chip (SoC) designs armed with embedded deterministic test (EDT)-based compression logic. The ability of the proposed scheme to improve the encoding efficiency and test compression, while reducing test application time, is accomplished by appropriate selecting and laying out automatic test equipment channel injectors of every single core EDT-based decompressor as well as appropriate bandwidth management of the entire test procedure combined with new control data optimization techniques. The efficacy of the proposed scheme is validated through experiments on several industrial SoC designs and is reported herein.

Test data compression has become a dominant approach to reduce the test cost today. Majority of test compression schemes are based on the fact that the generated test cubes have very few specified bits. This paper studies additional test cube properties and utilizes them to reduce the test data volume (TDV) further. Two approaches are proposed in this paper. The first one requires no additional hardware and the second one is based on the new DFT hardware, named background chains. The proposed approaches can be combined with other test compression schemes to achieve additional TDV reduction. The experimental results based on embedded deterministic test (EDT) show the proposed approaches achieve significant TDV reduction for industrial designs.

This paper presents novel methods of enhancing test compression solutions for SoC designs. The ability of the proposed schemes to improve the encoding efficiency, test compression, and test time is accomplished by either appropriate selecting or laying out ATE channel injectors within EDT-based decompressors. The efficacy of new techniques with respect to test bandwidth management is demonstrated by running experiments on several industrial SoC designs and is reported herein.

The paper presents an extended summary of the PhD thesis that tackles a low power decompression of test cubes in EDT environment and compaction of test responses in the presence of unknown states. The proposed low power decompression schemes allow one to reduce the load and unload switching activity by more than 93% and capture transitions by 52%. The X-masking scheme introduced in the thesis offers up to 48,000 x compression of control data, and eliminates all unknown states from test responses.

This paper describes a new approach for significantly improving overall defect coverage for CMOS-based designs. We present results from a defect-oriented cell-aware (CA) library characterization and pattern-generation flow and its application to 1,900 cells of a 32-nm technology. The CA flow enabled us to detect cell-internal bridges and opens that caused static, gross-delay, and small-delay defects. We present highvolume production test results from a 32-nm notebook processor to which CA test patterns were applied, including the defect rate reduction in PPM that was achieved after testing 800,000 parts. We also present cell-internal diagnosis and physical failure analysis results from one failing part.

This paper describes a low power programmable generator capable of producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared to best-to-date BIST-based PRPGs. We introduce a method to automatically select several controls of the generator allowing easy and precise tuning. The same technique is subsequently employed to deterministically guide the generator toward test sequences with improved fault-coverage-to-pattern-count ratios. Experimental results obtained for industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

This paper presents a new pseudorandom test pattern generator with preselected toggling (PRESTO) activity. It is comprised of a linear finite state machine (a linear feedback shift register or a ring generator) driving an appropriate phase shifter and armed with a number of features that allows this device to produce binary sequences with low toggling (switching) rates while preserving test coverage achievable by the best-to-date conventional BIST-based PRPGs with negligible impact on test application time.

This paper presents preemptive test application schemes for system-on-a-chip (SoC) designs with embedded deterministic test-based compression. The schemes seamlessly combine new test data reduction techniques with test scheduling algorithms and novel test access mechanisms devised for both input and output sides. In particular, they allow cores to interface with automatic test equipment through an optimized number of channels. They are well suited for SoC devices comprising both nonisolated cores, i.e., blocks that occasionally need to be tested simultaneously, and completely wrapped modules. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application schemes and are reported herein.

This paper discusses a low-power test scheme compatible with both test compression and built-in self-test environments. The key contribution is a detailed analysis showing that a simple power-aware controller may allow significant reductions of toggling rates when feeding scan chains with either decompressed test patterns or pseudorandom vectors. While the proposed solution requires minimal modifications of existing DFT logic, its use results in a low switching activity during all phases of scan test: loading, capture, and unloading. It reduces power consumption to or below a level of a functional mode, thus helping to resolve problems related to power dissipation, voltage drop, and increased temperature.

In this paper we examine several embedded low power test schemes that we have proposed over the last few years. These solutions are aimed at reducing the switching activity during all scan-based test operations, particularly including those developed for BIST or deployed to perform on-chip test data compression.

Growing test data volume and excessive test power consumption in at-speed scan testing are both serious concerns for the semiconductor industry. This paper presents a method to simultaneously reduce test data volume and test power in at-speed delay test utilizing clock gating. This is achieved through not clocking a high proportion of scan chains during both scan shift and test response capture. Reducing the number of scan chains shifted during scan load can be expected to permit higher scan shift frequency thus reducing the test time. Reduced test data volume can be expected to permit fewer tester channels for testing which can increase the number of chips tested in parallel. Experimental results for a set of industrial circuits show that the proposed method, on average, reduces test data volume by a factor 2.7, switching activity during scan shift by a factor of 5 and peak switching activity during test response capture by a factor of 2.

This paper presents a new BIST-based fault diagnosis scheme for non-march tests of complexity O(n^2). It can be used to identify failures in embedded memory arrays using galloping pattern tests. The proposed solution employs scalable and flexible logic to record test responses, with no negative impact on at-speed test. It enables recording of responses produced by failures hard to handle by conventional march tests. This, in turn, allows accurate isolation of memory failures during off-line processing.

This paper presents a novel scheme to address the challenge of identifying failing scan cells from production test responses in the presence of scan compression. The scheme is based on a very simple test response compactor employing orthogonal- spatial and time- signatures. The advantage of this scheme as compared to previous work in this field is the simple and incremental nature of the compaction hardware required. The ability of the scheme to accurately identify failing scan cells from compacted responses has been measured on production fail data from five industrial designs and is reported herein.

This paper presents a study addressing the challenge of interfacing automatic test equipment (ATE) with on-chip decompression logic deployed by system-on-chip designs or modular decompression environments. The ability of the proposed scheme to improve the encoding bandwidth by reusing groups of scan chains for test data storage has been measured on industrial designs and is reported herein.

This paper focuses on a new approach to significantly improve the overall defect coverage for CMOS-based designs with the final goal to eliminate any system-level test. This methodology describes the pattern generation flow for detecting cell-internal small-delay defects caused by cell-internal resistive bridges. Results have been evaluated on 1,900 library cells of a 32-nm technology. First production test results are presented from evaluating additional defect detections achieved with different fault models on a 45-nm design.

The paper presents a new channel allocation method for higher Embedded Deterministic Test (EDT) compression in SoC designs comprising isolated cores. It employs a test data reduction technique, which allows cores to interface with ATE through an optimized number of channels. This feature is subsequently used by a new test scheduling and test access mechanisms devised for both the input and output sides. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application scheme and are reported herein.

Growing test data volume and excessive test power consumption in scan testing are both serious concerns for the semiconductor industry. This paper presents a method to simultaneously reduce test data volume and test power utilizing clock gating. This is achieved through not clocking a high proportion of scan chains during both scan shift and test response capture. Reducing the number of scan chains shifted during scan load can be expected to permit higher scan shift frequency thus reducing the test time. Reduced test data volume can be expected to permit fewer tester channels for testing which can increase the number of chips tested in parallel. Experimental results presented for industrial circuits demonstrate that on average a factor of 1.98 and 4 reductions in test data volume and test power, respectively is achievable using the proposed method.

This paper presents a novel scheme to address the challenge of identifying failing scan cells from production test responses in the presence of scan compression. The scheme is based on a very simple test response compactor employing orthogonal—spatial and time—signatures. The advantage of this scheme as compared to previous work in this field is the simple and incremental nature of the compaction hardware required. The ability of the scheme to accurately identify failing scan cells from compacted responses has been measured on production fail data from five industrial designs and is reported herein.

The embedded deterministic test-based compression uses cube merging to reduce a pattern count, the amount of test data, and test time. It gradually expands a test pattern by incorporating compatible test cubes. This paper demonstrates that compression ratios can be order of magnitude higher, if the cube merging continues despite conflicts on certain positions. Our novel solution produces test clusters, each comprising a parent pattern and a number of its derivatives obtained by imposing extra bits on it. In order to load scan chains with patterns that feature original test cubes, only data necessary to recreate parent patterns as well as information regarding locations and values of the corresponding conflicting bits are required. A test controller can then deliver tests by repeatedly applying the same parent pattern, every time using a different control pattern to decide whether a given scan chain receives data from the parent pattern, or another pattern is used instead to recover content of the original test cube. Compression of incompatible test cubes preserves all benefits of continuous flow decompression and offers compression ratios of order 1000× with encoding efficiency much higher than 1.0. We also demonstrate that test clusters make it possible to deliver test patterns in a flexible power-aware fashion. This framework achieves significant reductions in switching activity during scan loading as well as additional test data volume reductions due to encoding algorithms employed to compress parent and control vectors.

This paper presents a built-in self-test (BIST)-based scheme for fault diagnosis that can be used to identify permanent failures in embedded read-only memories. The proposed approach offers a simple test flow and does not require intensive interactions between a BIST controller and a tester. The scheme rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.

Increasing the correlation among adjacent test stimulus bits can significantly reduce shift power consumption. However, it often causes test coverage loss when applying it to reduce the shift power consumption in logic BIST. In this paper, a new adaptive low shift power random test pattern generator (ALP-RTPG) is presented to improve the tradeoff between test coverage loss and shift power reduction in logic BIST. This is achieved by applying the information derived from test responses to dynamically adjust the correlation among adjacent test stimulus bits. When comparing with an existing method, called LT-RTPG, experimental results for industrial designs show that the proposed method can significantly reduce the test coverage loss while still achieving dramatic shift power reduction.

This paper presents a novel scheme to address the challenge of identifying failing scan cells from production test responses in the presence of scan compression. The scheme is based on a very simple test response compactor employing orthogonal - spatial and time - signatures. The advantage of this scheme as compared to previous work in this field is the simple and incremental nature of the compaction hardware required. The ability of the scheme to accurately identify failing scan cells from compacted responses has been measured on production fail data from five industrial designs and is reported herein.

The paper presents a new power-aware test scheme compatible with a newly proposed test compression environment based on deterministic clustering of test cubes with conflicts. The key contribution is a flexible test application framework that achieves significant reductions in switching activity during scan loading by means of a tri-modal test data decompressor.

The paper presents a preemptive test application scheme for system-on-chip (SoC) designs with EDT-based compression. It seamlessly combines a new test data reduction technique with a test scheduling algorithm and a novel test access mechanism. It is particularly well suited for SoC devices comprising non-isolated cores, i.e., blocks that occasionally need to be tested simultaneously.

This paper presents a novel low capture power test scheme integrated with EDT (Embedded Deterministic Test) environment. The key contribution of this paper is to generate test vectors that in capture mode mimic functional operation from switching activity point of view. Experimental results presented for industrial circuits demonstrate the effectiveness of the proposed method.

This paper presents a novel method to generate test vectors that mimic functional operation from switching activity point of view. The method uses states obtained by applying a number of functional clock cycles starting from the scan-in state of a test vector to fill the unspecified scan cell values in test cubes. Experimental results presented for industrial circuits demonstrate the effectiveness of the proposed method.

Unknown (X) states are increasingly often identified as having potential for rendering semiconductor tests useless. One of the key requirements for a reliable test response compactor is, therefore, to preserve observability of any scan cell for a wide range of X-profiles while maintaining very high-compaction ratios, providing ability to detect a variety of failures found in real silicon, and assuring design simplicity. We have proposed a fully X-tolerant test response compaction scheme which is based on a flexible scan chain selection mechanism. This new approach delivers extremely high compression of test results by observing that X states are typically not randomly distributed in test responses. Identical or similar patterns of correlated X states let the proposed scheme reduce the size of a scan chain selector and the amount of test data used to control it. It handles, moreover, a wide range of unknown state profiles such that all X states, including those being clustered and of high density, are suppressed in a per-cycle mode without compromising the test quality.

Embedded memories are increasingly identified as having potential for introducing new yield loss mechanisms at a rate, magnitude, and complexity large enough to demand major changes in fault diagnosis techniques. In particular, time-related or complex read faults that originate in the highest density areas of semiconductor designs require new methods to diagnose more complex faults affecting large groups of memory cells. This paper presents a built-in self-test (BIST)-based fault diagnosis scheme that can be used to identify a variety of failures in embedded random-access memory arrays. The proposed solution employs flexible test logic to record test responses at the system speed with no interruptions of a BIST session. It offers a simple test flow and enables detection of time-related faults. Furthermore, the way test responses are processed allows accurate and time-efficient reconstruction of error bitmaps. The proposed diagnostic algorithms use a number of techniques, including discrete logarithm-based counting with ring generators acting as very fast event counters and signature analyzers. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.

Diagnostic ATPG has traditionally been used to generate test patterns that distinguish pairs of modeled faults. In this work, we investigate the use of n-distinguishing test sets, which distinguish pairs of single stuck-at faults n times, to enhance the probability of distinguishing unmodeled defects. The basis for the use of n-distinguishing test sets to enhance defect diagnosis is similar to that for using n-detection test sets to improve the detection of unmodeled defects. We use a heuristic to target a subset of fault pairs for n-distinguishing in order to improve the efficacy of the patterns generated for aiding diagnosis. Experimental results on the larger ISCAS benchmark circuits are presented to demonstrate the improvements in defect diagnostic resolution due to the use of n-distinguishing test sets. We use randomly selected resistive bridges to represent unmodeled defects. The experimental results also show that the coverage of unmodeled defects by n-distinguishing test sets is similar to that by n-detection test sets even though the number of n-distinguishing tests is typically smaller. This suggests the possibility of using n-distinguishing test sets in place of n-detection test sets in manufacturing test.

This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits. The method creates sets of potentially compatible faults based on necessary assignments. It guides the justification and propagation decisions to create patterns that will accommodate most targeted faults. The technique presented achieves close to minimal test pattern sets for ISCAS circuits. For industrial circuits it achieves much smaller test pattern sets than other methods in designs sensitive to decision order used in ATPG.

The presented compression scheme is a novel solution that is based on deterministic vector clustering and encompasses three data reduction features in one on-chip decoding system. The approach preserves all benefits of continuous flow decompression and offers compression ratios of order 1000x with encoding efficiency much higher than 1.00.

The paper presents a BIST-based scheme for fault diagnosis that can be used to identify permanent and address independent failures in embedded read-only memories. The proposed approach offers a simple test flow and does not require intensive interactions between a BIST controller and a tester. The scheme rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of time-related faults.

The paper presents a new scan chain selection scheme for response compaction. The proposed solution performs selective masking of scan chains and handles a wide range of unknown state profiles, such that all X states can be eliminated in a per-cycle mode while preserving high observability of scan cells that capture errors.

This paper presents a new and comprehensive low-power test scheme compatible with a test compression environment. The key contribution of this paper is a flexible test-application framework that achieves significant reductions in switching activity during all phases of scan test: loading, capture, and unloading. In particular, we introduce a new on-chip continuous-flow decompressor. Its synergistic use with a power-aware scan controller allows a significant reduction of toggling rates when feeding scan chains with decompressed test patterns. While the proposed solution requires minimal modifications of the existing design for test logic, experiments indicate that its use results in a low switching activity which reduces power consumption to or below a level of a functional mode. It resolves problems related to power dissipation, voltage drop, and increased temperature. Our approach integrates seamlessly with test logic synthesis flow, and it does not compromise compression ratios. It fits well into various design paradigms, including modular design flow where blocks come with individual decompressors and compactors.

With feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design timing failures. It is essential that those errors be correctly and quickly diagnosed. In this paper, we analyze the multiple-delay-fault diagnosis problem and propose a novel approach to solve it. We enhance the diagnostic resolution by processing failure logs at various slower-than-nominal clock frequencies. We evaluate the utility ofn-detection and timing-aware automatic-test-pattern-generated (ATPG) sets. Experimental results show that using timing-aware ATPG sets yields better diagnostic resolution and results in better delay-defect-size estimations compared ton-detection ATPG sets. We experimentally determined our diagnosis algorithm's sensitivity to delay variations.

Power consumption during scan-based test becomes a major concern in modern nanometer technologies. Gating the outputs of scan cells can dramatically reduce the scan shift power. In this paper, we utilize the same gating logic at the outputs of scan cells to reduce the capture power consumption. This is achieved by inserting block enable cells (BECs) into the design to dynamically control the gating logic. During capture the BECs enable the gating logic to block the transitions originated from a subset of scan chains or scan segments propagating to combinational logic in order to reduce capture power. The implementation of the proposed method in test compression environment is also discussed. The experimental results on industrial designs show the significant capture power reduction by using proposed techniques.

This paper presents a new and comprehensive power-aware test scheme compatible with a test compression environment. The key contribution of the paper is a flexible test application framework that achieves significant reductions in switching activity during all phases of scan test: scan loading, unloading, and capture.

Interconnect opens are one of major failure mechanisms in contemporary deep sub-micro designs. In this paper, we present three test generation methods, static dominant, dynamic dominant, and double observation, to generate the tests for the interconnect opens. The first two methods take the electrical behavior of the interconnect opens into consideration during test generation and the third method is applied when the parasitic capacitances between the open net and its neighboring nets are not dominant parameter to determine the voltage at the open net. The experimental results show that N-detection stuck-at test set and transition test set are not sufficient to achieve high test coverage on detecting interconnect opens, especially when the voltage at the interconnect open is determined by a large number of neighboring nets. The top-up test patterns generated by using proposed test generation methods help to improve the test quality on detecting interconnect open defects.

The paper presents a BIST-based fault diagnosis scheme that can be used to identify a variety of failures in embedded memory arrays. The proposed solution employs flexible test logic to record test responses at the system speed with no interruptions of a BIST session. It offers a simple test flow and enables detection of time-related faults. Furthermore, the way the test responses are processed allows accurate reconstruction of error bitmaps.

This paper presents a new low-power test scheme integrated with the embedded deterministic test environment. The key contribution of this paper is a flexible test cube encoding scheme, which, in conjunction with a continuous flow decompressor, allows one to significantly reduce toggling rates when test patterns are fed into scan chains. The proposed solution requires neither additional design for testability logic nor modifications to the circuit under test. Experimental results obtained for industrial designs indicate that using this nonintrusive technique reduces switching activity to such extent that the resultant scan-in power consumption is similar to that of the functional mode, thus alleviating problems that are related to average and peak power dissipation, overheating, and risk of reliability degradation. Our approach seamlessly integrates with test logic synthesis flow, and it does not compromise compression ratios. Moreover, it fits well into various design paradigms, including modular design flow where modules come with individual decompressors and compactors.

With feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design-timing failures. It is essential that those errors be correctly and quickly diagnosed. The existing delay-fault diagnosis algorithms cannot identify delay faults that require nonrobust test patterns due to incorrect emulation of the failure analyzer's behavior. We propose a novel approach to performing delay-fault diagnosis for robust and nonrobust tests. We enhance the diagnostic resolution by utilizing passing patterns, processing failure logs at various slower frequencies, and applying n-detection and timing-aware automatic test pattern generation sets. Experimental results show that our approach can diagnose delay faults with good resolution. The algorithm is stable with respect to delay variations that manufactured chips might experience.

This paper presents X-Press - a new two-stage test-response compactor that can be easily integrated with a multiple scan-chain environment. This compactor preserves all benefits of spatial compaction and offers, due to its overdrive sequential section, compression much higher than the ratio of scan chains to compactor outputs. X-Press is also capable of handling a wide range of unknown (X) state profiles by deploying a two-level scan-chain-selection mechanism. In addition to a new compactor architecture, original contributions of this paper include a detailed analysis of two-level error masking caused by X states and a new algorithm to both rank scan chains and then to determine, in per-pattern mode, scan-chain-selection rules used to suppress X states. Experimental results obtained for a variety of designs show feasibility and efficiency of the proposed compaction scheme, altogether with actual impact of X states on a test-pattern count. Finally, diagnostic capabilities of the proposed scheme accompanied by further experimental results are also analyzed.

Timing-aware ATPG [1] has been shown to be an effective method for generating high-quality test sets that detect small delay defects through the longest paths. However, this method usually results in a much higher test pattern count than the traditional transition fault test generation. In this paper, we propose a new criterion that identifies a subset of transition faults to be targeted by the timing-aware ATPG in order to reduce test pattern count while minimizing the impact on the overall delay test quality. The new criterion utilizes the minimal static slack to classify certain transition faults as timing-critical. The test pattern count reduction is achieved by restricting the timing-aware ATPG to targeting the timing-critical transition faults while using traditional transition fault test generation for the remaining transition faults. The experimental results for the industrial circuits show the effectiveness of the proposed method.

Generating test patterns without considering timing exceptions and constraints can lead to invalid test responses, resulting in false failures on the tester or yield loss. A path-oriented approach to handle timing exception paths with setup violations during at-speed test generation has been presented in [1]. This paper presents a unified and complete algorithm for computing test responses in the presence of timing exceptions with both setup and hold violations, and Boolean timing constraints. The new algorithm analyzes all possible effects of glitches in the circuit. It resolves pessimism in the case of multiple interacting timing exception paths. The new method significantly reduces the number of unknowns in the test responses, resulting in improved test coverage and test compression. The new method can be applied to 1) any fault model, 2) any test pattern, 3) any simulation environment, and/or 4) any test generator.

The paper presents a novel low power test scheme integrated with the embedded deterministic test environment. It reduces significantly switching rates in scan chains with minimal hardware modification. Experimental results obtained for industrial circuits clearly indicate that switching activity can be reduced up to 150 times along with improved compression ratios.

A novel statistical learning algorithm is proposed to accurately analyze volume diagnosis results. This algorithm effectively overcomes the inherent ambiguities in logic diagnosis, to produce accurate feature failure probabilities, which are critical in understanding systematic yield limiters. The results of Monte-Carlo simulation are presented, which demonstrate the feasibility and impacts of various factors on this approach. Additional experiments based on injected defects are performed, which confirm the ability of this approach to generate accurate feature failure probabilities for an industrial design using actual diagnosis results.

This paper presents a novel low power test scheme integrated with the embedded deterministic test environment. It reduces switching rates in scan chains with no hardware modification. Experimental results obtained for industrial circuits indicate that switching activity can be reduced up to 23 times.

This paper presents an extensive study on evaluating the effects of static alternative fault models (AFM) on product quality in the face of the latest defect screening techniques. The fault models that are presented in this research are multiple-detect stuck-at, static transition fault, and layout-based deterministic bridges. The results show the quality impact when these new fault models are combined with a high quality stuck-at and TDF test sets

This paper presents new nonadaptive fault-diagnosis techniques for scan-based designs. They guarantee accurate and time-efficient identification of failing scan cells based on results of convolutional compaction of test responses. The essence of the method is to use a branch-and-bound algorithm to narrow the set of scan cells down to certain sites that are most likely to capture faulty signals. This search is guided by a number of heuristics and self-learned information used to accelerate the diagnosis process for the subsequent test patterns. A variety of experimental results for benchmark circuits, industrial designs, and real fail logs confirm the feasibility of the proposed approach even in the presence of unknown states. The scheme remains consistent with a single test session scenario and allows high-volume in-production diagnosis.

In order to generate correct at-speed scan patterns, the effect of timing exceptions and constraints needs to be considered during test generation. A path-oriented approach to handle timing exception paths during at-speed ATPG has been presented in (Vorisek et al., 2006). The new method has been applied to and tested on many example circuits at Semiconductor Technology Academic Research (STARC). This paper presents a sample of these test cases, and illustrates how the proposed method generates correct-by-construction at-speed patterns on these circuits without pessimism

In this paper, a new ATPG methodology is proposed to improve the quality of test sets generated for detecting delay defects. This is achieved by integrating timing information, e.g. from standard delay format (SDF) files, into the ATPG tool. The timing information is used to guide the test generator to detect faults through the longest paths in order to improve the ability to detect small delay detects. To avoid propagating faults through similar paths repeatedly, a weighted random method is proposed to improve the path coverage during test generation. During fault simulation, a new fault-dropping criterion, named dropping based on slack margin (DSM), is proposed to facilitate the trade-off between the test set quality and the test pattern count. The quality of the generated test set is measured by two metrics: delay test coverage and SDQL. The experimental results show that significant test quality improvement is achieved when applying timing-aware ATPG with DSM to industrial designs

In this paper, we propose a test pattern ordering algorithm for fault diagnosis. Test pattern ordering is effective in situations where the fail log is truncated and contains a limited number of fail data. In such cases, higher diagnostic resolution can be achieved with the test set appropriately ordered. Test pattern ordering is independent of the diagnosis algorithm used. The higher resolution achieved by test pattern ordering is obtained at no additional cost once the test patterns have been appropriately ordered. Experimental results on two industrial designs are presented to demonstrate the effectiveness of the proposed method.

The paper presents an efficient method for synthesis of scan chain selection logic. It is capable of acting as a flexible X-control logic for test response compactors. The same circuitry can also be employed to selectively gate scan chains for diagnostic purposes.

This paper introduces a new test response compaction scheme that rests on convolutional compactors. The resultant compression, however, is not limited by the ratio of scan chains to compactor outputs. This enhanced convolutional compactor, similarly to its origin, is capable of handling unknown states and detecting multiple errors. The experimental results demonstrate efficiency of the proposed scheme

Reducing power dissipation during test has been an active area of academic and industrial research for the last few years and numerous low power DFT techniques and test generation procedures have been proposed. Segmented scan [17-20] has been shown to be an effective technique in addressing test power issues in industrial designs [18]. To achieve higher shipped product quality, tests for delay faults are becoming essential components of manufacturing test. This paper demonstrates, for the first time, that segmented scan facilitates increased delay fault coverage without degrading the reduction of the switching activity obtained by segmented scan. The increased transition delay fault coverage is achieved through careful selection of the capture cycle application. Experimental results on larger ISCAS-89 benchmarks show that using three segments, on average, fault coverage using launch off capture can be increased by about 5.4% while simultaneously reducing the peak switching activity caused by capture cycles by over 30%.

This paper discusses the challenges associated with diagnosing chain integrity and system logic failures in the production test environment with limited failure information. The following three methods were proposed to enhance diagnosis resolution in this scenario: (1) static pattern re-ordering (2) dynamic pattern re-ordering (3) per-pin based diagnosis. Experimental results illustrate that per-pin based failure logging and diagnosis algorithms enable scan chain diagnosis in volume production environment. Successful application of per-pin based chain diagnosis is demonstrated with an industrial case

This paper presents a flow for using logic diagnosis to turn production material into vehicles for yield learning. High throughput logic diagnosis is combined with the newly emerging field of design for manufacturing to enable layout aware diagnosis. The ability of the flow to calculate feature failure rates and the application of the failure rates for yield learning is demonstrated through volume data analysis on a production ASIC

With feature sizes shrinking, manufacturing defects and parameter variations often cause design timing failures. Crosstalk coupling is one of such causes. It is essential that timing failures be correctly and quickly diagnosed. The authors present a methodology to diagnose the delay-defect in presence of crosstalk, given the physical information such as crosstalk coupling capacitance, neighborhood information and SDF delay information. The authors provide diagnosis results for 180, 130, 90 and 65 nm technologies

The paper presents a two-stage test response compactor with an overdrive section and scan chain selection logic. The proposed solution is capable of handling a wide range of X state profiles, offers compaction much higher than the ratio of scan chains to compactor outputs, and provides excellent diagnostic resolution

When the response to a test vector is captured by state elements in scan based tests, the switching activity of the circuit may be large resulting in abnormal power dissipation and supply current demand. High supply current may cause excessive supply voltage drops leading to larger gate delays which may cause good chips to fail tests. This paper presents a scalable approach called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests. Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method

In this paper, we investigate the impacts of the untestable defects, modeled by stuck-open faults and bridging faults, on the quality of transition fault test set. The presence of those defects may make some transition faults to be tested invalidly if they are not considered during transition fault test generation. As a result, the chips with delay defects may escape from testing. Two incremental ATPG procedures are proposed to address invalidly tested transition faults. Experimental results show that the quality of the transition fault test set can be maintained with few additional test patterns.

This paper describes a new time compactor built of multiple-input circular registers of relatively prime length. It has excellent ability to detect errors corresponding to real defects such as errors of small multiplicity and burst errors. It operates in modular arithmetic and uses the Chinese remaindering to diagnose scan errors. Given that circular registers do not multiply errors or X values, the compactor is X tolerant.

In this paper we investigate methods to detect delay faults in circuits that use standard scan design. We demonstrate that delay faults at several sites in a circuit cannot be detected using standard launch off capture and launch off shift tests that use two test cycles. However, faults at these sites are detectable using tests that use more than two test cycles. Experimental results on benchmark and industrial circuits that use standard scan design show that substantial numbers of transition delay faults require tests using more than one fault activation cycles to detect them.

This paper presents an enhanced architecture of on-chip pseudorandom test pattern generators, test data decompressors, and test response compactors based on ring generators. The new structure is aimed at improving layout and routing properties while, at the same time, reducing propagation delays introduced by associated phase shifters.

In this paper, we propose a multiple-fault-diagnosis methodology based on the analysis of failing patterns and the structure of diagnosed circuits. We do not consider the multiple-fault behavior explicitly, but rather partition the failing outputs and use an incremental simulation-based technique to diagnose failures one at a time. Our methodology can be further improved by selecting appropriate diagnostic test patterns. The n-detection tests allow us to apply a simple single-fault-based diagnostic algorithm, and yet achieve good diagnosability for multiple faults. Experimental results demonstrate that our technique is highly efficient and effective. It has an approximately linear time complexity with respect to the fault multiplicity and achieves a high diagnostic resolution for multiple faults. Real manufactured industrial chips affected by multiple faults can be diagnosed in minutes of central processing unit (CPU) time.

A new fault model, named propagation delay fault model, is proposed to test the gross gate delay defects modeled at each gate terminal and the distributed delay defects in the fault propagation paths. The proposed fault model assumes that the sum of the gross gate delay defect and the distributed delay defect are large enough to cause timing violation for all the paths passing through the fault site and the fault propagation path. Experimental results demonstrate that high fault coverage can be achieved in a reasonable amount of time and the test set size is comparable to the test set size generated for the transition fault model.

The conference theme of ITC 2005 focuses on evolutionary as well as revolutionary trends in test technology. It states: "Recent advances in areas such as on-chip compression, low-cost test, and data analysis have burst onto the scene and are being rapidly and widely adopted". Indeed, test compression is one of the fastest adopted DFT methodologies. It had been researched for ten years before it was commercially introduced four years ago, and now it has become the mainstream DFT technology. Just a couple of years ago, before on-chip test compression was introduced, it was broadly believed that Logic BIST was going to be the next generation DFT methodology for manufacturing test. There were three main advantages of test compression over Logic BIST that contributed to its rapid adoption: simplicity of the design flow that does not require test points or x-bounding logic, excellent manageable and predictable test quality, and significant reduction of cost of test. Compression of volume of test data and test time by several orders of magnitude combined with on-chip PLLs controlling at-speed capture allow for dramatic reduction of cost of test. Disruptive technology of this magnitude has impact that goes far beyond cost of manufacturing test. Test compression has changed competitive landscape, opened up completely new opportunities in product quality and yield management, and has redefined DFT technology roadmaps. It stimulates research and development activities in new areas that until now were considered not promising or not practical, enables quality of testing that was unachievable until now, accelerates adoption of new fault models that take into account physical data bases and timing information, and changes how fault diagnostics and yield learning are done in manufacturing environment. The presentation will discuss many of these issues, new opportunities, new and not so new challenges, as well as future technology roadmaps.

A method to generate test patterns referred to as defect aware test patterns is proposed. Defect aware test patterns increase the ability to detect unmodeled defects. The proposed method can be used with any test generation procedure to improve the effectiveness of the tests in detecting unmodeled defects. Experimental results on several industrial designs show the effectiveness of defect aware tests. We also propose a measure to estimate the effectiveness of given test sets in detecting unmodeled defects.

A unified gate-level fault model for interconnect opens and bridges is proposed. Defects are modeled as constrained multiple line stuck-at faults. A novel feature of the proposed fault model is its flexibility to accommodate increasing levels of accuracy. Additionally the model does not require accurate device level circuit models to achieve desired accuracy. Efficient methods for fault simulation and test generation are discussed and experimental results on benchmark circuits and industrial designs are presented. The experimental results presented show that the tests generated using simpler versions of the proposed fault model achieve higher defect coverage than the tests using two currently popular methods to derive high defect coverage tests.

This paper describes a fault diagnosis technique for scan-based designs with convolutional test response compaction. The proposed approach allows a time-efficient and accurate identification of failing scan cells using Gauss Jordan elimination method.

In scan based designs, 10%-30% defects are in scan chains. Hence scan chain fault diagnosis becomes an important process for silicon debug and yield ramp up. With embedded compression techniques getting popular, chain diagnosis on devices with the embedded compression techniques becomes a challenge. In this paper, we provide a general methodology that can be applied for performing chain diagnosis in the context of any embedded compression techniques with any existing chain diagnosis algorithms. The proposed methodology enables seamless reuse of the existing chain diagnosis infrastructure with compressed test data. Experimental results show that with compressed patterns, the chain diagnosis resolution can be enhanced up to one order of magnitude with only 25% of failure cycles collected from ATE, compared to the diagnosis results with uncompressed patterns.

The paper presents non-adaptive fault diagnosis techniques for scan-based designs. These schemes guarantee accurate and time-efficient identification of failing scan cells based on results of a convolutional test response compaction in the presence of unknown states

Even though embedded test compression was commercially introduced only four years ago, it has already been broadly adopted as a mainstream DFT methodology. This article discusses the basic criteria for test compression, its strengths and weakness. It also provides the characteristics of EDT (embedded deterministic test) technology

The paper presents a very efficient method for synthesis of convolutional compactors capable of tolerating a number of unknown states in a single time frame while providing very high compaction ratios.

This paper introduces a new class of finite memory compaction schemes called convolutional compactors (CCs). They provide compaction ratios of test responses in excess of 100/spl times/, even for a very small number of outputs. This is combined with the capability to detect multiple errors, handling of unknown states, and the ability to diagnose failing scan cells directly from compacted responses. The CCs can also be used to significantly enhance conventional multiple input signature registers. Experimental results presented in the paper demonstrate the efficiency of convolutional compaction for several industrial circuits.

In modern technologies, process variations can be quite substantial, often causing design timing failures. It is essential that those errors be correctly and quickly diagnosed. Unfortunately, the resolution of the existing delay-fault diagnostic methodologies is still unsatisfactory. In this paper, the feasibility of using the circuit timing information to guide the delay-fault diagnosis is investigated. A novel and efficient diagnostic approach based on the delay window propagation (DWP) is proposed to achieve significantly better diagnostic results than those of an existing delay-fault diagnostic commercial tool. Besides locating the source of the timing errors, for each identified candidate the proposed method determines the most probable delay defect size. The experimental results indicate that the new method diagnoses timing faults with very good resolution.

In scan test environment, designs with embedded compression techniques can achieve dramatic reduction in test data volume and test application time. However, performing fault diagnosis with the reduced test data becomes a challenge. In this paper, we provide a general methodology based on circuit transformation technique that can be applied for performing fault diagnosis in the context of any compression technique. The proposed methodology enables seamless reuse of the existing standard ATPG based diagnosis infrastructure with compressed test data. Experimental results indicate that the diagnostic resolution of devices with embedded compression is comparable with that of devices without embedded compression.

Nanometer technology enables manufacturing of very large SoC designs that have many cores originating from a variety of sources. The challenge here is to integrate different test solutions provided by suppliers of those cores into one comprehensive chip level test. The principal requirement is to reduce the cost of manufacturing test. The DFT methodologies requirement supports high-quality low-cost manufacturing test. The low cost ATE is used for reducing mixed signal test cost. The new fault structures that require detection is done by ATPG engines for test generation and diagnosis.

In modern technologies, process variations can be quite substantial, often causing design timing failures. It is essential that those errors be correctly and quickly diagnosed. In this work, we analyze failures caused by the hold-time-violations. We investigate the feasibility of using circuit-timing information to guide the hold-time-fault diagnosis. We propose a novel and efficient diagnostic approach based on timing window propagation. For each identified candidate, our method locates the source of the hold-time violation and determines the most probable defect size. Experimental results indicate that the new method diagnoses hold-time related defects with very good resolution.

Transition delay fault (TDF) testing has become a necessary test method in very deep sub micron (VDSM) technologies due to the presence of resistive defects that cause subtle timing failures. The transition delay fault model is based on a slow-to-rise and slow-to-fall fault at each node in the circuit. Some resistive defects such as resistive vias actually induce both faults and the TDF test set can contain unnecessary test patterns for proper screening of this type of defect. The inline resistance fault (IRF) model more accurately represents this defect type and is studied in depth in This work. ATPG experimental results show that IRF patterns can be generated 1.4 to 1.8 times faster with 45% to 58% fewer patterns than traditional TDF patterns. IRF and TDF pattern test results are presented and show that the more expensive TDF remains a more comprehensive test than IRF as expected, but that the quality impact of using only the IRF test set is minimal, especially when combined with effective IDDQ outlier screening such as statistical post processing. Additionally, a methodology is presented for the determination of the number of delay defects that behave according to each model from the test data alone, which is necessary to accurately determine delay defect coverage from multiple test coverage metrics.

Growing ASIC design sizes and advanced deep sub-micron technologies require new fault models and more test vectors to meet high test quality goals. To realize these goals within given test resources and cost constraints, new DFT techniques must be used. This paper reports test quality metrics and the test cost of industrial designs for different fault models using three DFT techniques: ATPG for deterministic patterns, Logic BIST for pseudo-random patterns, and EDT for compressed deterministic patterns. It is shown how these techniques can be used to achieve the high quality goals within the test resources currently available for stuck-at tests.

The paper introduces a new non-adaptive fault diagnosis technique for scan-based designs. The proposed scheme guarantees accurate and time-efficient identification of failing scan cells based on results of a convolutional test response compaction.

The paper presents enhanced architectures of pseudo-random test pattern generators and on-chip test data decompressors based on ring generators. The new structures are aimed at improving their layout and routing properties while at the same time reducing propagation delays introduced by associated phase shifters.

This paper presents a novel methodology of designing generators and compactors of test data. The essence of the proposed approach is to use a set of transformations, which alters the structure of the conventional linear feedback shift registers (LFSRs) while preserving the transition function of the original circuits. It is shown that after applying the transition function preserving transformations in a certain order, the resultant circuits feature a significantly reduced the number of levels of XOR logic, minimized internal fanouts, and simplified circuit layout and routing, as compared to previous schemes based on external feedback LFSRs, internal feedback LFSRs, and cellular automata, all implementing the same characteristic polynomial. Consequently, the proposed devices can operate at higher speeds than those of conventional solutions and become highly modular structures.

This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The presented scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG methodology and adopts a very simple flow. It is nonintrusive as it does not require any modifications to the core logic such as the insertion of test points or logic bounding unknown states. The EDT scheme consists of logic embedded on a chip and a new deterministic test-pattern generation technique. The main contributions of the paper are test-stimuli compression schemes that allow us to deliver test data to the on-chip continuous-flow decompressor. In particular, it can be done by repeating certain patterns at the rates, which are adjusted to the requirements of the test cubes. Experimental results show that for industrial circuits with test cubes with very low fill rates, ranging from 3% to 0.2%, these schemes result in compression ratios of 30 to 500 times. A comprehensive analysis of the encoding efficiency of the proposed compression schemes is also provided.

We examine various forms of embedded deterministic test with particular emphasis on input stimuli compression and test response compaction schemes. Subsequently, the embedded deterministic test (EOT) scheme, which significantly reduces manufacturing test cost by providing a dramatic reduction in scan test data volume and scan test time, is discussed.

We study the relationship between multiple fault diagnosability and fault detection count. Instead of developing a complex diagnostic algorithm for multiple fault behavior, we change the test sets used in test and diagnosis. This allows us to apply a simple single-fault based diagnostic algorithm, and yet achieve very good diagnosability for the failure test cases caused by multiple faults. We have verified experimentally the effectiveness of n-detection tests for multiple-fault cases and explained the results in probabilistic terms.

This paper presents the impact of multiple-detect test patterns on outgoing product quality. It introduces an ATPG tool that generates multiple-detect test patterns while maximizing the coverage of node-to-node bridging defects. Volume data obtained by testing a production ASIC with these new multiple-detect patterns shows increased defect screening capability and very good agreement with the bridging coverage estimated by the ATPG tool. 1.

This paper introduces a finite memory compactor called convolutional compactor that provides compaction ratios of test responses in excess of 100x even for a very small number of outputs. This is combined with the capability to detect multiple errors, handling of unknown states, and the ability to diagnose failing scan cells directly from compacted responses. A convolutional compactor can be easily configured into a MISR that preserves most of these properties. Experimental results demonstrate the efficiency of compaction for several industrial circuits.

In this paper, we analyze failing circuits and propose a multiple-fault diagnosis approach. Our methodology has been validated experimentally and has proved to be highly efficient and effective in diagnosing multiple faults. We do not consider the multiple-fault behavior explicitly, but rather use an incremental simulation-based approach to diagnose failures one at a time. Furthermore, to improve the diagnosability, we propose a failing-primary-output partitioning algorithm. Experimental results show that our approach has approximately linear time complexity, and it achieves high diagnosability and resolution. Our approach has also been validated on data collected from manufactured chips. The diagnosis time is within minutes for real industrial chips that failed because of multiple faults. 1.

This paper presents a new highly modular architecture of generators and compactors of test patterns. This structure has fewer levels of logic, smaller fan-out, reduced area, and operates at faster speed than external feedback LFSRs, internal feedback LFSRs, and cellular automata, all implementing the same characteristic polynomial.

When a design is manufactured for the first time, it may suffer from timing-related errors that result from inaccuracies in the timing analysi tool used during the design process. Such errors will appear as delay faults in all (or many) of the manufactured chips. In addition, variations that occur during the manufacturing process may cause delay defects that vary across chips. It is necessary to diagnose and correct failures of the first type (in the presence of failures of the second. type) before the chip can be manufactured again. This may have to be repeated until design errors are eliminated. Experiments that enable one to find common fault responses of faulty circuits are described.

This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic decision ordering, conflict driven recursive learning and conflict learning. An important feature shared by all these techniques is that they are triggered by the occurrence of a conflict in the generation of tests. Hence, they are not active all the time nor for all the faults. This feature allows the ATPG system that uses these techniques to resolve hard-to-resolve faults with far fewer backtracks and leaves the system as efficient as before in the absence of conflicts. We have incorporated these techniques into a commercial D-algorithm based ATPG tool. The experimental results on full scan versions of ITC'99 benchmark circuits demonstrate an improvement of the ATPG system both in the number of aborted faults and in test generation time.

This paper introduces embedded deterministic test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented.

Test automation has been a cornerstone of the manufacturing test industry, much as electronic design automation has been to the semiconductor industry. Thus, it is fair to say that test automation providers will have a significant role to play in addressing the challenges involved in testing system-chips of the future. This session contains presentations that examine the test challenges presented by system-level integration, from the perspective of the providers of test tools and methodologies. The presenters will highlight innovations that will lead to improved test flows, addressing critical issues such as testing cost, test application time, and reuse of test hardware for silicon debug.

The semiconductor industry is capable of building "tester-limited fabs" and definitely needs a more cost-effective solution for the cost of test problem than the one we have today. The solutions are likely, to come from several different sources. While the ATE industry is addressing the cost of test problem by designing new DFT testers, it is the EDA industry that holds the key to providing an embedded test solution that guarantees high-quality, low cost manufacturing test. In this presentation we examine various DFT technologies and their ability to provide high quality low cost manufacturing test.

This paper introduces a method that enables the diagnosis of embedded memories via test response compression and automatic bitmap recognition. The proposed method has been tested via simulation with various memory specifications, fail patterns and test algorithms; it has also been implemented in a 0.18 /spl mu/m CMOS test chip.

A static compaction procedure to reduce test set size for scan designs and a procedure to order test patterns in order to steepen the fault coverage curve are presented. The computational effort for both procedures is linearly proportional to the computational effort required for standard fault simulation with fault dropping. Experimental results on large industrial circuits demonstrate both the efficiency and effectiveness of the proposed procedures.

This paper introduces a method that enables failure diagnosis of BISTed memories by compression of test responses. This method has been tested by simulation of memories with various specifications, fail patterns and test algorithms. The proposed method has been implemented in 0.18 /spl mu/ CMOS IC.

This paper presents a new pseudoexhaustive test methodology for digital finite impulse response (FIR) filters. The proposed scheme can be employed to detect any combinational faults within the basic cell of the functional units occurring in linear phase comb filters, trees of sign-extended adders and phase-shift multipliers. It uses additive generators as a source of pseudoexhaustive patterns to systematically test all FIR filter building blocks.

The effect of crosstalk errors is most significant in high-performance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that we have developed to enable on-chip at-speed testing of crosstalk defects in System-on-Chip interconnects. The self-test methodology is based on the Maximal Aggressor Fault Model [13], that enables testing of the interconnect with a linear number of test patterns. To enable self-testing of the interconnects, we have designed efficient on-chip test generators and error detectors to be embedded in necessary cores; while the test generators generate test vectors for crosstalk faults, the error detectors analyze the transmission of the test sequences received from the interconnects, and detect any transmission errors. We have also designed test controllers to initiate and manage test transactions by activating the appropriate test generators and error detectors, and having error diagnosis capability. We have developed, simulated, and synthesized parameterized HDL models of the self-test structures. We have applied the self-test methodology to test crosstalk defects in the buses of a DSP chip. Using a new high-level crosstalk simulation technique, we have validated the self-test methodology, including the self-test structures inserted in the DSP chip.

A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors applied when the circuit operates as a sequential circuit, without using scan. These sequences can be applied at-speed, i.e., at the normal circuit clock speed. The objectives set for choosing the lengths of the functional sequences are to increase the number of vectors applied at-speed, and to reduce the number of settings of functional sequence lengths, without compromising the fault coverage achieved. The experimental results presented demonstrate that compared to earlier methods, the proposed method achieves the above objectives while also achieving higher fault coverages for most of the benchmark circuits considered.

The probability of obtaining desired test patterns in subsequences generated by two-dimensional test pattern generators is examined. Various architectures of generators comprising of linear feedback shift registers, cellular automata and associated phase shifters are thoroughly investigated. Two new algorithms that can be employed to synthesize phase shifters minimizing linear dependencies and assuring highly balanced usage of all generator stages are also introduced.

The paper presents a novel, comprehensive and systematic methodology, which can be used to automate synthesis of cellular automata-based test pattern generators with phase shifters. First, a very fast and simple simulation framework is proposed to either verify or generate maximum-length linear finite state machines such as cellular automata or linear feedback shift registers. Subsequently, a new framework is presented for efficient selection of phase shifters that satisfy criteria of channel separation and circuit complexity. As shown in the paper, it is possible to synthesize, in a time-efficient manner, very large cellular automata and their corresponding fast phase shifters for built-in self-test applications with guaranteed structural and functional properties.

This paper presents novel systematic design techniques for the automated register transfer level synthesis of phase shifters-circuits used to remove effects of structural dependencies featured by pseudorandom test pattern generators driving parallel scan chains. Using a concept of linear feedback shift register (LFSR) duality this paper relates the logical states of LFSRs and circuits spacing their inputs to each of the output channels. Consequently, the method generates a phase-shifter network satisfying criteria of channel separation and circuit complexity by taking advantage of simple logic simulation of the LFSRs. It is shown that it is possible to synthesize in a time-efficient manner very large and fast phase shifters for built-in self-test applications with guaranteed minimum phaseshifts between scan chains, and very low delay and area of virtually one two-way XOR gate/channel.

In this paper, we introduce a hierarchical test set structure called star test, derived from the experimental observation of the fault clustering phenomena. Based on the concept of star test, two applications are studied: one applied to built-in-self-test (BIST); the other to automatic test pattern generation (ATPG). First, a very high quality and low-cost BIST scheme, named STAR-BIST is proposed. Experimental results have demonstrated that a very high fault coverage can be obtained without any modification of the logic under test, no test data to store and very simple BIST hardware which does not depend on the size of the circuit. Second, an efficient test generator, named STAR-ATPG, is developed which speeds up the ATPG performance by a factor of up to five for large industrial circuits.

This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200 K to 800 K gates, pose significant challenges to logic BIST methodology, flow, and tools. The paper presents the process of generating a BIST-compliant core along with the logic BIST controller for at-speed testing. Comparative data on fault grades and area overhead between automatic test pattern generation (ATPG) and logic BIST are reported. The experimental results demonstrate that with automation of the proposed solutions, logic BIST can achieve test quality approaching that of ATPG with minimal area overhead and few changes to the design flow.

The paper presents novel algorithms for the automated synthesis of cellular automata-based test generators with phase shifters. As shown in the paper, it is possible to synthesize in time-efficient manner very large cellular automata and their corresponding fast phase shifters for BIST applications with guaranteed structural and functional properties.

Star test is a novel test pattern generation technique in which a few test vectors serve as centers of clusters for other test vectors which are derived by complementing at random their coordinates. By properly selecting the deterministic patterns as centers, the star tests have very high probability to detect most of the faults in a circuit. This paper presents an efficient algorithm to combine the star test approach with a traditional test pattern generator yielding a significant speed up of the ATPG process. With the new STAR-ATPG methodology, the major effort of the test generation is transferred from an computationally more complex test pattern generation process into simpler fault simulation. Experimental results on several large industrial designs demonstrate that a factor of 1.5-2.5 average speed up is achieved by the new method with the same abort limit. Also, STAR-ATPG achieves higher fault coverage than traditional ATPG under the same abort limit. To achieve the same fault coverage as STAR-ATPG, it requires the traditional method to increase the abort limit significantly and result in 5 times slower.

The paper presents a comparative study of randomness properties of patterns generated by one-dimensional linear hybrid cellular automata (LHCA) and linear feedback shift registers (LFSRs) with phase shifters on their outputs. It is shown that properly synthesized phase shifters allow LFSRs to match performance of the LHCAs as pseudo-random pattern generators (PRPGs), in marked contrast to several suggestions that LHCAs can outperform LFSRs in variety of testing applications.

The paper presents a new fault diagnosis technique for scan-based designs with BIST. It can be used for nonadaptive identification of the scan cells that are driven by erroneous signals. The proposed scheme employs a pseudorandom scan cell selection routine which, in conjunction with a conventional signature analysis and simple reasoning procedure, allows flexible trade-offs between the test application time and the diagnostic resolution.

This paper presents an efficient and novel method for sequential learning of implications, invalid states, and tied gates. It can handle real industrial circuits, with multiple clock domains and partial set/reset. The application of this method to improve the efficiency of sequential ATPG is also demonstrated by achieving higher fault coverages and lower test generation times.

The paper presents a new modular logic BIST architecture for intellectual property (IF) cores and block-oriented design methodology. The scheme involves two-step development process: design and analysis of BIST-ready IP cores and system integration. A BIST-ready core has inserted scan chains, test points, a repeater with phase shifter to perform serial to parallel conversion of test vectors, and a space-time test-response compactor. It is also simulated to determine its fault coverage and signature for a specified configuration of BIST hardware. Particulars of a method to compute the composite signature for the whole design based on signatures representing individual cores are presented altogether with a new technique to expand test vectors. At the system ASIC level, the paper demonstrates how multiple cores can be seamlessly integrated and then tested in exactly the same manner as they were analyzed by sharing the same BIST controller.

The paper introduces a new algorithm for the automated synthesis of phase shifters-circuits used to remove effects of structural dependencies featured by two-dimensional test generators. The algorithms presented in the paper synthesize in a time-efficient manner very large and fast phase shifters for built in self-test environment, with guaranteed minimal phase shifts between scan chains, and very low delay and area of virtually one 2-way XOR gate per channel.

The paper presents novel systematic design techniques for the automated synthesis of phase shifter circuits used to remove effects of structural dependencies featured by test generators driving parallel scan chains. As shown in the paper, it is possible to synthesize very large and fast phase shifters for BIST applications with guaranteed phaseshifts between scan chains and very small number of gates per channel.

The paper presents an efficient scheme to compress and decompress in parallel deterministic test patterns for circuits with multiple scan chains. It employs a boundary-scan-based environment for high quality testing with flexible trade-offs between test data volume and test application time while achieving a complete fault coverage for any fault model for which test cubes are obtainable. It also reduces bandwidth requirements, as all test cube transfers involve compressed data. The test patterns are generated by the reseeding of a two-dimensional hardware structure which is comprised of a linear feedback shift register (LFSR), a network of exclusive-or (XOR) gates used to scramble the bits of test vectors, and extra feedbacks which allow including internal scan flip-flops into the decompressor structure to minimize the area overhead. The test data decompressor operates in two modes: pseudorandom and deterministic. In the first mode, the pseudorandom pattern generator (PRPG) is used purely as a generator of test vectors. In the latter case, variable-length seeds are serially scanned through the boundary-scan interface into the PRPG and parts of internal scan chains and, subsequently, a decompression is performed in parallel by means of the PRPG and selected scan flip-flops interconnected to form the decompression device. Extensive experiments with the largest ISCAS' 89 benchmarks show that the proposed technique greatly reduces the amount of test data in a cost effective manner.

This paper presents a new scan-based BIST schemewhich achieves very high fault coverage without the deficienciesof previously proposed schemes. This approach utilizes scan orderand polarity in scan synthesis, effectively converting the scanchain into a ROM capable of storing some "center" patterns fromwhich the other vectors are derived by randomly complementingsome of their coordinates. Experimental results demonstrate that avery high fault coverage can be obtained without any modificationof the mission logic, no test data to store and very simple BISThardware which does not depend on the size of the circuit.

This paper presents a new pseudo-exhaustive test methodology for digital finite impulse response (FIR) filters. The proposed scheme can be employed in a built-in self-test (BIST) environment to detect any combinational faults occurring in linear phase comb filters, trees of sign-extended adders and phase-shift multipliers. It uses additive generators as a source of pseudo-exhaustive patterns to test systematically all FIR filter building blocks.

The paper presents a new fault diagnosis technique for scan-based BIST designs. It can be used for non-adaptive identification of the scan cells that are driven by erroneous signals, irrespective of the error multiplicity. The proposed scheme employs a simple scan cell selection hardware which in conjunction with a conventional signature analysis allows flexible tradeoffs between the test application time and the diagnostic resolution.

This paper presents an improved scan-based BIST scheme which achieves very high fault coverage without any modification of the mission logic, i.e. no test point insertion, no test data to store and very simple BIST hardware which does not depend on the size of the circuit. The approach utilizes scan order and its polarity in scan synthesis, effectively converting it into a ROM encoding a few test vectors which serve as centers of clusters from which the other vectors are derived by complementing at random their coordinates. The proposed method successfully tests the random pattern resistant faults, which is the major problem of traditional LFSR-based BIST, with lower hardware cost and a more efficient algorithm than previous methods. Experimental results demonstrate that a very high fault coverage can be achieved with much smaller test set than other pseudorandom pattern generation methods published so far.

The usage of multipliers in fixed-width data-dominated architectures (also termed data paths) poses serious testability problems. Due to truncation of their outputs, the fault observability of the multipliers degrades, and the resulting output patterns are inadequate to completely test functional blocks that are driven by them. Consequently, the overall random pattern testability of data paths deteriorates substantially. In this paper, we propose new generic design schemes, based on residue number system arithmetic, to improve the overall testability of data paths. The approach uses, in the test mode, the truncated least significant bits of the product to increase the variety of patterns at the output of a multiplier. This, in turn, improves the fault detectability of multipliers, and consequently, have a remarkable impact on the overall testability of data paths. The proposed techniques can be incorporated with a minimal performance degradation and area overhead, and are independent of the multiplier architecture. Experimental analysis performed on four high-level synthesis benchmarks exhibits a significant improvement in the overall testability of the corresponding data-path implementations.

Recently, it has been shown that retiming has a very strong impact on the run time required for sequential, structural automatic test pattern generators (ATPG's), as well as the levels of fault coverage and fault efficiency attained. In this paper, we show that, for circuits with no hardware reset or a global reset state, retiming preserves testability with respect to a single stuck-at fault test set by adding a prefix sequence of a predetermined number of arbitrary input vectors. We show that this result holds for test sets derived based on structural and functional methods, and based on the conventional and multiple observation time testing strategies. Furthermore, we derive the conditions under which synchronizing sequences are preserved under retiming. We show that a structural synchronizing sequence for a circuit drives any of its corresponding retimed circuits to an equivalent state. In addition, we show that functional synchronizing sequences are preserved under retiming by adding a prefix sequence of a predetermined number of arbitrary input vectors. The impact of retiming on ATPG complexity and test-set preservation under retiming suggest a new approach for enhancing the performance of structural, sequential ATPG's. Experimental results show that high fault coverages can be achieved on high-performance circuits optimized by retiming with much less CPU time (a reduction of two orders of magnitude in several instances) than if ATPG is attempted directly on those circuits.

A new built-in self-test (BIST) methodology is presented in which all generation and compaction functions are executed by basic building blocks such as adders, ALU's, and multipliers, performing regular arithmetic functions in digital signal processing (DSP) cores. It is demonstrated how these components are themselves tested, and subsequently used to perform more complex testing functions. The need for extra hardware is either entirely eliminated or drastically reduced, test vectors can be easily distributed to different modules of the system, test responses can be collected in parallel, and there is virtually no performance degradation. As an integral part of the proposed BIST environment, arithmetic two-dimensional (2-D) generators of pseudorandom test vectors are also introduced to further integrate the scheme with parallel scan and boundary scan designs used to test peripheral devices of the core.

This paper presents a novel test point insertion technique which, unlike the previous ones, is based on a constructive methodology. A divide and conquer approach is used to partition the entire test into multiple phases. In each phase a group of test points targeting a specific set of faults is selected. Control points within a particular phase are enabled by fixed values, resulting in a simple and natural sharing of the logic driving them. Experimental results demonstrate that complete or near-complete stuck-at fault coverage can be achieved by the proposed technique with the insertion of a few test points and a minimum number of phases.

This paper presents a new effective scheme to decompress in parallel deterministic test patterns for circuits with multiple scan chains. Two implementations of the scheme are discussed. In the first one, the patterns are generated by the reseeding of a hardware structure which is mostly comprised of the already existing DFT environment. In the second approach, the patterns are generated through the execution of a program on a simple embedded processor. Extensive experiments with the largest ISCAS'89 benchmarks show that the proposed technique greatly reduces the amount of test data with low cost. Efficient automatic test pattern generation algorithms are also presented to enhance the efficiency of the proposed approach.

Introduced is a self-driven test point structure which permits at-speed, on-chip, non-scan, sequential testing using parallel pseudorandom test patterns applied only to the primary inputs of the circuit under test. The test network is unique in that aside from a test mode flag, all I/O signals needed for test system operation are tapped from within the circuit itself. High single stuck-at fault coverage is achieved for a number of ISCAS-89 benchmarks.

Existing built-in self-test (BIST) strategies require the use of specialized test pattern generation hardware which introduces significant area overhead and performance degradation. In this paper, we propose an entirely new approach to generate test patterns. The method is based on adders widely available in data-path architectures used in digital signal processing circuits and general purpose processors. The resultant test patterns, generated by continuously accumulating a constant value, provide a complete state coverage on subspaces of contiguous bits. This new test generation scheme, along with the recently introduced accumulator-based compaction scheme (Rajski and Tyszer, 1993) facilitates a BIST strategy for high performance datapath architectures that uses the functionality of existing hardware, is entirely integrated with the circuit under test, and results in at-speed testing with no performance degradation and no area overhead.

The probability of linear dependency in subsequences generated by linear feedback shift registers is examined. It is shown that this probability for a short subsequence, e.g., a sequence defined by the length of a scan chain, can be much higher than that for an entire m-sequence.

The research reported in this paper has been conducted to identify those attributes, of both sequential circuits and structural, sequential automatic test pattern generation algorithms, which can lead to extremely long test generation times. The retiming transformation is used to create families of circuits which have the same sequential depth and number and length of cycles, but a significantly different percentage of valid states. It was observed for three different sequential test pattern generators that the increase in complexity of test pattern generation is related to a new circuit attribute, termed density of encoding, and not to the sequential depth or number and length of cycles-i.e., those circuit parameters to which the complexity of test pattern generation has traditionally been attributed.

Abstract| Recently, it has been shown that retiming has a very strong impact on the run time of sequential, structural automatic test pattern generators (ATPGs), as well as the levels of fault coverage and fault eciency attained.In this paper, we show that retiming preserves testability with respect to a single stuck-at fault test set by adding a pre x sequence of a pre-determined number of arbitrary input vectors.Experimental results show that high fault coverages can be achieved on high performance circuits optimized by retiming with a much less CPU time (a reduction of two orders of magnitude in several instances) than if ATPG is attempted directly on those circuits.

This paper demonstrates how fault simulation of building blocks found in data-path architectures can be performed extremely efficiently and accurately by taking advantage of their simple functional models and structural regularity.This technique can be used to accelerate the simulation of those blocks in virtually any fault simulation environment, resulting in fault simulation algorithms that can perform fault grading in a very demanding BIST environment.

The usage of multipliers in the increasingly demanding fixed-width data path architectures poses serious testability problems. Their truncated outputs not only degrade the fault observability, but the output responses of multipliers are inadequate to completely test functional blocks that are driven by them. In this paper, we propose a new design for testability scheme to improve the overall testability of data paths. The methodology takes into account the truncated least significant bits of the product in the test mode to increase the variety of patterns at the output of a multiplier. The proposed techniques are part of the Arithmetic Built-in Self Test methodology and can be incorporated with a minimal performance degradation and area overhead.

A novel highly efficient fault simulation technique targeted for circuits produced through high-level synthesis is presented. The technique combines hierarchical and functional fault simulation of commonly used building blocks that have regular structures. Comparison with gate-level simulation demonstrates the advantage of using this technique for this class of circuits.

In this paper, we propose an entirely new Built-in Self Test scheme for high-level synthesis of data path architectures that makes use of the arithmetic blocks in the data path to generate test vectors and compact test responses. The paper employs state coverage to evaluate testability in an abstract level, and subsequently, use it to guide the synthesis of testable circuits.

A methodology for evaluating the fault coverage of RAM test algorithms is proposed and the architecture of a flexible software analysis program is described. The analysis, performed for arbitrary test sequences, provides a comprehensive set of coverage statistics for functional cell-array faults. An overview of the analysis capabilities of the program is given, the fault state transition conditions for several representative fault classes are specified, and coverage analyses results for a variety of test algorithms are presented.

This paper presents a new and efficient scheme to decompress a set of deterministic test vectors for circuits with scan. The scheme is based on the reseeding of a Multiple Polynomial Linear Feedback Shift Register (MP-LFSR) but uses variable-length seeds to improve the encoding efficiency of test vectors with a wide variation in their number of specified bits. The paper analyzes the effectiveness of this novel approach both theoretically and through extensive experiments. A modular design of the decompression hardware re-uses the same LFSR used for pseudo-random vector generation and scan registers to minimize the area overhead.

We propose a new scheme for built-in test (BIT) that uses multiple-polynomial linear feedback shift registers (MP-LFSR's). The same MP-LFSR that generates random patterns to cover easy to test faults is loaded with seeds to generate deterministic vectors for difficult to test faults. The seeds are obtained by solving systems of linear equations involving the seed variables for the positions where the test cubes have specified values. We demonstrate that MP-LFSR's produce sequences with significantly reduced probability of linear dependence compared to single polynomial LFSR's. We present a general method to determine the probability of encoding as a function of the number of specified bits in the test cube, the length of the LFSR and the number of polynomials. Theoretical analysis and experiments show that the probability of encoding a test cube with s specified bits in an s-stage LFSR with 16 polynomials is 1-10/sup -6/. We then present the new BIT scheme that allows for an efficient encoding of the entire test set. Here the seeds are grouped according to the polynomial they use and an implicit polynomial identification reduces the number of extra bits per seed to one bit. The paper also shows methods of processing the entire test set consisting of test cubes with varied number of specified bits. Experimental results show the tradeoffs between test data storage and test application time while maintaining complete fault coverage.>

In this paper, we study the testability preservation of the concurrent decomposition and factorization transformations under several delay-fault testing constraints. We show that all transformations, except dual extraction of multiplexor structures, preserve testability with respect to a general Robust Path-Delay-Fault (RPDF) test set, Validatable Nonrobust (VNR) delay-fault test set, and Delay Verification (DV) test set. In addition, we provide new, sufficient conditions for the algebraic resubstitution with complement transformation to preserve RPDF, VNR, and DV testability, that cover a larger class of complementary expressions than was known previously. Experimental results on a set of Berkeley PLA's and MCNC benchmark circuits show that dual extraction of multiplexor structures is utilized in only 2 out of 50 benchmark circuits. We demonstrate that while disabling this transformation has negligible effect on area, it results in an efficient test-set preserving multilevel logic synthesis algorithm, that preserves testability with respect to RPDF, VNR, and DV test sets.>

Recently, a new, very efficient method of multilevel logic synthesis based on factorization and decomposition of Boolean expressions has been introduced. It has been shown that the transformations used by this method preserve the single stuck-at testability of two-level circuits. This paper shows that single-cube extraction, double-cube extraction, and dual-extraction of double-cubes/spl isin/D/sub 1,1,2/ and D/sub 2,2,2/ preserve testability with respect to a general robust path-delay-fault (RPDF) test set. However, the authors show that while dual-extraction of double-cubes/spl isin/D/sub 2,2,3/ preserves RPDF testability of paths through the extracted divisors with respect to a single-input-changing test set, it does not guarantee RPDF testability preservation of unmodified paths. Furthermore, the authors provide sufficient conditions for algebraic resubstitution with complement to preserve RPDF testability that cover a larger class of complementary expressions than was known previously. The testability preservation of these transformations is demonstrated on a set of RPDF testable Berkeley PLAs.>

Necessary, nonconflicting, and arbitrary assignments can be distinguished during algorithmic test pattern generation. The identification of necessary and nonconflicting assignments is algorithmic in the sense that there is no element of choice or luck in the computation, no reliance on heuristics, and no possibility of these assignments causing a backtrack if the fault is testable. This paper presents algorithms based on the mathematical properties of images and inverse images of set functions to define reduction and tendency lists in combinational logic circuits, used to identify necessary and nonconflicting assignments, respectively. Issues relating to the efficient implementation of these algorithms are addressed from both a theoretical and practical perspective. Experimental results obtained on a variety of benchmark circuits show that algorithmic assignment identification can be used to reduce or eliminate backtracking in automatic test pattern generation.>

An accumulator-based compaction (ABC) scheme for parallel compaction of test responses is introduced. The asymptotic and transient coverage drop introduced by accumulators with binary and 1's complement adders is studied using Markov chain models. It is proven that the asymptotic coverage drop in ABC with binary adders is 2/sup -k/, where k is the number of bits in the adder that the fault can reach. In ABC with 1's complement adders, the asymptotic coverage drop for a fairly general class of faults is (2n-1)/sup -1/, where n is the total number of bits. The analysis of transient behavior relates the coverage drop with the probability of fault injection, the size of the accumulator, and the length of the test experiment. The process is characterized by damping factors derived for various values of these parameters.>

A recursive technique for generating exhaustive patterns is presented. The method is optimal, i.e., in one experiment it covers exhaustively every block of k adjacent inputs in the first 2/sup k/ vectors. Implementation methods based on characteristic functions of test vectors are provided. They include a parallel pattern generator employing an exclusive-or array, and two serial generators that can be easily adopted in a scan-based built-in self-test environment.>

Efficient strategies to perform selectively fault-free simulation, critical path tracing in fanout-free regions, and fault simulation of stem faults in a parallel pattern evaluation environment are presented and analyzed in an implementation-independent manner. The dynamic changes in the complexity of the fault simulation components as the fault simulation progresses and faults are detected are shown to be extremely significant. In particular, fault-free simulation tends quickly to become more expensive than both the critical path tracing within fanout-free regions and the explicit simulation of stem faults. In addition, the presence of redundant faults is shown to have an inhibiting effect on the reduction of the fault simulation complexity.>

An accumulator-based compaction (ABC) scheme for parallel compaction of test responses is presented. In this scheme an accumulator with an n-bit binary adder is slightly modified such that the quality of compaction defined by the asymptotic coverage drop is similar to that offered by shift registers with irreducible polynomials of cellular automata. A Markov-chain model is used to analyze both the asymptotic coverage drop introduced by this scheme, and its transient behavior. It is shown that the asymptotic coverage drop depends both on the size of the accumulator and the probability of a fault injection. The upper bound of the coverage drop during the transition phrase is also provided. The proposed scheme is compatible with the width of the data path, and the test can be applied at the normal mode speed. The minimal hardware overhead involves only one-bit register to implement the feedback between the carry-out and carry-in lines.>

The primary consideration in the entire logic synthesis process is the quality of the resulting circuit measured by its speed, chip area, and recently also testability. The crucial phase in automatic logic synthesis, where all these parameters are determined, is the process of decomposition and factorization which generates multilevel Boolean equations for the synthesized circuit. There are a number of various aspects of testability. These aspects depend on the fault models and testing strategies used. One of the basic objectives is to synthesize circuits that are completely testable for a given class of faults.>

The issues of printed circuit board (PCB) interconnect testing are addressed in the context of boundary-scan architecture. Boundary-scan architecture is treated here as the framework for a PCB level built-in self-test (BIST). A novel BIST method is developed which utilizes various features of the architecture. Boundary-scan architecture is shown to have the capability to generate time-efficient test vector sets. Response compaction within the boundary-scan chain is introduced to reduce shift out time as well as to simplify detection and diagnosis. However, the proposed BIST schemes require some extensions of the standard boundary-scan cells, and the schemes can work only if every boundary-scan cell of every IC on the PCB has the proposed extensions.>

The authors present a concurrent method for the decomposition and factorization of Boolean expressions. The method uses only two-literal single-cube divisors and double-cube divisors considered concurrently with their complements. The authors demonstrate that these objects, despite their simplicity, provide a very good framework on which to reason about common algebraic divisors and the duality relations between expressions. The simplicity of these objects makes it possible to compute the cost function associated with them accurately and dynamically. Hence, the method is entirely greedy, and in each iteration it extracts the best expression along with its complement. The decomposition is based on testability-preserving transformations, and the synthesized multilevel network is fully tested by a complete test derived for the original circuit. The algorithm has been implemented and excellent results on several benchmark circuits illustrate its efficiency and effectiveness.>

The application of the novel concept of correlated random patterns to the testing of fully testable synthesized multi-level circuits is presented.The concept represents an alternative to weighted random pattern testing.Reductions in a circuit's random pattern test length are achieved by taking advantage of correlations measured between values applied at different input positions in a complete deterministic test.Experimental results show that correlated random patterns can achieve 100% fault coverage of synthesized circuits using orders of magnitude less patterns than when equiprobable random patterns are used.

The authors study the relation between the length of the linear feedback shift register (LFSR), the size of the circuit (which defines the size of the fault list), and the quality of diagnostic resolution. They present an analytical model that is used to obtain a simple formula determining the fraction of faults that are uniquely diagnosed for a given circuit size and the LFSR length. The model is verified through extensive experiments on benchmark circuits.>

An examination was made of the diagnostic properties of signature analysis. By theoretical and experimental studies the authors derived the probabilities that a given number of signatures occur during a test, and that a given number of signatures will be produced uniquely (i.e. by one fault). These characteristics were validated by a series of simulations of the benchmark circuits under test together with a response compaction procedure using linear feedback shift registers (LFSRs) implementing primitive polynomials. The experimental results confirm the validity of the theoretical model. The authors perform further calculations in order to reveal some important relationships between the size of the used LFSR, the total number of faults and the diagnostic resolution of signature analysis. Indeed, these results provide justification for the adoption of a simple formula that encompasses all the factors considered in the signature analysis compaction technique. Because of its simplicity it can be used directly in VLSI BIST design as well as in a wide range of other applications.>

Efficient algorithms are described for decomposition and factorization of Boolean expressions. The method uses only two-literal single-cube divisors and double-cube divisors considered concurrently with their complementary expressions. It is demonstrated that these objects, despite their simplicity, provide a very good framework to reason about common algebraic divisors and the duality relations between expressions. The algorithm was implemented and excellent results on several benchmark circuits illustrate its efficiency and effectiveness.>

Efficient strategies for selectively performing fault-free simulation, critical path tracing in fanout-free regions, and fault simulation of stem faults in a parallel pattern evaluation environment are presented and analyzed in an implementation-independent manner. The dynamic changes in the complexity of the fault simulation components as the fault simulation progresses and faults are detected are shown to be extremely significant. In particular, fault-free simulation tends quickly to become more expensive than both the critical path tracing within fanout-free regions and the explicit simulation of stem faults. In addition, the presence of redundant faults is shown to have an inhibiting effect on the reduction of the fault simulation complexity.>

A methodology for the experimental evaluation of fault models, using fault diagnosis as the basic approach, is developed. The methodology includes a way of determining the defect level of test sets, in addition to determining the adequacy of the fault models used to generate them. The key elements of the method are the design and fabrication of an easily diagnosable test chip, representative of the class of circuits being studied, the CAD (computer-aided-design) tools used in its design, and its fabrication process; the derivation of an extremely robust test set, capable of detecting faults from within a wide range of fault models; the development of a set of diagnostic tools to perform automated diagnosis on faulty circuits and the use of the results to get measures of 'effectiveness' of the fault models considered; the validation of the results of the diagnosis by means of an electron-beam voltage-contrast circuit prober. Experimental results from a large number of samples of the test circuit are presented.>

The authors present a novel test pattern generation algorithm which uses the concept of necessary assignments to reduce or eliminate backtracking in automatic test pattern generation. Necessary assignments are those which must be made in order to find a test pattern; without them the search is guaranteed to fail. The algorithm is based on the mathematical concept of images and inverse images of set functions. In order to take advantage of formal concepts developed for Boolean algebras, the algorithm uses a 16-valued algebra. It has been used to generate test patterns for all faults in a variety of benchmark circuits. Experimental results indicate that the algorithm is particularly efficient at redundancy identification, which is often a problem for conventional test pattern generation algorithms. The benefits of a 16-valued system are illustrated through examples of faults which are not properly handled by conventional 5- or 9-valued systems.>

The authors present a very efficient new method for the decomposition and factorization of Boolean expressions, which produces irredundant multilevel networks. The method is based on very simple objects, namely, double-cube divisors and single-cube divisors with only two laterals. It is demonstrated that these objects, despite their simplicity, provide a very good framework for reasoning about common algebraic divisors and duality relations between expressions. Since both the time and space complexity of the operations on double-cube and single-cube divisors is polynomial in the size of the two-level representation, the algorithms run much faster than those based on kernels. It is shown both theoretically and experimentally that the decomposition and factorization transformations introduced preserve testability, which implies that a complete test set developed for an input network also gives complete coverage of faults in the synthesized multi-level network.>

An exact fault simulation can be achieved by simulating only the faults on reconvergent fan-out stems, while determining the detectability of faults on other lines by critical path tracing within fan-out-free regions. The authors have delimited, for every reconvergent fan-out stem, a region of the circuit outside of which the stem fault does not have to be simulated. Lines on the boundary of such a stem region, called exit lines, have the following property: if the stem fault is detected on the line and the line is critical with respect to a primary output, then the stem fault is detected at that primary output. Any fault simulation technique can be used to simulate the stem fault within its stem region. The fault simulation complexity of a circuit is shown to be directly related to the number and size of stem regions in the circuit. The concept of stem regions has been used as a framework for an efficient fault simulator for combinational circuits. The concept allows a static reduction of the circuit area of explicit analysis for single- as well as multiple-output circuits. A dynamic reduction of processing steps is also achieved as the fault simulation progresses and fault coverage increases. The simulation algorithm is described, and experimental results are shown for the well-known benchmark circuits.>

The authors propose test schemes for glue logic (non-boundary-scan components) interconnects. Testing these interconnects is difficult owing to reduced accessibility and glue-logic function-dependent outputs. The proposed schemes address these testability issues and provide efficient boundary-scan based techniques. The tests are applied under the B-Scan DFT (design-for-testability) environment as scan tests. Thus, issues such as ease of test vector generation, test vector loading time, and test application time are very important for the proposed schemes. The application of the test schemes is described.>

An efficient PLA crosspoint fault simulation algorithm is presented. Parallel Boolean vector operations on a bitwise representation of PLA faults replace set operations, leading to increasing efficiency as the PLA size grows. Experimental results demonstrate execution times averaging over 100% faster than PLATYPUS and almost two and a half orders of magnitude faster than the CHIEFS fault simulator.>

The concept of stem regions has been used as a framework for a fast fault simulator for combinational circuits. The concept allows a static reduction of the circuit area of explicit analysis, for single-output as well as multiple-output circuits. A dynamic reduction of processing steps is also achieved as the fault simulation progresses and fault coverage increases. Both the static and dynamic reductions are fully compatible with the parallel pattern evaluation technique, resulting in a very efficient implementation. The simulation algorithm is described, and experimental results for well-known benchmark circuits are shown.>

An interconnection network capable of spontaneously reconfiguring a VLSI processor array upon detection of faulty processors is presented. Although the reconfiguration process is global in nature, the network control circuitry is localized around each processor and is therefore completely modular. In effect, the switches and control circuitry are completely local to each processing element (PE) even though the reconfiguration algorithm the network performs is general in nature. Further, as the control circuitry around each PE is fixed and no global control circuitry of any kind is required, the area overhead due to the network circuitry grows linearly with both the array size and the total number of spares.>

A comparative study is presented of different methods of calculating multiple fault coverage and aliasing probability measures. The objectives are to describe the ways that these ratios are defined to give them a physical interpretation, and to separate the discussion of how to define the measure from how the measure might be actually obtained or calculated. The interpretation, accuracy, and applicability of the measures are discussed.>

A general technique is described to represent stuck-open faults in CMOS networks by transition (slow-to-rise and slow-to-fall) faults in equivalent gate-level circuits. Generally, CMOS complex gate require two gate-level representations: one for the n- part and another for the p-. The two representations may not be dual. After transformation, an algorithm based on the GEMINI logic system is used to determine the stuck-open fault coverage of a given test set. Multiple stuck-open faults are handled implicitly. Thus, results are not invalidated in the presence of untested or untestable faults. Robust test sets can be generated easily. The method can be used both for test generation and for fault diagnosis. Experimental results for multiple stuck-open fault coverage for ten benchmarking circuits are presented and compared. In particular, coverage figures for both robust and nonrobust test sets are presented.>

A built-in self-test of interconnects based on boundary scan architecture is described. Detection and diagnosis schemes are proposed which provide minimal-size test vector sets. I/O scan chains order independent test vector sets and walking sequences. Properties like ease of test vector generation, structure-independent detection and diagnosis, and local response compaction have made the developed schemes suitable for built-in-self-test implementation. An example board-interconnect test session is described using one of the proposed schemes.>

A method for PLA (programmable logic-array) test-pattern generation based on a branch-and-bound algorithm that function monotonicity is presented. The algorithm makes irrevocable input assignments first, resulting in the efficient generation of compact test sets. In most cases there is no backtracking. An intelligent branching heuristic is presented. The algorithm handles extended fault models, including cross-point and delay faults. Heuristics which speed up test-set generation and improve test-set compaction are discussed. Results of tests on a wide range of benchmark PLAs are included.>

The authors present a fault coverage analysis method for test generation and fault diagnosis of large combinational circuits. Input vectors are analyzed in pairs in two steps using a 16-valued logic system, GEMINI. Forward propagation is performed to determine, for each line in the network, the set of all possible values it can take if the network contains any single or multiple faults. Based on the values observed at primary outputs, backward implication is performed to determine the value actually carried by each line. Some deduced values imply the line is not faulty; similarly, some values imply that there is a fault in the subnetwork driving the line, or on the line itself. By keeping track of this information, it is possible to locate a fault to within its equivalence class. An extended fault model which includes stuck-at, stuck-open, and delay faults is used. Multiple faults of all multiplicities are implicitly considered; thus, the results obtained using this method are not invalidated in the presence of untested or untestable lines.>

It is relatively easy to generate a complete single contact fault detection test set Tc for a PLA. However such a test set may fail to detect all multiple faults due to the phenomenon of masking. In previous papers attempting to quantitatively predict the multiple fault coverage capability of a single fault detection test set Tc in PLA's, it was proved that every multiple contact fault in an irredundant PLA is detected by Tc if the multiple fault does not contain any four-way masking cycle. In this correspondence, the masking relations are studied in detail and it is shown that Tc in fact detects a signifilcant percentage of faults with four-way masking. Based on these results more realistic bounds of the coverage capability of Tc are determined. It is shown that the multiple fault coverage ratio of Tc increases with the increasing number m of rows of a PLA and for m = 24 Tc detects 99 percent of all contact faults of size 8 or less.

The increasing number of applications of programmable logic arrays (PLA's) has evoked the development of test generation methods for these circuits. There are known methods for complete single contact fault detection test set generation. These test sets fail to detect all multiple faults in a PLA due to the phenomenon of masking. In this correspondence, we present a method to quantitively predict the multiple fault coverage capability of a single fault detection test set in a PLA. The method enables us to determine the coverage ratio, which is defined as the ratio of the number of multiple contact faults detected by a single fault test Tcto the total number of all multiple faults. It is shown that the multiple fault coverage ratio of Tcdrops with an increasing size of faults, and most unexpectedly, the ratio increases with an increasing number of rows. The number of crosspoints in one product line has very little influence on the ratio.

Known rearrangement algorithms proposed by Slepian and Paull (method 1) involve two middle switches of the three-stage Clos network. These switches are chosen arbitrarily. However, the middle switches selection rules affect the rearrangement process. In this paper four methods for choosing the switches were studied. Simulation results and analysis have shown that the allocation of the least used switches can decrease the volume of computation required for rearrangements. In the case of limited rearrangement, this method improves the blocking performance of a network.