This article presents hardware-efficient harmonics cancellation techniques using digital predistortion (DPD) for low-distortion sinusoidal signal generation, targeted for the dynamic characteristic testing of high-resolution 14-bit and 16-bit 1 MS/s analog-to-digital converters (ADCs) in VLSI testing environments. For 14-bit ADC testing, a single 16-bit digital-to-analog converter (DAC) with a simplified DPD circuit is demonstrated to achieve a second-order harmonic distortion (HD2) level of −92dBc. For 16-bit ADC testing, where higher resolution is required, we propose a novel dual-DAC architecture utilizing a dual-range synthesis method to enhance effective resolution and suppress harmonics up to the fifth-order (HD2–HD5). Furthermore, to minimize the hardware overhead in practical implementations, we introduce optimized field-programmable gate array (FPGA) design strategies, including time-division multiplexing (TDM) and compressed sine look-up tables (LUTs), achieving a 96.8% reduction in memory usage. The parameters are extracted via a single-step, deterministic calibration flow, ensuring high testing throughput without iterative optimization. Experimental results show HD2–HD5 levels down to −120 dBc, providing a hardware-efficient solution for high-precision built-out self-test (BOST) and future system-on-chip (SoC) integration.

This paper presents a 10ps-order flexible resolution time-to-digital converter (TDC) consisting of only Lookup Tables and Flip-Flops that can be applied to legacy FPGAs, which is industry friendly. The proposed TDC is a Vernier delay-line based TDC. By using MUX chains as the delay adjustable buffers, it realizes flexible and high resolution 10ps-order TDC. By controlling the control values of each MUX chain independently, the nonlinearity of TDC is compensated. In the evaluation using the AMD Artix-7 FPGA, the DNL and INL were [−0.26 LSB, 0.91 LSB] and [−0.84 LSB, 2.27 LSB], respectively, at a resolution of 8.92 ps.

This paper introduces a highly reliable delay-based weak FPGA Physically Unclonable Function (PUF), leveraging stochastic delay measurement with PLLs. The delay of delay-lines is precisely measured using the proposed fully synchronous stochastic delay measurement method. Thus, the reliability surpasses that of conventional PUFs that depend on asynchronous circuits or measurement. In the evaluation, the inter-chip HD of the proposed PUF without Spread Spectrum Clock Generator (SSCG) is 47.79%, and the intra-chip HD is 0.0052%, which is about 1/100 of the conventional PUFs. With SSCG, the inter-chip HD of the proposed PUF is 47.98%, and the intra-chip HD is 0.00092%, which is about 1/5 of the value in the absence of SSCG.

Digital technologies are rapidly prevailing in our society, and there the performance of analog circuits is progressing and their market amount is growing steadily. We have experienced that in many cases analog parts may be small compared to digital ones, but analog ones are troublesome. Testing of analog circuits plays a crucial role in achieving both reliability and low cost such as in computer, Internet, AI, IoT and automotive systems. Also, in ATE systems, analog parts are key. Analog testing is a challenge including circuit design, signal processing algorithms and measurement methods/systems.This session will discuss analog testing related issues with three talks by researchers from industry. The first talk introduces a state-of-art low jitter 1GHz crystal oscillator by an ATE manufacturer. The second one explains a time measurement BOST using a successive approximation register time-to-digital converter (SAR TDC) with fine resolution by a semiconductor company. The third one is a proposal of an ADC diagnosis method using obtained self-calibration parameters, by an ADC design researcher.

This paper presents a physically unclonable function (PUF) using flash time-to-digital converter (TDC) with linearity self-calibration. The proposed PUF utilizes that the variation of delay of delay elements of TDC is unique to the device and unclonable. The proposed PUF is constructed using the flash TDC with linearity self-calibration using histogram method. With the linearity self-calibration operation, variation of delay elements is estimated. The response output of the PUF is calculated using the estimated variation and the challenge inputs. The proposed PUF is a simple digital circuit consisting of basic digital elements. It is easy to design and implement to both SoC and FPGA. It can be used as not only strong PUF but also as a TDC with fine linearity. The experimental results with Artix7 FPGA show that the intra-chip variation is 8.9 % and the inter-chip variation is 46.9 %. The probability of the correct identification is 99.8 %. Extra resources to construct the proposed PUF are 33.7 % of the resources of the TDC with linearity self-calibration.

This paper describes two harmonics cancellation techniques using digital predistortion (DPD) for low-distortion sinusoidal signal generation with direct digital synthesizer; it is targeted for the dynamic characteristic testing of 14-bit and 16-bit 1MS/s ADCs and their testing sinusoidal wave frequencies are around 100kHz. (i) The first one is an analog-intensive DPD method for the 16-bit ADC testing. The HD2 and HD3 of the original sinusoidal signal are measured with FFT method, and then their 180-degree phase-shifted signals are generated with an auxiliary DAC and added to the original signal to cancel the HD2 and HD3. Our experiments show that −120dBc of HD2 and HD3 can be achieved. (ii) The second one is a digital-intensive DPD method for the 14-bit ADC testing. The digital data of the 180-degree phase-shifted signals of the measured HD2 and HD3 are added to the original digital data of the direct digital synthesizer. The circuit is simple, and our experiments show that −92dBc of HD2 can be achieved. Their details of analysis, simulation and experimental results are shown.

This paper demonstrates that a 20-bit subrange ADC for high precision voltage measurement can be implemented with standard ATE resource and BOST circuits, without special devices. Our prototype 20-bit ADC employs subranging architecture and consists of a 16bit ADC (LTC1867), a 20-bit DAC (ADC5791), Arduino and some additional circuits. Its operation has been confirmed with simulations and experiments, and effects of non-idealities for each circuit to the overall 20-bit ADC performance have been evaluated. We consider that a 16bit audio-band digitizer in an ATE system can be used as the 16bit ADC while the 20-bit DAC as well as an error amplifier (another component for the subranging ADC) can be implemented with BOST circuits.

Testing of analog circuits plays a very important role in achieving both reliability and low cost for IoT and automotive systems. It is a technological challenge including circuit design, signal processing algorithms and measurement methods. This session consists of three talks from industry and academia in this area.

This paper describes the application of our previously proposed residue sampling circuit to RF/Analog Mixed-Signal (AMS) device testing. The residue sampling circuit provides high-frequency signal estimation using multiple low-frequency sampling circuits following an analog Hilbert filter and ADCs; the sampling frequencies are relatively prime. It is based on aliasing phenomena in the frequency domain for waveform sampling and the residue number theory. A high frequency cosine wave is provided as an input signal. Cosine and sine signals with the same frequency are generated by an analog Hilbert filter and are fed into sampling circuits with different (relatively prime) low sampling frequencies. Their analog outputs are analog-to-digital converted and complex FFT is performed on both. Since the high frequency signal is sampled with low frequency clocks, aliasing (spectrum folding) occurs. However, each aliased frequency is different because each sampling clock frequency is different in the sampling circuits. Based on the Chinese remainder theorem, this difference allows the input frequency to be estimated. High frequency resolution can be achieved over long time periods and large numbers of FFT points. We consider here applications to RF/AMS device testing; (i) two tone testing for high frequency narrow band devices, (ii) wireless communication device testing such as LTE, Bluetooth and (iii) wideband analog filter frequency characteristics testing. These considerations are supported by simulations.

Background: In IoT system devices, currents become smaller and they have to operate for ten years with a coin cell battery. Then their accurate and fast measurement is required at the mass production shipping stage. However, the conventional method needs a large resistor (Rm, MΩ-order in Fig. 1) which makes the testing slow, and the ATE environment is noisy.Research Target: Our target is the development of a testing technique to measure the current in the order of nano or sub-nano ampere with high linearity in the noisy ATE environment and in short time as well as with only additional low cost built-out self-test (BOST) circuits.Approach: Fig. 2 shows the proposed current measurement circuits. The current under test is converted to the voltage through an op-amp and a resistor Rmof 10kΩ, and it is then converted to the AC voltage; these conversions are done with small BOST circuits. The AC voltage is amplified and converted to the digital signal through an AC amp, a sample/hold circuit and an ADC. FFT is performed and its power spectrum is calculated; the input current value is obtained. The resistor (Rm) of 10k generates spike noises which are spurious components in the power spectrum. However, usage of the sample/hold circuit reduces their effects. Thanks to the DC-AC conversion, the measurement accuracy is not degraded by the system noise in the low frequency region. The nano-ampere current and the resistor of 10kΩ produces several tens μV level voltage and our previous research in [1, 2] shows that the DC-AC conversion method can measure this level of the voltage accurately and in short time. Also, its multi-channel measurement is possible.Experiment Verification: Preliminary experiment with the prototype system in Fig. 2 was performed and its measured result is shown in Fig. 3. The measurement circuit gain in Fig. 2 was calibrated with 1.0nA input current (Iin), which corresponds to Vin of 10.0μV. Also an offset of 0.2μV due to electromotive force (EMF) was calibrated. We see in Fig. 3 that the proposed method can measure the current as low as 50pA. So far EMF limits the lowest measurable current. Fig. 4 shows 100 times of measurements for 1.0nA without averaging. Each measured current value is obtained by 1K-point FFT with 25.6 ksps, 16-bit ADC (myDAQ) usage and the measurement time of 40ms. The measured data is within 0.94nA to 1.07nA; the variation range is 0.13nAp−p.Conclusion: A method of fast and accurate current measurement as low as 50pA using IV conversion and DC-AC conversion in ATE environment has been developed.

In LSI testing, equivalent time sampling techniques are frequently used because the input signals to the device under test and the sampling clock are controllable; when the repetitive input signals are applied to the analog device under test, its output signals can be also repetitive. In this paper, we investigate an efficient waveform acquisition method with the equivalent-sampling using the metallic ratio of the sampling frequency and the input frequency, which is expected to be used for on-line, short-time and simple analog/RF/mixed-signal IC testing.

This paper demonstrates the harmonic distortion measurement of operational amplifiers by applying our proposed summing node method; we show that it can provide low-cost and high-accuracy testing at the mass production shipping stage. Experiments show that measurement accuracy below -130 dBc is possible without expensive test equipment such as an audio analyzer. We show by theory, simulations, and experiments that the summing node method makes the measurement accuracy robust to the harmonics of the signal source providing the sinusoidal input signal to the operational amplifier under test. In other words, a high precision signal generator is not required. Furthermore, we propose the false summing node method, which does not require direct probing of the summing node, in order to avoid oscillation and instability of the video-band operational amplifier under test. Simulations and experiments verify that it can achieve accurate testing without probing of the summing node and it is robust against the ratio variation of the two resistors in the false summing node testing circuit.

This paper describes that the mature ADC testing method with a simple test system using the incoherent sampling and the standard algorithm of windowing and FFT with 4Kpoint data can measure the SINAD of our target 12-bit SAR ADC accurately by proper setting of the input and sampling frequencies, which is industry-friendly. We show the input sinusoidal signal and sampling clock frequency relationship for accurate testing of the ADC dynamic characteristics with an incoherent sampling method using a flat-top window. We have clarified the measured SINAD accuracy of the input signal frequency dependency for a fixed sampling frequency, a specified resolution of the ADC under test and a given number of FFT points (data samples) in the incoherent sampling environment. Mature technology combinations with their optimal usage and without advanced methods can lead to the low-cost high-quality testing of the ADC, which can be well accepted in industry. Their analysis, simulation and experimental results are shown.

This paper proposes a summing node test method for the operational amplifier and shows the followings: (i) It can be used for parallel testing of multiple AC characteristics (such as open loop gain (AOL), PSRR and CMRR) of one operational amplifier simultaneously with the equivalent accuracy but much faster compared to the NULL method. Also it can measure them even for multiple operational amplifiers at the same time. (ii) It can measure THD, SNR and THD+N of the operational amplifier with the comparable accuracy to the audio analyzer usage case, by applying proper analog filters. In other words, it can measure them with remarkable accuracy at very low cost. These have been verified with simulations and experiments. The proposed summing node test method uses an inverting operational amplifier under test and its negative input is amplified by an auxiliary non-inverting operational amplifier. The input and power supply voltages for the operational amplifier under test are modulated by AC signals with different frequencies. The auxiliary amplifier output is digitized after analog filtering and FFT is performed to the digitized data. This proposed method can reduce operational amplifier test time with good accuracy but without expensive instruments at mass production shipping, to meet the requirements for IoT and automotive as well as audio applications.

This paper describes an accurate and fast testing technique for a precision voltage reference. Our proposed DC-AC conversion and FFT spectrum analysis method is applied and its experiment results show that measurement accuracy within ±100μV and measurement variation (repeatability) within ±10μV are feasible.

This paper describes the similarity of the crest factor reduction effect among the four algorithms (Newman, Kitayoshi, Schroeder and Narahashi) and unifies their initial phase setting equations using the derivation of the Narahashi phase. When testing the frequency characteristics of analog/mixed-signal ICs, a multi-tone (sum of multiple sine waves) signal is often used instead of a single tone signal, to reduce their testing time. However, as the amplitude of each tone signal becomes smaller if multiple sine waves are simply added without care of their initial phases, the SNR of the test result becomes worse and the test accuracy becomes lower. To alleviate this problem, it is necessary to generate a multi-tone signal using a crest factor reduction algorithm. There are four representative multi-tone signal generation algorithms for reducing crest factor, and their study results are presented.

The IP session highlights three innovative test practices in Asia, which include a testing solution for the millimeterwave (76- to 81- GHz) without expensive instruments, an on-chip delay measurement method for in-field test and a power control method of at-speed scan test for IR violation reduction. These would be useful for automotive and IoT application device testing.

This paper describes an accurate and fast testing technique for small DC offset voltage of a high precision operational amplifier. Chopper techniques for DC-AC conversion and FFT spectrum analysis are combined and then accurate DC voltage measurement on the order of μV can be achieved. We have also investigated thermo-electromotive force effects and their countermeasures. Their simulations and experiments with prototype measurement systems have been carried out, and the measurement linearity up to as low as 0.2 μV of the DC measurement voltage was confirmed. We have also investigated its extension to multi-channel realization for short testing time.

This paper investigates multi-tone signals for short-time and high quality testing of analog circuit frequency response. First, we study three multi-tone signal generation algorithms for minimum crest factor using an arbitrary waveform generator, and show that they are comparable. Then we propose crest factor controlled multi-tone signal generation algorithms for effective testing of transmitters. These algorithms are verified with simulations.

The IP session highlights three innovative test practices in Japan, which include DC parametric test time reduction using digital controlled DC resource and deep reconsideration for ADC distortion testing as well as test time reduction of low sampling rate and high-resolution ADC linearity. These would be useful for automotive and IoT application device testing.

This paper proposes time-to-digital converter (TDC) architectures using two asynchronous oscillators with different frequencies; each starts oscillation at different cycle at the rising timing of the corresponding input timing signal. We show here that by counting their oscillation start phase difference using digital counters, a highly linear stable time digitizer circuit can be realized. We propose two architectures using this principle: analog centric one and digital centric one. The analog centric one uses oscilloscope trigger circuits and the digital centric one uses ring oscillators. For analog centric one, its operation is stable but two external asynchronous sine signals are required. For digital centric one, all TDC circuits including the calibration can be implemented with full digital circuit. We present their configuration, operation and simulation verification.

This paper describes the optimal waveform acquisition condition between the measured waveform repetitive frequency (fsig) and the sampling clock frequency (fCLK) in an equivalent-time sampling system, when the measured waveform is periodic. We have obtained that in the case of fCLK / fsig = 1.6180.. or the golden ratio, a waveform missing phenomenon for the equivalent-time sampling can be avoided and highly efficient waveform acquisition sampling can be realized. We consider that this can be explained using the relationship to the golden section search algorithm. This paper presents its theoretical consideration and simulation results, and we consider that these results can be utilized in several LSI testing applications such as an ADC histogram testing method using a sine wave input and a timing measurement circuit design besides the equivalent-time sampling system.

This paper describes algorithms, simulation and experiment verifications of a novel harmonic distortion suppression technique for an arbitrary waveform generator (AWG). It can automatically suppress the harmonics and the image components over a full Nyquist region of the AWG by preprocessing the sinusoidal waveform data using "phase switching method". We show this technique can apply to cancel the harmonics from mid-frequency regions. Also we show two-tone signal generation with IMD suppression. With these methods, distortion components close to the signal are suppressed simply by changing DSP program or waveform memory contents-AWG nonlinearity identification is not required-and spurious components, generated far from the signal band, are relatively easy to remove using an analog filter.

The IP session highlights three innovative practices in Asia, which include low cost testing of analog front-end circuits, evaluation of complex analog filter and power reduction of power-on self-test for automotive MCU.

This paper presents a time-to-digital converter (TDC) architecture with reduced hardware suitable for timing built-in self-test (BIST) / built-out self-test (BOST) implementation. In order to reduce the number of buffers and D Flip-Flops (DFFs) in a conventional Flash TDC or Vernier TDC, successive approximation is applied to construct a successive approximation register (SAR) TDC. Besides, Vernier TDC has been added as the sub-circuit to form a (two-step SAR) + (SAR-Vernier) TDC architecture. Its self-calibration method for the linearity improvement is shown. We also propose to use a trigger circuit (originally used in an equivalent-time sampling oscilloscope) in front of the SAR TDC which enables to measure the timing effectively when two timing inputs are single-shot as well as repetitive clocks.

This paper proposes low-distortion sinusoidal/two-tone signal generation techniques for analog/mixed-signal IC testing with a digital Automatic Test Equipment (ATE) using only single digital output pin. They provide a rectangular waveform approximated to a single-tone or two-tone with specified harmonics suppression; we can specify multiple harmonics to suppress using digital control, and it is followed by an analog LPF for smoothing. The proposed method is simple for implementation with modest performance, compared to a wide dynamic range delta-sigma DAC. Its configuration, principle, simulation as well as experimental results at the laboratory level are presented. Also its application, combined with a high-speed DAC for analog circuit testing is described.

This paper describes a phase switching algorithm for Interpolating Digital-to-Analog Converter (DAC) based Arbitrary Waveform Generators (AWG). This was possible by using the standard phase switching algorithm with the addition of simple phase offset and systematic phase difference adjustment; this was discovered by experimenting with suppression of the intermodulation distortion (IMD) components of a two-tone signal. In this case, we examine the 3rd, 5thand 7thorder IMD tones and the effect of the phase switching algorithm and phase shift has on the AWG by measurement with a digitizer. Then we show what the effect of the developed two-tone phase switching technique has upon the performance measurement of a 16-bit Analog-to-Digital Converter (ADC). It is shown that using the original algorithm, no improvement could be achieved for the odd order IMD products. However, by using an even order suppression technique (another phase difference) with a phase shift, a suppression was achieved compared to the standard two-tone signal generation (without phase switching). We show how this technique allows the use of a low-cost tester resource to test IMD products with a higher dynamic range than was previously possible.

This paper proposes signal generator (BIST/BOST) algorithms and architectures for mixed-signal IC testing input. They can provide rectangular waveforms approximated to single-tone and/or two-tone signals with harmonics/IMD suppression. Their circuit consists of digital circuit, a 1-bit DA converter with an analog filter. Proposed method is simple for implementation with modest performance, compared to a wide dynamic range delta-sigma DAC [1, 2] and other methods [3-5].

This paper describes application of a complex band-pass (BP) ΔΣ DA modulator to I-Q signal generation for I-Q balance testing of communication IC as well as ATE system usage. First we explain that the complex BP ΔΣ DA modulator is superior to two real-BP ΔΣ DA modulators regarding to noise-shaping characteristics. Then we examine the characteristics of the complex BP ΔΣ DA modulator and its extension - a complex multi-BP modulator - as well as its newly derived Data Weighted Averaging (DWA) algorithm for its linearity enhancement. We also propose a digital self-calibration technique, and show their simulation results. Their combination is also investigated. We discuss application of our proposed techniques to IC testing.

A CMOS pulsewidth modulation (PWM) transceiver circuit that exploits the self-referenced edge detection technique is presented. By comparing the rising edge that is self-delayed by about 0.5 T and the modulated falling edge in one carrier clock cycle, area-efficient and high-robustness (against timing fluctuations) edge detection enabling PWM communication is achieved without requiring elaborate phase-locked loops. Since the proposed self-referenced edge detection circuit has the capability of timing error measurement while changing the length of self-delay element, adaptive data-rate optimization and delay-line calibration are realized. The measured results with a 65-nm CMOS prototype demonstrate a 2-bit PWM communication, high data rate (3.2 Gb/s), and high reliability (BER> 10-12) with small area occupation (540 μm2). For reliability improvement, error check and correction associated with intercycle edge detection is introduced and its effectiveness is verified by 1-bit PWM measurement.

This paper describes a method of generating low-distortion sinusoidal waves using an arbitrary waveform generator (AWG), and experimental results of using such a generator for ADC dynamic performance testing. With this proposed method, 3rdorder harmonics of the generated signal are suppressed simply by changing the AWG program (or waveform memory contents)-AWG nonlinearity identification is not required-and spurious components, generated far from the signal band, are relatively easy to remove using an analog filter; our theoretical analyses, simulations, and experiments showed that a simple passive LC analog filter (with relaxed requirements compared to the one for direct HD3 removal) is sufficient. Our ADC testing results-using signals generated by an AWG with the proposed algorithm, and a simple passive LC LPF-show measurement errors (caused by 3rdorder harmonics generated by AWG DAC nonlinearity) half that of previous algorithms.

Design of a clock jitter reduction circuit that exploits the phase blending technique between the uncorrelated clock edges that are self-delayed by multiples of the clock cycle, nT is presented. By blending uncorrelated clock edges, the output clock edges approach the ideal timing and, thus, timing jitter can be reduced by a factor of √2 per stage. There are three technical challenges to realize this: 1) generating uncorrelated clock edges, 2) phase averaging with small time offset from the ideal center position, and 3) minimizing the error in nT-delay being deviated from ideal nT. The proposed circuit overcomes each of these by exploiting an nT-delay, gated phase blending, and self-calibrated nT-delay elements, respectively. Measurement results with a 180-nm CMOS prototype chip demonstrated an approximately four-fold reduction in timing jitter from 30.2 ps to 8.8 ps in 500-MHz clock by cascading the proposed circuit with four-stages.

This paper presents a theoretical analysis of the stochastic calibration of TDC using two ring oscillators. Designers of TDC with the calibration function have to decide the design parameters to guarantee the convergence of error and valid calibration time. The basic theory of the calibration is useful to decide these parameters and the policy on the calibration design. The performance of the stochastic calibration depends on the design parameters, the frequencies of the two ring oscillators, the number of the stages, the buffer delay, and so on. This work analyzes explicitly the relation between these parameters and the performance of the calibration with simulation-based analysis. Simulation results reveal that the convergence of the calibration is guaranteed when both of the cycles of the two ring oscillators are the prime cycles. The histogram of each bin converges to the corresponding buffer delay value in a well-behaved manner, the DNL measurement error decreases monotonically in proportion to the increase of the number of the times of the measurement. In other words, the required number of the measurement times is in proportion to the required accuracy of calibration. This result is applied to the calibration of VDL-based TDC, too.

This paper describes a digital method of reducing timing mismatch effects in time-interleaved ADCs used in ATE systems: we use cross-correlation among channel ADC outputs to detect channel timing skew, and make successive-approximation adjustments to our proposed linear-phase-digital delay filter to compensate for the timing skew. Simulation results validate the effectiveness of the proposed method. We found that using multitone input signals with cross-correlation of outputs provided a more robust way of detecting timing skew than using a singletone input signal. Since our proposed approach is fully digital, it is reliable, and suitable for fine CMOS implementation.

This paper demonstrates a reference-free, high-resolution on-chip timing jitter measurement circuit. It combines a self-referenced clock and a cascaded time difference amplifier (TDA), which results in reference-free, high-resolution timing jitter measurement without sacrificing operational speed. The test chip was designed and fabricated in 65 nm CMOS. Measured results of the proposed circuit show the possibility of detecting a timing jitter of 1.61-ps RMS in 820 MHz clock with less than 4% error.

This paper describes algorithms for generating low intermodulation-distortion (IMD) two-tone sinewaves, for communication application ADC testing, using an arbitrary waveform generator (AWG) or a multi-bit ΣΔ DAC inside an SoC. The nonlinearity of the DAC generates distortion components, and we propose here eight methods to precompensate for the IMD using DSP algorithms and produce low-IMD two-tone signals. Theoretical analysis, simulation, and experimental results all demonstrate the effectiveness of our approach.

This paper reviews the theory and introduces the architecture for a clock source with low phase noise and for measuring timing jitter. This approach utilizes a sample mean and sum of two random variables, and can be implemented in CMOS or SiGe BiCMOS circuits.

This paper proposes a new procedure for calculating high-accuracy PDF estimates, which are free of random error and nearly free of bias error. The procedure is verified experimentally using random jitter and a 16-bitADC.

This paper describes the timing skew compensation technique using the digital filter with our novel linear phase condition. First we describe the digital filter which can set its group delay with the arbitrary fine time resolution while it maintains the linear phase characteristics; the conventional linear phase digital filter can set its group delay with the time resolution of a half of the sampling period. We will provide its structure and operation, theoretical analysis as well as simulation verification. Next we will describe the application of our proposed digital filter to compensate for timing skew in the following cases: (1) Sampling timing skew among channels in the time-interleaved ADC system. (2) I, Q-path timing skew in the single-side band (SSB) signal generator. We show its effectiveness with simulation.

A Time-to-Digital-Converter (TDC) is to measure the interval time between two signals, and its time resolution of several pico seconds is achieved when it is implemented with advanced CMOS process [1–5]. Its applications are gradually expanding such as a phase comparator of all-digital-PLL, a sensor interface circuit, modulation circuit and demodulation circuit as well as a TDC-based ADC [1–6]. The TDC will play more important role in nano-CMOS era because it is well-matched to implement with fine digital CMOS process; it consists of mostly digital circuits, and as the switching speed increases, its performance is improved.

Interleaving is one method of configuring a highspeed waveform digitizer. Degradation of the dynamic range, however, results from co-channel mismatched characteristics among the individual ADCs. Especially, mismatches of the non-linear characteristics have not been analyzed so far. This paper constructs a mathematical model, and proposes a method for correcting mismatches of both linear and non-linear characteristics using a digital signal processing technique. This method does not require any additional hardware.

A second-order multibit switched-capacitor (SC) complex bandpass ΔΣ AD modulator has been designed, fabricated and tested for application to low-IF receivers in wireless communication systems. We have employed two new algorithms there to improve the signal-to-noise-and-distortion (SNDR) of the modulator, (i) A complex bandpass filter with I, Q dynamic matching to reduce the mismatch influence between I, Q paths. As its by-product, the complex modulator can be divided into two separate parts without signal line crossing between the upper and lower paths. Therefore, the layout design of the modulator can be greatly simplified; (ii) A new complex bandpass data-weighted averaging (DWA) algorithm is implemented to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy. Implemented in a 0.18-μm CMOS process and at 2.8V supply, the modulator achieves a measured peak SNDR of 64.5dB at 20MS/s with a signal bandwidth of 78kHz while dissipating 28.4mW and occupying an area of 1.82mm2.

There are two dynamics issues in vision chips: (i) the temporal dynamics issue due to the parasitic capacitors in a CMOS chip, and (ii) the spatial dynamics issue due to the regular array of processing elements in a chip. In this paper we consider parasitic inductances as well as parasitic capacitances for a network dynamics model. We show that in some cases the temporal stability condition for the network with parasitic inductances and capacitances is equivalent to that for the network with only parasitic capacitances, but in general they are not equivalent. We also show that the spatial stability conditions are equivalent in both cases.

This paper discusses digital error correction algorithms for folding/interpolation AD converters which yield to very simple circuitry. The relationships between error correction and input signal frequency have been clarified theoretically and also confirmed by simulation.

A typical analog image-processing neural network consists of a 2D array of simple processing elements. When it is implemented with CMOS LSI, two dynamics issues naturally arise: (1) parasitic capacitors of MOS transistors induce temporal dynamics. Since a processed image is given as the stable equilibrium point of temporal dynamics, a temporally unstable chip is unusable; and (2) because of the array structure, the node voltage distribution induces spatial dynamics, and the node voltage distribution could behave in a wild manner which is undesirable for image-processing purposes. This paper derives several explicit formulas and relationships for the 2D dynamics, which are useful for the design and analysis of the class of networks of interest.

A typical image processing neuro chip consists of a regular array of very simple cell circuits. When it is implemented by a CMOS process, two stability issues naturally arise. First, parasitic capacitors of MOS transistors induce temporal dynamics. Since a processed image is given as the stable limit point of the temporal dynamics, a temporally unstable chip is unusable. Second, because of the array structure, the node voltage distribution induces spatial dynamics, and it could behave in a wild manner, e.g. oscillatory. The main contributions are: (i) a clarification of the spatial stability issue; (ii) explicit if and only if conditions for the temporal and the spatial stability in terms of circuit parameters; (iii) a rigorous explanation of the fact that even though the spatial stability is stronger than the temporal stability, the set of parameter values for which the two stability issues disagree is of (Lebesgue) measure zero; and (iv) theoretical estimates of the processing speed.