Abstract This paper presents a new adaptive window‐based guided filtering and interpolation for polarization image demosaicing. Considering the correlation between the polarization channels, the authors use the total intensity S 0 as a guide image to guide the interpolation of all channels. The guided filtering is performed with a new adaptive window size selection technique. A novel iterative residual interpolation is proposed to construct accurate full resolution polarization. Experiments are conducted with the sample images from the demosaicking algorithms dataset. Objective evaluations demonstrate that the proposed algorithm can reduce root mean squared error by at least 27% over other methods. Subjective visual inspection can also verify the improvements in the clarity of objects in angle and degree of the linear polarization images.

Owing to its good compression ability, discrete cosine transform (DCT) is widely used in signal processing, including high-efficiency video coding (HEVC). For efficient implementation, approximate DCTs and integer DCTs were proposed, but the challenge in the tradeoff between coding performance and implementation cost always exists. To solve this problem, this article proposes a new algorithm to derive Int-DCT with good coding performance and low hardware cost. To address the multiobjective optimization problem, we extract information from the initially shortlisted transform matrices to derive the weighting factors for the different matrices properties. Those properties having a higher impact to the performance are assigned with higher weights and vice versa. Subsequently, an efficient search algorithm is proposed to shortlist those candidates which can lead to better coding performance evaluated by the proposed measure. Last but not the least, a splitting method is proposed to search the efficient extended double-base number system (EDBNS) representation of the coefficients for hardware implementation and select the solution which encounters the lowest cost. The experimental results in ASIC demonstrate that the implementation area and power cost of designs by the new algorithm are reduced by at least 11.1% and 17.5% for 32-point transform, respectively, over other competing algorithms. Meanwhile, the transforms generated by the proposed algorithm causes negligible impact to coding performance compared to the original transforms in HEVC.

Along with the popularization of small unmanned aerial vehicles (UAVs), societal concerns related to security, privacy, and public safety have gained more attention, thus opening a new avenue for small UAV surveillance. However, the conventional radar technologies pose challenges for the surveillance of small UAVs due to the high cost, small radar cross section, low flying altitude, and slow flying speed. In this article, we propose a novel micro-Doppler signature-based surveillance method using machine learning techniques, for detection, classification, and localization of small UAVs. Via extensive experiments, we demonstrate the performance gain of our proposed method by applying long short-term memory neural network.

Fast Fourier transform (FFT) is an essential algorithm in digital signal processing and advanced mobile communications. With the continuous development of modern technology, the area-power efficient hardware implementation of FFT has attracted a lot of attention. In this article, a novel design for FFT implementation is proposed. The number of resource-expensive multiplications in our design is decreased by a twiddle factor merging technique that reduces the hardware area. Subsequently, a common subexpression sharing scheme is applied to reuse the hardware resources to further save the hardware area. In addition, a magnitude-response aware approximation algorithm is proposed for applications where the transformation accuracy can be compromised a little bit for lesser hardware area and power dissipation. Logic synthesis shows that the proposed 16-point FFT architecture can save hardware area and power dissipation on application-specific integrated circuit (ASIC) by up to 65.7% and 53.1% compared with recently published designs. Similarly, the proposed 32-point FFT architecture achieves up to 58.8% reduction on hardware area and 60.0% reduction on power dissipation on ASIC.

Wavelet transform using Haar filter is a fast process for decomposing an image into low and high frequency sub-bands, which is an important step in multi-focus image fusion. This transformation alone is usually not sufficient to produce satisfying fused images, and therefore additional tools like focused region decision map and feature extraction are needed to enhance the fusion quality. In this paper, we propose a multi-focus image fusion algorithm that is suitable for efficient hardware implementation. The algorithm speed is significantly improved by utilizing Haar wavelet and computationally simple fusion rules. To further improve the circuit power and delay, we limit the logic operations to additions, subtractions, and multiplications only. Experiments on different benchmarks demonstrate that our proposed algorithm can reduce the fusion time by up to 99.97% compared with the state-of-the-art competing methods without compromising the fusion quality. In addition, the hardware implementation of the proposed algorithm reduces the circuit area and delay by 79.5% and 92.5%, respectively, when compared to the most competitive algorithm in this paper while maintaining similar fusion quality.

This paper presents a novel optimized quantization constraint set, acting as an add-on to existing DCT-based image restoration algorithms. The constraint set is created based on generalized Gaussian distribution which is more accurate than the commonly used uniform, Gaussian or Laplacian distributions when modeling DCT coefficients. More importantly, the proposed constraint set is optimized for individual input images and thus it is able to enhance image quality significantly in terms of signal-to-noise ratio. Experimental results indicate that the signal-to-noise ratio is improved by at least 6.78% on top of the existing state-of-the-art methods, with a corresponding expense of only 0.38% in processing time. The proposed algorithm has also been implemented in GPU, and the processing speed increases further by 20 times over that of CPU implementation. This makes the algorithm well suited for fast image retrieval in security and quality monitoring system.

This paper presents a fast and effective polarization image demosaicking algorithm, which explores inter-channel dependency of Stokes parameters for the minimization of residual aliasing artifacts after cubic spline interpolation. A guided filtering approach is used for denoising. An optimization based on the confidence level of the aforementioned guided filtering, the correlations between the demosaicked image and input, as well as the total intensity, angle and degree of linear polarization, is constructed and solved with Newton's method. Experimental results demonstrate that the proposed algorithm can surpass the existing methods in terms of both objective root mean squared error and structural similarity index by at least 36.0% and 3.4%, respectively, and by close visual inspection of the clarity of objects in the angle and degree of linear polarization images. The proposed algorithm consists of only convolutions and element-wise operations, making it fast and parallelizable for efficient GPU acceleration. An image of size 512 × 612 × 4 can be processed within 10 s on i7-6700k CPU, and gains further 5 times speedup with M4000M GPU.

Shifting an input data by variable amounts is commonly found in arithmetic operations, data encoding and bit-indexing. Although some shift amounts along the entire shift range are not required, the typical realization by a full-range logarithm shifter requires full implementation and therefore suffers from complexity and power overhead. In this paper, the notion of sporadic logarithmic shifter (SLS) is introduced for the first time, and a new design methodology is proposed for its optimization. By reusing parts of existing substructure of conventional logarithmic shifter or post-multiplexing the hardwired shifts, contagious subranges of desirable shift amounts are successively realized. Synthesis results on 8-bit and 16-bit SLSs show average application-specified integrated circuit area and power savings of up to 73.24% and 63.90%, respectively, over conventional logarithmic shifters. In addition, by applying the proposed SLSs to the discrete cosine transform (DCT) architecture, at least 47.5% area savings and 2.9% power savings can be achieved over two constant multipliers-based DCT architectures reported in the literature.

Homography has wide applications in aerial photographic surveys, camera calibration, traffic scene analysis, and sports science, such as player and team performance evaluation. Unlike the mainstream homography that utilizes points as matching features, homography estimation for sports and traffic video can achieve higher accuracy and speed by utilizing straight lines in the scenes, which convey more information than points. Owing to the more stringent requirement of accuracy and computational speed for advanced video analysis, this paper presents a novel homography computational algorithm. Three major novelties are proposed and validated, which are multiple points Hough transform for straight line extraction, correspondence initialization by angle to estimate a set of quasi-optimal solutions, and the feature correspondences optimization to achieve a minimized error using genetic algorithm. With these contributions, the experiments have shown that the proposed algorithm can improve the homography computational accuracy by up to 130% and reduce the processing time by up to 96% over the state-of-the-art algorithms for the same purposes.

This paper makes a paradigm shift in the assumed notion of common subexpressions for complexity reduction of multiple constant multiplications implementation. Our proposed unified adder/subtractor (UAS)-based common subexpression elimination (CSE) algorithm is inspired by the recent advancement in complex arithmetic component mapping for datapath synthesis of digital systems. A dedicated UAS operator is designed at gate level to achieve arithmetic reduction for concurrent computation of the sum and difference of two input signals. To maximize computation reuse, dual subexpression is defined to enable a UAS to be shared by the otherwise incompatible odd and even common subexpressions. The three different types of common subexpression are uniquely encoded by a quadruple in the proposed data structure. Constant coefficients are represented by signed digits in Cartesian coordinate system from which nonoverlapping pairs of nonzero digits are parsed for dual, even, and odd subexpressions to maximize the reuse of all three types of arithmetic resources. The effectiveness of our proposed UAS-based CSE in overcoming the complexity reduction bottleneck are demonstrated by comparing the synthesis results obtained from six benchmark finite impulse response filters, an electroencephalogram filter bank, fast Fourier transform, and discrete cosine transform multipliers designed by ten algorithms. The results show a noteworthy 27.2% reduction in area-time complexity of our method over the baseline canonical signed digit implementation. Our solutions are also more power efficient, with average power saving of 12.0% over those designed by other algorithms in comparison.

In this paper, a new design algorithm is proposed to synthesize low complexity twiddle factor multipliers in radix-2 FFT. A prudently defined cost function has been proposed as a measure of hardware complexity when generating trigonometric expressions for the complex multiplier coefficients. The selected trigonometric expressions of the coefficients lead to cost efficient implementation of twiddle factor multipliers by maximizing the sharing of both trigonometric expressions and weight-two common subexpressions in the coefficients. The effectiveness of the proposed design algorithm are demonstrated using two design examples where the proposed solution saves up to 31% of arithmetic operator and multiplexer costs over other existing methods.

This paper presents a new method to design low complexity programmable FIR filters by the merit of optimization on the multiplexer array. Searching approach for efficient common subexpressions has been presented to design each filter tap with the minimum number of multiplexers. The other multiplexer optimization technique is also proposed to reduce the number of inputs of multiplexers. These design methods contributed to the significant complexity reduction comparing to other design methods. Logic synthesis result shows that the designed 12-bit programmable filter can achieve the complexity saving up to 40.37% in ASIC implementation and 36.31% in FPGA implementation over other existing methods.

Scalability of current programmable FIR filter design methods are severely limited by the huge search space for common subexpressions and the density of unique subexpressions over the complete range of integers of desirable precision. This paper presents the first attempt to solve this problem by means of Canonical Double-Based Number Representation (CDBNR). We address the representation sparsity of generic filter coefficients by developing a simplified CDBNR search algorithm. The statistics generated for all double base products of a given coefficient word length are used to maximize the sharing of arithmetic operators and reduce the multiplexing cost. The effectiveness and scalability of the proposed design algorithm are demonstrated using two design examples. For the 8-bit programmable filter example implementable by two latest design methods, our proposed solution saves about 24% of arithmetic operator and multiplexer costs for large filter.

This paper proposes a new design methodology to reduce the logic complexity of reconfigurable multiplier block (ReMB). The minimization problem is modeled as a scheduled time-multiplexed data flow graph (TDFG). To reduce the number of operators to be scheduled in the DFG, the most dominant common subexpressions are greedily identified and eliminated based on the subexpressions' frequencies which are updated dynamically in the optimization process. High level synthesis algorithm is then employed to perform the scheduling of operators to control steps. By binding the compatible operators in the same control steps, more operators can be saved. Two design examples are used to demonstrate the effectiveness of the proposed algorithm. On average, the logic complexity of the proposed ReMB design is about 19% lower than that of the classical ReMB methods, and 7% lower than that of the latest and most competitive ReMB design methodology.

Efficient power modeling of a generic class of digital circuits is crucial to the analysis and development of optimization algorithms of power efficient design. This paper proposes a new switching power index model for the power analysis of multiplier-block based FIR filter. Unlike the existing glitch path count (GPC) and glitch path score (GPS), the proposed power index (PI) model takes into account correlated input switching activity propagations of full adders within and across adders of different widths, as well as the variation of load capacitances due to sharing of adders in reduced adder graph. Dynamic power simulations of several benchmark filters in an ASIC design flow show that this PI measure is more closely correlated with the actual dynamic power dissipation than the existing GPC and GPS models.

Multiplying a signal by a known constant is an essential operation in digital signal processing algorithms. In many application scenarios, an input or output signal is repeatedly multiplied by several predefined constants at different instances. These temporal redundancies can be exploited for the design of an efficient reconfigurable constant multiplier (RCM). An RCM achieves greater hardware savings than the conventional multiple constant multiplication architecture, limited only by the available latency of the subsystem. Motivated by a number of lucrative examples, this paper presents a new high-level design methodology for RCM. Common subexpressions in the preset constants represented in minimum signed-digit system are first eliminated to obtain a minimum depth multiroot directed acyclic graph (DAG). The DAG is converted into a primitive data flow graph (DFG) where mobile adders are identified. By scheduling each mobile adder into a control step within its legitimate time window with the minimum opportunity cost, mutually exclusive adders can be merged with significantly reduced adder and multiplexing cost. The opportunity cost for each scheduling decision is assessed by the probability displacement and disparity measures of the scheduled node as well as its predecessors and successors in the DFG. The algorithm is runtime efficient as exhaustive search for the best fusion of independently optimized constant multipliers has been avoided. Simulation results on randomly generated 12-b constant sets show that the solutions generated by the proposed algorithm are on average 19% to 25% more area-time efficient than the best reported solutions.

This paper extols the virtues of information theoretic approach to the synthesis of reduced multirooted directed acyclic graph (DAG) representation for the multiplier block of FIR filters. The proposed maximum likelihood decomposition algorithm can be viewed as an efficient divide-and-conquer approach with dynamic tracking of the statistic of weight-two subexpressions. As isomorphic subgraphs of the resultant reduced multirooted binary partition tree (MBPT) represent common subexpressions, higher weight common subexpressions are eliminated implicitly in the graph synthesis process. Experimental results show that the proposed algorithm produce designs with good tradeoffs for low logic complexity and logic depth