EDBT 2026 Demo / reviewers in the wild / expert
Andreas von Bechtolsheim
dblp:53/926
· DBLP profile ↗
5ranked-venue papers
4as first author
0since 2021 · last 2007
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 first-authorComputer networks · 1Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-authorHuman-computer interaction and ubiquitous computing · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer networks
1 paper |
Internet architecture and protocols · 56% Transport protocols and congestion control · 44% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Memory systems · 57% Electronic design automation · 43% |
Topics — the 5 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Internet architecture and protocols
buffer management |
0.0 | 1 | 2001 | Using Dynamic Buffer Limiting to Protect against Belligerent Flows in High-Speed Networks · ICNP 2001 |
Transport protocols and congestion control
queue management |
0.0 | 1 | 2001 | Using Dynamic Buffer Limiting to Protect against Belligerent Flows in High-Speed Networks · ICNP 2001 |
Internet architecture and protocols
high-speed networks |
0.0 | 1 | 2001 | Using Dynamic Buffer Limiting to Protect against Belligerent Flows in High-Speed Networks · ICNP 2001 |
Rendering
raster graphics |
0.0 | 1 | 1980 | High-performance raster graphics for microcomputer systems · SIGGRAPH 1980 |
Memory systems › memory architecture
frame buffer architecture |
0.0 | 1 | 1980 | High-performance raster graphics for microcomputer systems · SIGGRAPH 1980 |
Methods — techniques the papers use, named apart from their topics
hardware implementation · 0.0read-modify-write cycle · 0.0DMA · 0.0(x,y) addressable memory · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2007 | Scaling to PetaFlopsabstractThis presentation discusses the myriad of challenges involved in getting to true Petaflop performance, including the CPUs, memory, interconnect, and software. Andreas von Bechtolsheim |
CLUSTER | 1 |
| 2001 | Using Dynamic Buffer Limiting to Protect against Belligerent Flows in High-Speed NetworksabstractConventional QoS mechanisms have focused primarily on providing better than normal service for some flows over others. With networks moving to much higher speeds and reasonable provisioning, best efforts access to network resources is adequate for common applications except when a belligerent flow attempts to consume an excessive amount of bandwidth. Any mechanism that attempts to contain such a flow must be able to operate at wirespeed in hardware. In this environment, conventional QoS mechanisms are not sufficient, either because they do not have mechanisms to contain these belligerent flows or because they are not practical to implement in hardware. In this paper we describe dynamic buffer limiting (DBL), a buffer and queue management mechanism designed to recognize and handle belligerent flows at very high speed and suitable for hardware implementation. Fusun Ertemalp, David R. Cheriton, Andreas von Bechtolsheim |
ICNP | 3 |
| 2000 | Why Doesn't EDA Get Enough Respect?
Andreas von Bechtolsheim, Joe Costello, Aart de Gues, Patrick Scaglia |
ICCAD | 1 |
| 1980 | High-performance raster graphics for microcomputer systemsabstractA frame buffer architecture is presented that reduces the overhead of frame buffer updating by three means. First, the bit-map memory is (x,y) addressable, whereby a string of pixels can be accessed in parallel. Second, the pixel-change operation is performed by hardware in a single read-modify-write cycle. Third, multiple objects in the frame buffer are addressable simultaneously by a set of address registers. The remaining task of generating (x,y) addresses and providing new data can be managed rapidly by current microprocessors or DMA-devices.With a modest expenditure of hardware, this architecture eliminates all the bit-shifting, bit-masking, and bit-manipulation conventionally associated with frame buffer graphics, while retaining the full generality of user-programmable control. The particular implementation described allows raster manipulation at full bit-map memory bandwidth. It can paint a 16×16 pixel character into the frame buffer in 16 microseconds and can modify a 1024×1024 pixel raster in 64 milliseconds. Andreas von Bechtolsheim, Forest Baskett |
SIGGRAPH | 1 |
| 1978 | Interactive specification of structured designs
Andreas von Bechtolsheim |
DAC | 1 |