Modern wireless communications systems deploy massive MIMO systems with large numbers of transmit and receive antennas and analog–digital RF transceiver architectures that admit RF beamforming. These systems need to be tested and tuned postmanufacture to ensure signal quality. In analog architectures, this poses a problem due to the lack of observability of internal circuit nodes and due to the convergence of multiple RF beamforming chains into a combined baseband signal from which it is difficult to de-embed individual RF chain behaviors. Existing test techniques estimate nonlinearities in RF chains up to the third order and require significant frequency bandwidth to test multiple RF chains in a MIMO system in parallel, thereby reducing the overall test time. In this research, to improve testing efficiency, overlapping test tones over a minimal frequency range are applied to each of the MIMO RF chains in parallel, allowing specifications of individual RF chains up to fifth-order distortion to be determined accurately. For postmanufacture tuning, a response feature clustering approach followed by an implicit cost-driven tuning procedure is proposed. Tuning for error vector magnitude (EVM) and signal-to-interference ratio (SiNR) is performed under power constraints. Experimental results show that the proposed parallel testing methodology is 1.7$\times$more frequency-efficient than existing techniques, and the proposed postmanufacture tuning algorithm can tune a receiver with four RF chains in 1.8 ms.

Test stimulus generation algorithms for analog/RF circuits rely on iterative simulation of the circuits concerned and are extremely computation-intensive. Our objective is to speed up test stimulus generation while allowing tests to be optimized dynamically (adapted) across diverse process corners that a device under test (DUT) is experiencing during manufacturing without compromising test quality. To achieve this, we propose to dynamically recognize devices from unknown process corners during manufacturing test and create Booleanized models of these devices from measurements performed on hardware. The cumulative ensemble of Booleanized models across different devices is used to (re-) optimize tests depending on observed performance statistics. The use of Booleanized models for test generation allows orders of magnitude speed up in test computation time while allowing emulation of devices long after they have shipped to the customer. The method is demonstrated using the alternative test methodology developed in prior research and allows the tests concerned to adapt to process shifts in a dynamic manner during device manufacture. The simulation results and hardware measurements are used to demonstrate the efficacy of the proposed techniques.

High levels of integration in SoCs and SoPs is making pre as well as post-silicon validation of mixed-signal systems increasingly difficult due to: (a) lack of automated pre and postsilicon design checking algorithms and (b) lack of controllability and observability of internal circuit nodes in post-silicon. While digital scan chains provide observability of internal digital circuit states, analog scan chains suffer from signal integrity, bandwidth and circuit loading issues. In this paper, we propose a novel technique based on built-in state consistency checking that allows both pre as well as post-silicon validation of mixed-signal/RF systems without the need to rely on manually generated checks. The method is supported by a design-for-validation (DfV) methodology which systematically inserts a minimum amount of circuitry into mixed-signal systems for design bug detection and diagnosis purposes. The core idea is to apply two spectrally diverse stimuli to the circuit under test (CUT) in such a way that they result in the same circuit state (observed voltage/current values at internal or external circuit nodes). By comparing the resulting state values, design bugs are detected efficiently without the need for manually generated checks. No assumption is made about the nature of the detected bugs; the stimulus applied is steered towards those that are the most likely to detect design bugs. Test cases for both pre and post-silicon design bug detection and diagnosis prove the viability of the proposed BISCC approach.

Future 5G wireless systems will deploy massive MIMO systems with large numbers of transmit and receive antennas and novel RF transceiver architectures that admit RF beamforming. Such systems will need to be designed with built-in test and post-manufacture self-tuning capability for yield enhancement and in-field tuning. A key issue is the lack of observability into internal circuit nodes due to the convergence of multiple RF beamforming chains into a combined baseband signal and the need to decouple individual RF chain behaviors from combined baseband signals. A second problem is that of testing and tuning as many RF chains in parallel as possible across a diverse range of specifications and modes of operation (beam steering angles) using optimized test stimulus. The interdependence between phase shift and gain of phase-shifter/amplifier configurations complicates the latter. Also, in relation to SISO/MIMO omnidirectional systems, large numbers of tuning knobs are involved. To solve the above, we propose novel algorithms for parallel testing and tuning of massive MIMO beamforming systems. Machine learning assisted coarse tuning is first performed followed by a fine-tuning procedure utilizing gradient descent. Tuning for EVM and signal-to-interference ratio is performed under power constraints. Simulation results prove the viability of the proposed techniques.

We present a methodology for algorithmic generation of test signals for the detection and diagnosis of a variety of short and open-circuit defects in analog circuits. Prior algorithms have focused on test generation for known short or open defect values. This places the burden of failure coverage on accurate analysis of observed defects in known failed parts at high cost. In this work, we optimize the test stimulus to detect theweakestshorts and opens in analog circuits using a concurrent stimulus and defect value optimization algorithm. Since the defect value itself is an optimization parameter, the responses of nonlinear circuits corresponding tomultiple defect valuesare considered as opposed to asinglelinearized representation corresponding to a fixed defect value as in the existing state of the art. The algorithm produces a test stimulus along with the values of the weakest shorts and opens that the stimulus can detect (the locations of the defects are specified to the algorithm). These values are determined by the design of the analog circuit itself and therefore subsume all specified detectable defects for the circuits concerned. Experimental results show the feasibility of the proposed approach on selected test cases and defect sets.

Physically Unclonable Function (PUF) circuits are designed to provide part-specific responses that are random across different copies of the circuit by exploiting the unavoidable process variations in nanometer scale fabrication. This property can be used as an important building block in security and cryptographic applications including key generation and challenge-response authentication. A major problem, however, is to ensure PUF response stability and reliability in the presence of circuit and environmental noise. SRAM based PUFs are most promising in this regard but still require extensive output error correction because the response of many cells in the memory array is not consistent. Unfortunately, all such "weak" cells cannot be determined in advance to allow their unstable responses to be masked out. In this paper we present a new SRAM PUF design that allows all the unstable weak cells to be reliably identified over the full range of operating conditions including temperature, electrical noise, and aging. By using the remaining "strong" cells, each instantiation of our SRAM PUF provides the same consistent and repeatable response every time it is challenged, without any need for error correction. Experiments reported here show that relatively few (of the order of 10%) SRAM PUF cells are truly stable in the presence of realistic circuit noise; in addition to the expected noise level, this number also depends on the random variability in the manufacturing process. Our simulation results show that the new SRAM PUF can be designed to maintain good robustness against any level of expect circuit and environmental noise, and is resilient to aging.

In the modern mixed-signal SoC design cycle, designers are frequently tasked with detecting and diagnosing behavioral discrepancies between design descriptions given at different levels of hierarchy, e.g. behavioral vs. transistor level descriptions or behavioral/transistor level descriptions vs. fabricated silicon. One problem is detection, to determine if behavioral differences between design descriptions exist. If such differences (anomalies) are detected, then diagnosis is concerned with identifying the module in a hierarchical design description of the system that is most likely the root cause of the anomaly (typically under the constraint that only the primary outputs of the top-level hierarchies are observed. Previously proposed machine-learning classifiers require prior knowledge about the kinds of likely design errors typically encountered. In this work, we present a novel technique for the algorithmic foundation of circuit diagnosis predictions which does not require any assumptions about the nature of design errors. Our method employs iterative and alternate on-the-fly test generation and least-squares fitting of embedded low-order nonlinear filters to produce a best-guess estimate of the root cause of the anomaly. Experiments are conducted on two test vehicles, an RF transceiver and a phase-locked loop, several bug models are implemented, and the system's diagnosis predictions are analyzed.

The test generation problem for analog/RF circuits has been largely intractable due to the fact that repetitive circuit simulation for test stimulus optimization is extremely time-consuming. As a consequence, it is difficult, if not impossible, to generate tests for practical mixed-signal/RF circuits that include the effects of tester inaccuracies and measurement noise. To offset this problem and allow test generation to scale to different applications, we propose a new approach in which FSM models of mixed-signal/RF circuits are abstracted from hardware measurements on fabricated devices. These models allow accurate simulation of device behavior under arbitrary stimulus and thereby test stimulus generation, even after the device has been shipped to a customer. As a consequence, it becomes possible to detect process shifts with fine granularity and regenerate tests to adapt to process perturbations in a dynamic manner without losing test accuracy. A complete methodology for such adaptive testing of mixed-signal/RF circuits is developed in this paper. Simulation results and hardware measurements are used to demonstrate the efficacy of the proposed techniques.

In the recent past, Physically Unclonable Functions (PUFs) have been proposed as a way of implementing security in modern ICs. PUFs are hardware designs that exploit the randomness in silicon manufacturing processes to create IC-specific signatures for silicon authentication. While prior PUF designs have been largely digital, in this work we propose a novel PUF design based on transfer function variability of an analog push-pull amplifier under process variations. A differential amplifier architecture is proposed with digital interfaces to allow the PUF to be used in digital as well as mixed-signal SoCs. A key innovation is digital stimulus engineering for the analog amplifier that allows 2X improvements in the uniqueness of IC signatures generated over arbiter-based digital PUF architectures, while maintaining high signature reliability over +/- 10 % voltage and -20 to 120 degree Celsius temperature variation. The proposed PUF is also resistive to model building attacks as the internal analog operation of the PUF is difficult to reverse-engineer due to the continuum of internal states involved. We show the benefits of the proposed PUF through comparison with a traditional arbiter-based digital PUF using simulation experiments.

Insertion of malicious Trojans into outsourced chip manufacturing generally results in increased capacitances of internal circuit nodes that have been tapped for node controllability and observability by malicious circuitry. Current path delay measurement and side channel Trojan detection techniques are unable to detect Trojans that present low loading to such tapped circuit nodes, especially in the presence of large manufacturing process variations. In this paper, a high-resolution Trojan detection method for digital logic based on pulse propagation is developed. The method exhibits 25X -- 30X higher diagnostic resolution (ability to measure small capacitive loads on internal circuit nodes) as compared to current path delay based Trojan detection techniques in the presence of significant manufacturing process variations. Further, a key benefit is that theoretically, as opposed to path delay measurement based methods, the diagnostic resolution of the test approach is independent of circuit logic depth over and above the benefits already mentioned above. Test methods and test infrastructure compatible with existing scan based techniques are described. Simulation results are presented to prove the viability and effectiveness of the proposed Trojan detection scheme and especially for circuits with large logic depths (35-70 gates) suffering from worst case process variation effects.

As silicon integration complexity increases with 3D stacking and Through-Silicon-Via (TSV), so does the occurrence of memory and IO defects and associated test and validation time. This ultimately leads to an overall cost increase. On a 14nm Intel SOC, a reusable BIST engine called Converged-Pattern-Generator-Checker (CPGC) are architected to detect memory and IO defects, and combined with the software assisted repair technology to automatically repair memory cell defects on 3D stacked Wide-IO DRAM. Additionally, we also present the CPGC gate count, power, simulation, and silicon results. The reusable CPGC IP is designed to connect to a standard IP interface, which enables a quick turn-key SOC development cycle. Silicon results show CPGC can speed up validation by 5x, improve test time from minutes down to seconds, and decrease debug time by 5x including root-cause of boot failures of the memory interface. CPGC is also used in memory training and initialization, which makes it a critical part of Intel SOC.

As RF design scales to the 28nm technology node and beyond, pre-silicon simulation and verification of complex mixed-signal/RF SoCs is becoming intractable due to the difficulties associated with simulating diverse electrical effects and design bugs. As a consequence, there is increasing pressure to develop comprehensive post-silicon test and debug tools that can be used to identify design bugs and improve modeling of complex electrical nonidealities observed in silicon. Often, it is not known a-priori what these bugs are and how they can be modeled, significantly complicating the debug process. In this research, a new atomic model learning approach is proposed that uses supervised learning techniques to diagnose design bugs and learn unknown module-level behaviors. Nonideality modeling artifacts called model atoms are inserted into different nodes of the design signal flow paths to learn unknown behaviors along those paths. Under the assumption that the design bug is localized, it is shown that the source of the bug can be identified with high resolution even when the nature of the bug is unknown. The method has been applied to a conventional wireless as well as a polar radio transmitter and key results that demonstrate usefulness and feasibility of the proposed approach are presented.

With trends in mixed-signal systems-on-chip indicating increasingly extreme scaling of device dimensions and higher levels of integration, the tasks of both design and device validation is becoming increasingly complex. Post-silicon validation of mixed-signal/RF systems provides assurances of functionality of complex systems that cannot be asserted by even some of the most advanced simulators. We introduce RAVAGE (from “random;” “validation;” and “generation”), an algorithm for generating stimuli for post-silicon validation of mixed-signal systems. The approach of RAVAGE is new in that no assumption is made about any design anomaly present in the DDT; but rather, the stimulus is generated using the DUT itself with the objective of maximizing the effects of any behavioral differences between the DUT (hardware) and its behavioral model (software) as can be seen in the differences of their response to the same stimulus. Stochastic test generation is used since the exact nature of any behavioral anomaly in the DUT cannot be known a priori. Once a difference is observed, the model parameters are tuned using nonlinear optimization algorithms to remove the difference between its and the DUT's responses and the process (test generation→tuning) is repeated. If a residual error remains at the end of this process that is larger than a predetermined threshold, then it is concluded that the DUT contains unknown and possibly malicious behaviors that need further investigation. Experimental results on an RF system (hardware) are presented to prove feasibility of the proposed technique.

Due to the use of scaled technologies, high levels of integration and high speeds of today's mixed-signal SoCs, the problem of validating correct operation of the SoC under electrical bugs and that of debugging yield loss due to unmodeled multi-dimensional variability effects is extremely challenging. Precise simulation of all electrical aspects of the design including the interfaces between digital and analog circuitry, coupling across power and ground planes, crosstalk, etc., across all process corners is very hard to achieve in a practical sense. The problem is expected to get worse as analog/mixed-signal/RF devices scale beyond the 45nm node and are more tightly integrated with digital systems than at present. In this context, a post-silicon validation methodology for analog/mixed-signal/RF SoCs is proposed that relies on the use of special stimulus designed to expose differences between observed DUT behavior and its predictive model. The corresponding error signature is then used to identify the likely "type" of electrical bug and its location in the design using nonlinear optimization algorithms. Results of trial experiments on RF devices are presented.

Modern RF circuits suffer from increased electrical degradation induced by electrical stress and thermal effects due to the high speeds of operation and the effects of technology scaling. Detection of such degradation is important, particularly in wireless basestations which must operate round-the-clock with high dependability. In this paper, a new approach for detecting degradation in RF transmitter systems using pilot symbols is proposed and is superior to prior algorithms because degradation can be monitored on a frame-to-frame basis independent of the data being transmitted. The response of the RF transmitter to known pilot symbols is captured at the output of the RF power amplifier using an envelope detector and is fitted to a third order transmitter model using a model-parameter solving algorithm. It is shown that the computed model parameters deviate away from their nominal values, exhibiting model anomalies once nonidealities due to electrical degradation start affecting transmitter behavior. The amount of the degradation is proportional to the magnitude of this deviation as measured by a distance metric and is easily computed using simple algorithms running on the baseband processor. Preliminary results indicate the feasibility and low cost of the proposed approach.