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Bo-Ru Ke

dblp:54/10063 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2011
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 50% Hardware reliability and fault tolerance · 25% Storage systems · 25%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance › error correction
error-correcting codes		 0.112011
Reliability analysis and improvement for multi-level non-volatile memories with soft information · DAC 2011
Storage systems › data representation › data encoding › error correction coding
LDPC codes		 0.112011
Reliability analysis and improvement for multi-level non-volatile memories with soft information · DAC 2011
Memory systems › non-volatile memory › multi-level cell
multi-level cell memory		 0.112011
Reliability analysis and improvement for multi-level non-volatile memories with soft information · DAC 2011
Memory systems
non-volatile memory		 0.112011
Reliability analysis and improvement for multi-level non-volatile memories with soft information · DAC 2011

Methods — techniques the papers use, named apart from their topics

soft information · 0.1non-uniform reference voltages · 0.1LDPC codes · 0.1
YearPublicationVenuePosition
2011 Reliability analysis and improvement for multi-level non-volatile memories with soft information
abstract
This paper presents the systematic methodology of error correction scheme using low-density parity check (LDPC) codes to improve the reliability and endurance of multi-level cell (MLC) non-volatile memories. Using our realistic error model, the LDPC architecture with the scheme of non-uniform reference voltages (NURV) is proposed to trade off among error correction capability, area, and throughput, which can improve the bit-error-rate significantly.
Shih-Liang Chen, Bo-Ru Ke, Jian-Nan Chen, Chih-Tsun Huang
 DAC2