Fault tolerance is a crucial operational aspect of biological systems and the self-repair capabilities of complex organisms far exceeds that of even the most advanced electronic devices. While many of the processes used by nature to achieve fault tolerance cannot easily be applied to silicon-based systems, in this paper we show that mechanisms loosely inspired by the operation of multicellular organisms can be transported to electronic systems to provide self-repair capabilities. Features such as dynamic routing, reconfiguration, and on-chip reprogramming can be invaluable for the realization of adaptive hardware systems and for the design of highly complex systems based on the kind of unreliable components that are likely to be introduced in the not-too-distant future. In this paper, we describe the implementation of fault tolerant features that address error detection and recovery through dynamic routing, reconfiguration, and on-chip reprogramming in a novel application specific integrated circuit. We take inspiration from three biological models:phylogenesis, ontogenesis,andepigenesis(hence the POE in POEtic). As in nature, our approach is based on a set of separate and complementary techniques that exploit the novel mechanisms provided by our device in the particular context of fault tolerance.

The complexity exhibited by pervasive systems is constantly increasing. Customer electronics devices provide day to day a larger amount of functionalities. A common approach for guaranteeing high performance is to include specialized coprocessor units. However, these systems lack flexibility, since one must define, in advance, the coprocessor functionality. A solution to this problem is to use run-time reconfigurable coprocessors, exploiting the advantages of hardware while keeping a flexible platform. In this paper, we describe a self-reconfigurable pervasive platform containing a dynamically reconfigurable cryptographic coprocessor. As case-study, we consider three ciphering algorithms and we compare the performance of the coprocessor against a full-software implementation. The number of ciphering algorithms can be infinitely extended using a remote server

Besides the numeric variables which are common in fuzzy modeling, some variables involved in the description of specific behaviors are categorical. Such variables are discrete, have no order a-priori, and most of the time handle a large amount of values (e.g., genes, proteins, countries, religions, etc.). This paper proposes a methodology for the fuzzification of categorical variables which could make part of a larger fuzzy modeling approach. The proposed solution allows to automatically create fuzzy membership functions for nominal categorical variables. We study some parameters so as to better assess their possible effect on the final outcome of the whole fuzzy modeling process.

This paper presents a genetic fuzzy system approach to control a nonlinear dynamic model of the HIV infection. The system is conceived to find mamdani fuzzy controllers that are capable of boosting the immune response while reducing the impact on the body because of the use of potentially toxic medicaments. General aspects of the used approach are described while special emphasis is given to the evolutionary mechanism. The best solution found from several evolutionary runs is analyzed in terms of control and interpretability issues.

In spite of the high parallelism exhibited by cellular automata architectures, most implementations are usually run in software. For increasing execution parallelism, hardware implementations on FPGAs have been proposed, under the cost of being un-flexible, and inefficient in terms of resource utilization. In this paper, we present a platform for evolving CA by exploiting the partial re-configurability of current commercial FPGAs. Our implementation includes an on-chip soft-processor that generates a partial bitstream, reconfigures the FPGA, and computes the fitness. After finding a good individual, the evolved CA can be used as a peripheral for performing useful computation. As case study we present CA co-evolution for a random number generator and for the firefly synchronization problem

This paper presents an FPGA-based implementation of a co-processing unit able to parse context-free grammars of real-life sizes. The application fields of such a parser range from programming language syntactic analysis to very demanding natural language applications where parsing speed is an important issue.

Describes a networked FPGA-based implementation of the FAST (Flexible Adaptable-Size Topology) architecture, an artificial neural network (ANN) that dynamically adapts its size. Most ANN models base their ability to adapt to problems on changing the strength of the interconnections between computational elements according to a given learning algorithm. However, constrained interconnection structures may limit such ability. Field programmable hardware devices are very well adapted for the implementation of ANNs with in-circuit structure adaptation. To realize this implementation, we used a network of Labomat-3 boards (a reconfigurable platform developed in our laboratory), which communicate with each other using TCP/IP or a faster direct hardware connection.

Labomat 3 is a reconfigurable platform for teaching and research purposes developed by our laboratory. The main features of the board are: (1) a microprocessor associated with two mid-range FPGAs, (2) a powerful multitasking real-time operating system including a JavaVM, (3) easy to use design tools, and (4) a networking interface. In this paper we describe the hardware and software of the board as well as some application domains.

Article Free Access Share on A FPGA-based hardware implementation of generalized profile search using online arithmetic Authors: Emeka Mosanya Logic Systems Laboratory, Swiss Federal Institute of Technology, INN Ecublens. CH-1015 Lausanne, Switzerland Logic Systems Laboratory, Swiss Federal Institute of Technology, INN Ecublens. CH-1015 Lausanne, SwitzerlandView Profile , Eduardo Sanchez Logic Systems Laboratory, Swiss Federal Institute of Technology, INN Ecublens. CH-1015 Lausanne, Switzerland Logic Systems Laboratory, Swiss Federal Institute of Technology, INN Ecublens. CH-1015 Lausanne, SwitzerlandView Profile Authors Info & Claims FPGA '99: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arraysFebruary 1999 Pages 101–111https://doi.org/10.1145/296399.296436Published:01 February 1999Publication History 2citation434DownloadsMetricsTotal Citations2Total Downloads434Last 12 Months6Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Field-programmable gate arrays (FPGAs) are large, fast integrated circuits-that can be modified, or configured, almost at any point by the end user. Within the domain of configurable computing, we distinguish between two modes of configurability: static-where the configurable processor's configuration string is loaded once at the outset, after which it does not change during execution of the task at hand, and dynamic-where the processor's configuration may change at any moment. This paper describes four applications in the domain of configurable computing, considering both static and dynamic systems, including: SPYDER (a reconfigurable processor development system), RENCO (a reconfigurable network computer), Firefly (an evolving machine), and the BioWatch (a self-repairing watch). While static configurability mainly aims at attaining the classical computing goal of improving performance, dynamic configurability might bring about an entirely new breed of hardware devices-ones that are able to adapt within dynamic environments.

RENCO is a reconfigurable network computer based on a Motorola 68360 processor for the conventional part, and four Altera Flex 10K130 or 10K250 FPGAs for the reconfigurable part. Therefore, the user has at his/her disposal up to one million programmable logic gates for executing his/her applications in a custom-made processor. RENCO runs a real-time operating system and a Java virtual machine.

We describe the hardware implementation of the ProfileScan algorithm, a very sensitive method to discover distant biomolecular sequence relationships. This is part of the GENSTORM project, aimed at providing a dedicated computer for biological sequence processing based on FPGAs.

No abstract available.

No abstract available.

The growth and the operation of all living beings are directed through the interpretation, in each of their cells, of a chemical program, the DNA string or genome. This process is the source of inspiration for the Embryonics (embryonic electronics) project, whose final objective is the conception of very large scale integrated circuits endowed with properties usually associated with the living world: self-repair (cicatrization) and self-replication. We begin by showing that any logic system can be represented by an ordered binary decision diagram (OBDD), and then embedded into a fine-grained field-programmable gate array (FPGA) whose basic cell is a multiplexer with programmable connections. The cellular array thus obtained is perfectly homogeneous: the function of each cell is defined by a configuration (or gene) and all the genes in the array, each associated with a pair of coordinates, make up the blueprint (or genome) of the artificial organism. In the second part of the project, we add to the basic cell a memory and an interpreter to, respectively, store and decode the complete genome. The interpreter extracts from the genome the gene of a particular cell as a function of its position in the array (its coordinates) and thus determines the exact configuration of the relative multiplexer. The considerable redundancy introduced by the presence of a genome in each cell has significant advantages: self-replication (the automatic production of one or more copies of the original organism) and self-repair (the automatic repair of one or more faulty cells) become relatively simple operations. The multiplexer-based FPGA cell and the interpreter are finally embedded into an electronic module; an array of such modules make it possible to demonstrate self-repair and self-replication.

If one considers life on Earth since its very beginning, three levels of organization can be distinguished: the phylogenetic level concerns the temporal evolution of the genetic programs within individuals and species, the ontogenetic level concerns the developmental process of a single multicellular organism, and the epigenetic level concerns the learning processes during an individual organism's lifetime. In analogy to nature, the space of bio-inspired hardware systems can be partitioned along these three axes-phylogeny, ontogeny and epigenesis (POE)-giving rise to the POE model. This paper is an exposition and examination of bio-inspired systems within the POE framework, with our goals being: (1) to present an overview of current-day research, (2) to demonstrate that the POE model can be used to classify bio-inspired systems, and (3) to identify possible directions for future research, derived from a POE outlook. We discuss each of the three axes separately, considering the systems created to date and plotting directions for continued progress along the axis in question.

As the number of applications combining hardware and software steadily grows, the need for tools dedicated to co-design and co-synthesis is becoming more and more urgent. In this paper, we describe two platforms designed to prototype this kind of application and to serve as a basis for the development and test of CAD tools. The first platform, called LOPIOM, consists of a microcontroller, four FPGA and four interconnection circuits and can be used to prototype complex systems. The second, LABOMAT, is used as a basic prototyping and teaching platform. The architecture and the software environment developed for these cards is described along with some applications.

If reconfigurable processors are to become widely used, we will need tools to help conventional programmer use them. In particular, a single high-level language should be used to program the whole application; both the part which will become the hardware configuration and the part which remains software. Spyder is a reconfigurable processor with configurable execution units. The C++ language has been chosen as the source language to program this processor. In this paper we present a compiler capable of synthesizing the hardware configuration of FPGA execution units from C++ source code. The same source code can be compiled by a standard C++ compiler for simulation purposes. First estimates show that this approach leads to very short synthesize time as compared to VHDL synthesizer for a similar quality of the generated hardware.

A low power, event-driven microprocessor, called PUNCH, has been conceived, realized and commercialized in Switzerland. In this paper we present a development and prototyping system for PUNCH, composed of two main parts: an emulator and a monitor. The emulator is an implementation of the PUNCH architecture using Actel FPGA circuits, on a NuBus format card hosted by a Macintosh computer. The monitor is a program running on the Macintosh, allowing symbolic debugging (display and modification of the resources of the processor, as well as control of the execution of the applications).

A superscalar processor with three execution units is described in details in this paper. The execution units are implemented using reprogrammable field-programmable gate array (FPGA) chips, allowing the user to configure them to best fit the application. Each instruction, composed of 128 bits, directly controls all the processor resources, in a horizontal microprogramming way.>

The concept of binary decision trees is extended to include multiple output Boolean functions. A systematic and programmable method is then developed for the minimization of trees realizing multiple output incompletely specified functions. Further simplification of minimal trees can be achieved through state reduction methods to obtain subminimal decision algorithms. Possible physical realizations of decision trees and algorithms as well as their applications are discussed.