Occupancy monitoring in public transportation has become a focal point due to its implications for service optimization and passenger comfort. This paper presents a device-free human presence detection method using Ultra-wideband (UWB) radar sensors to estimate seat-level occupancy in buses. The system leverages the impact of human bodies on Radio Frequency (RF) signal propagation, utilizing Angle of Arrival (AoA) and Channel Impulse Response (CIR) data from two ceiling-mounted dual-antenna UWB radars. Seating areas are spatially divided into rows and columns for classification, based on which two classification models are developed: a Naïve Bayes classifier based on AoA data and a Random Forest model based on raw CIR data. Experimental results show that the AoA-based Naïve Bayes model achieves classification accuracies of 67.1% for column prediction and 83.2% for row prediction at a per-pulse level, while consistently outperforming the CIR-based Random Forest models by correctly identifying four out of five evaluated positions when aggregating several predictions over time. The findings suggest that deriving compact and interpretable AoA features from raw CIR data leads to better performance for the seat-level classification task. This approach supports scalable deployment and encourages further exploration of AoA-based methods for complex scenarios such as multi-person localization.

Chemical–mechanical planarization (CMP) is a critical and complex process in semiconductor manufacturing, where high precision and tight tolerances demand sophisticated process control. Machine learning (ML) has emerged as a promising tool to support this need. However, the literature is fragmented across domains and often lacks concrete guidance on deploying ML methods in real-world CMP environments. This review addresses that gap and provides actionable insights for both academic researchers and industrial practitioners. This work systematically analyzes peer-reviewed publications at the intersection of ML and CMP. It offers three significant contributions: First, it provides a detailed assessment of the types and sources of data used in CMP-related ML studies, distinguishing between equipment-level data, process-level data, and product-level data. Second, it introduces a structured classification of ML applications across four key areas: Research and Development, Real-Time Process Control, Equipment Health Monitoring, and Post-Process Feedback and Analysis. Third, it synthesizes commonly reported challenges along the data science pipeline. Where available, practical solutions and implementation strategies are discussed. Across these areas, existing studies illustrate ML’s potential to, among other things, enable more adaptive control, reduce metrology demands, enhance defect detection, and support layout- and process-aware design optimization, highlighting its growing role in CMP process innovation. The review concludes by outlining open research gaps and proposing future directions, including the development of benchmark datasets, integration of domain knowledge, and extension of modeling efforts to additional targets such as dishing and within-wafer non-uniformity. While focused on CMP, many challenges discussed, such as data leakage, sparse target labeling, and hybrid modeling, are relevant across engineering informatics. Addressing them in CMP can inform the broader development of robust and adaptable ML systems in intelligent manufacturing.

OmpSs is an OpenMP-like directive-based programming model that includes heterogeneous execution (MIC, GPU, SMP, etc.) and runtime task dependencies management. Indeed, OmpSs has largely influenced the recently appeared OpenMP 4.0 specification. Zynq All-Programmable SoC combines the features of a SMP and a FPGA and benefits DLP, ILP and TLP parallelisms in order to efficiently exploit the new technology improvements and chip resource capacities. In this paper, we focus on programmability and heterogeneous execution support, presenting a successful combination of the OmpSs programming model and the Zynq All-Programmable SoC platforms.

OmpSs is a directive-based programming model that uses OpenMP-like directives, that allow to execute the tasks annotated on both the SMPs and as FPGA kernels on modern SoC processors, like the Xilinx Zynq platform. OmpSs includes the support for accelerators (MIC, GPUs, FPGAs) and task dependencies, like OpenMP 4.0 will support. In this paper we present our approach for the support of FPGAs and the Zynq SoC, the current status of the implementation, its analysis and performance evaluation.

Digital pre-distortion (DPD) is an advanced digital signal-processing technique that mitigates the effects of power amplifier (PA) nonlinearity in wireless transmitters. DPD plays a key role in providing efficient radio digital front-end (DFE) solutions for 3G/4G basestations and beyond. Modern FPGAs are a promising target platform for the implementation of flexible wireless DFE solutions, including DPD. In this paper, we present a software programmable design flow that facilitates the implementation and integration of efficient DPD solutions on Xilinx's Zynq All Programmable SoC, combining industry-standard embedded processors and programmable logic fabric into one chip. In addition to software programmability, another key contribution of this design flow is the flexible partitioning of functionality among hardware and software components, depending on the complexity of the DPD parameter estimation algorithm in use. We have applied processor-specific optimizations to the software implementation and used the Vivado High-Level Synthesis (HLS) tool as the design tool for the programmable logic. Using this design flow, we integrated a complete DPD feedback path on the Zynq SoC that achieves up to 7x speed-up from hardware acceleration.

This paper describes the implementation of an FPGA prototype of an application based on embedded ASIC technology. The overall goal is to implement a system that can monitor an Ethernet data stream and extracts configuration data marked by the EtherType field in the Ethernet header. For evaluation the application is implemented on a prototype consisting of two XILINX FPGA boards. Since the target platform is an ASIC with embedded reconfigurable architectures the prototype is divided in the corresponding parts. One board emulates the embedded reconfigurable architecture that contains the Ethernet MAC. Ethernet packets can reconfigure this MAC. The second board emulates the static part of the application that controls the reconfiguration process.

In this paper we present the hardware implementation of a Particle Filter for location estimation. Based on distance information to static network nodes, the filter estimates the three-dimensional position of a mobile network node. The design has been derived from a set of formal operation properties and synthesized for an FPGA prototype platform. Accessed through a serial interface, it can be used as a location estimation core from microcontrollers with low computational power. The implemented models for state transition and measurements can be re-parameterized during operation. Due to the chosen design approach these models can also easily be modified or exchanged in order to match the application needs. The correct functionality of the implementation has been shown using real time-of-flight based distance measurements. Therefore, the prototype platform has been integrated in an existing IEEE 802.15.4a compliant wireless network infrastructure.

Formal executable specification is one in the ITRS 2007 design report proposed solution to handle future design challenges. Specifications have to be checked for completeness and consistence. Furthermore, it is desirable to support later design steps by generating descriptions for simulation and synthesis, properties for simulative and formal verification and testing scripts. This can be achieved by using formal specification. During development the results of the design steps have to be fed back in the specification tool in order to track changes and the progress of the development. In this paper we present a specification tool which combines formal specification with requirements engineering to achieve a consistent and traceable specification.

An ever increasing portion of design effort is spent on functional verification. The verification space as the set of possible combinations of a design’s attributes is likely to be very large making it infeasible to verify each point in this space. State-of-the-art verification tools tackle this problem by using directed random generation of combinations in conjunction with manually defined corner cases in order to get satisfactory coverage with the desired distribution. In this work, the underlying methodology to automatically generating complete sets of disjoint coverage models on the basis of formal attribute definitions is extended to take relational constraints into account. This allows the utilization of coverage models with non-orthogonal, non-planar boundaries, which can make hole analysis for coverage data obsolete. It shall be demonstrated, how the proposed methodology can be used to automatically determine corner cases more accurately than it is possible with conventional approaches.