Time-Sensitive Networking (TSN) extends Ethernet to enable deterministic networking making it suitable for latency-sensitive industrial applications. To ensure bounded end-to-end delays and minimal jitter, a network-wide communication schedule with exclusively reserved transmission slots is enforced for time-triggered hard realtime traffic. While numerous scheduling methodologies exist for generating such schedules, their practical applicability remains uncertain. In this paper, we present a testbed for evaluating the real-world suitability of TSN schedules. We describe the hardware and software setup and demonstrate our evaluation methodology.

In Time-Sensitive Networking (TSN), Time-Aware Shaping facilitates the convergence of deterministic and lowpriority traffic in Ethernet networks. The allocation of bandwidth for low-priority traffic is crucial when scheduling timetriggered (TT) streams to prevent starvation and packet loss caused by queue congestion. This issue is particularly pertinent in online scheduling scenarios, where the deletion of streams can lead to schedule fragmentation. To prevent this issue, the time slots of the TT streams must be compressed to provide larger contiguous gaps for low-priority traffic in the schedule. In this paper, we present a novel heuristic approach for compressing schedules, which facilitates the grouping of time slots into units, thereby increasing the bandwidth for low-priority traffic and improving the schedulability of future streams. The proposed heuristic can be tailored to specific use cases through adaptive weighting, allowing a comprehensive evaluation of time slots according to the properties of the associated time slot units, TT streams, and the network.

Time-Sensitive Networking (TSN) is a key technology for converged industrial communication systems enabling the integration of traffic with diverse Quality of Service (QoS) requirements such as timeliness, throughput, and reliability. To ensure that all data streams meet their requirements, the Network Calculus (NC) allows to analytically derive worst-case performance estimations. In this paper, we model rate-constrained streams alongside time-triggered hard real-time traffic in a line topology. Additionally, we compare the analytical results with a simulation conducted in the OMNeT++ network simulator. Our comparison shows that the worst-case delay predicted by the NC is 3 to 4 times higher than the delay observed in a simulation. Similarly, the estimated backlog (i.e., the amount of data queued in TSN switches) is $\mathbf{2}$ to $\mathbf{3}$ times larger than the simulation results.

In the modern world, accurate crowd counting is integral to a multitude of applications, including urban planning, transportation management, and crowd control. The advent of opportunistic communication networks, which enable devices to sporadically exchange data in a decentralized fashion, has introduced a new set of challenges in crowd estimation. This paper delves into two opportunistic people counting protocols: UrbanCount and HeartBeatCount. UrbanCount, while a robust protocol in its own right, comes with certain limitations that hinder its real-world applicability. In response to these limitations, this paper introduces refinements to UrbanCount, making it more practical and effective. Additionally, a novel protocol called HeartBeatCount is presented, which significantly enhances crowd size estimation accuracy, particularly in sparse scenarios. Through an evaluation, we compare the performance of these protocols and conclude that HeartBeatCount offers a more resilient solution for opportunistic people counting in various real-world scenarios.

Time-Sensitive Networking (TSN) facilitates the implementation of realtime data traffic with deterministic delay and jitter in Ethernet networks. In its time-triggered communication variant, network paths as well as transmission time slots along the paths need to be planned and reserved for all data streams, respectively. Conventionally, such a feasible (i. e., realtime compliant) network schedule is computed and optimized offline, installed upon deployment, and cannot be changed anymore at runtime without stopping the communication. The latter becomes unsuitable for future industrial use cases with a growing demand for flexibility including schedule adjustments. In this paper, we present an online scheduler capable to incrementally integrate new streams at runtime and to adapt the existing schedule, if necessary, while retaining the realtime guarantees given to active streams. For this purpose, the scheduling heuristic identifies streams whose adjustment requires minimal reconfiguration efforts. In a thorough evaluation, we analyze the scheduler's trade-off between resource usage and schedule quality showing its suitability for diverse application scenarios.

Time-Sensitive Networking (TSN) disrupts realtime communication technology by making IEEE Ethernet realtime-capable. For time-triggered, hard realtime traffic, TSN provides standardized mechanisms to reserve communication paths as well as individual transmission time slots for data frames. By leveraging these means in a precomputed network schedule, TSN allows for bounded end-to-end delays and minimal jitter. Not being part of the IEEE standard, corresponding scheduling algorithms are an active field of research. Unfortunately, due to differing model assumptions, evaluation setups, and key metrics, a fair comparison of schedulers is impossible so far. In this paper, we present a systematic and reproducible approach to benchmark TSN schedulers. First, we provide a scheduler taxonomy that enables to cluster schedulers by their characteristics. Second, we analyze interactions of input parameters and scheduler results to derive a benchmarking parcour for quantitative comparisons. Finally, we use the approach to benchmark existing schedulers and show subtle interaction effects. This way, our approach enables—for the first time-comparability between schedulers, fueled by the public availability of our benchmarking scenarios.

SSD-based block-level caches can notably increase the performance of HDD-based storage systems. However, this demands a sensible choice of the cache block size, which depends strongly on the workload characteristics. Many workloads will most likely favor either small or large cache blocks. Unfortunately, choosing the appropriate cache block size is difficult due to the diversity and dynamics of storage workloads. Thus, adapting the cache block size to the workload characteristics at run time has the potential to substantially improve the cache performance compared to using a fixed cache block size. However, changing the used cache block size for all cached data is very costly and neglects that distinct parts of the data may exhibit different access patterns, which favor distinct cache block sizes.In this paper, we experimentally study the performance impact of the cache block size and fine-grained adaptation, i.e., for individual parts of the data, between small and large cache blocks in write-back SSD caches. Based on our results, we make two major observations on the performance impact of the cache block size and its adaptation. First, using an inappropriate cache block size can reduce the overall throughput by up to 84% compared to using the most suitable cache block size. Second, fine-grained adaptation between small and large cache blocks is highly beneficial as it avoids such a performance deterioration, whereas it can increase the overall throughput by up to 126% in comparison to using the more suitable fixed cache block size.

Future applications of the Industrial Internet of Things will increasingly depend on the timely exchange of information and data. Time-Sensitive Networking, which is currently being standardized, therefore extends switched Ethernet networks by realtime communication capabilities offering deterministic message delays. In its time-triggered communication variant, a network path needs to be planned for each realtime data flow and corresponding transmission time slots have to be reserved on the network links along that path. In this paper, we present the first joint mathematical model for path routing and time slot scheduling that combines multicast support with an individual transmission scheduling on each link along a flow's path. We provide a formalization as an Integer Linear Programming (ILP) problem and discuss several optimizations to significantly reduce the ILP solver's runtime without affecting the solution quality. In a thorough evaluation, we show the applicability of our approach and analyze the effects and trade-offs of different objective functions.

Due to a notably higher cost per bit of storage capacity, NAND flash memory solid state drives (SSDs) are not expected to completely replace hard disk drives (HDDs) in the near future. Using SSDs as a cache for HDDs, however, proved very effective in increasing the performance of storage systems. The performance increase depends strongly on both the SSD cache design and the workload applied to the storage system. However, distinct parts of the data may exhibit significantly different access patterns that potentially change rapidly and unpredictably over time. This particularly applies to complex dynamic systems, such as virtualized environments. Existing SSD cache architectures are not able to exploit such differences in access patterns, as they only use a single cache design, even when adapting certain cache parameters.In this paper, we propose a novel generic architecture for adaptive block-level SSD caches that simultaneously employs multiple SSD caches with complementary designs. The goal is to use for each kind of access pattern the SSD cache design that fits the pattern best. Results of our experimental evaluation show that the proposed SSD cache architecture adapts to different workloads well. For a broad range of workloads, it provides an overall throughput that is comparable to the respective best single cache design, whereas it is able to outperform these cache designs for superimposed mixed workloads and workloads with changing characteristics.

Writing correct and efficient parallel programs is hard. A lack of overview leads to errors in control- and dataflow, e.g., race conditions, which are hard to find due to their nondeterministic nature. In this paper, we present a graphical programming model for parallel stream processing applications, which improves the overview by visualizing high level dataflow together with explicit and concise annotations for concurrency-related dependency information. The key idea of our approach is twofold: First, we present a powerful graphical task editor together with annotations that enable the designer to define stream properties, task dependencies, and routing information. These annotations facilitate fine-granular and correct parallelization. Second, we propose seamless integration with the safe parallel programming language Rust by providing automated code structure generation from the graphical representation, design patterns for common parallel programming constructs like filters, and a scheduling and runtime environment. We demonstrate the applicability of our approach with a network-based processing system as it is typically found in advanced firewalls.

Tracing and profiling low-level kernel functions (e.g. as found in the process scheduler) is a challenging task, though, necessary in both research and production in order to acquire detailed insights and achieve peak performance. Several kernel functions are known to be not traceable because of architectural limitations, whereas tracking other functions causes side effects and skews profiling results.

The growing computational power of modern CPUs allows increasingly complex signal processing applications to be successfully implemented and executed on general-purpose processors and operating systems. In this regard, the application's architecture, its design, and operating system integration directly affect the maximal achievable processing bandwidth. In this paper, we present alternative driver architectures for signal processing applications that differ in the distribution of processing stages between kernel space and user space. Using the processing of ADS-B air traffic radio signals for civil aviation as case study, we evaluate the performance of the design alternatives on a Linux system and quantify their strengths and weaknesses with respect to data overhead, usage of vector units, applicable compiler optimizations, and cache behavior. Based on our results, we determine the best design choice and derive guidelines for the development of efficient signal processing applications.