Reconfigurable Intelligent Surfaces (RISs) are emerging as a key technology for enhancing wireless communications in smart city environments, offering robust, low-latency connectivity. This paper presents the design of an adaptive control system based on high-voltage, mixed-signal integrated circuits for controlling tunable RISs, tailored for wireless cellular communications in urban areas. The proposed system enables enhanced programmability by dynamically steering beams and fine-tuning signal reflections through the precise control of varactor diodes embedded within the RIS unit cells. This flexible system architecture supports real-time software reconfiguration, allowing RIS units to adapt to varying network conditions and scale seamlessly across smart city infrastructures. Simulated results on a 0.35 μm CMOS high voltage process technology demonstrate the circuit's ability to achieve low power consumption and high reconfiguration speed across a wide temperature range. The control electronics are separated from the RIS panels, this way enabling tiling of multiple surfaces for scalable, cost-effective deployment. This approach offers a promising pathway to meeting the growing demand for seamless, high-speed, and energy-efficient connectivity in next-generation smart city applications, including vehicular networks, Internet of Things, smart traffic management and smart infrastructure.

Reconfigurable intelligent surfaces (RISs) are recognized as a fundamental enabler for improving energy efficiency in 6G and future networks. However, the power consumption and the reconfiguration delay still need improvement for what is required at GHz frequencies, thus delaying their commercial adaptation. On that regard, this study proposes the incorporation of Integrated Circuits (ICs) with MOS varactor loadings as part of the RIS framework, to improve power consumption and speed, while having precise tuning of the reflection phase for individual unit-cells. The presented circuit design features an asynchronous digital circuit responsible for transmitting binary streams to digital-to-analogue converters, which in turn, bias MOS varactors that are directly connected to each unit-cell within the RIS. The use of asynchronous digital control circuits facilitates the development of ultra-low power, high-speed ICs, thereby enhancing the dynamic scalability of the RIS system. Simulated results of the asynchronous circuit are presented on a mature, cost-effective, CMOS 0.18 μm process technology, showing static power consumption of 40,63 μW, dynamic energy consumption of 474.43 pJ and reconfiguration delay of 23.38 ns. The simulations are accompanied by a scalability analysis and a discussion of potential capabilities, offering valuable insights for the future of ICs on RIS systems. The proposed approach and circuit provide flexibility and performance to RIS systems not achievable with conventional control systems due to their benefits of using clockless networking communication.

Most FPGA-based Convolutional Neural Network (CNN) hardware accelerators target the datacenter rather than edge processing units. To further fill this gap, this work presents SqueezeJet-3 - a novel FPGA-based embedded system, consisting of software and hardware, for accelerating edge CNN inference. Even though SqueezeJet-3 is optimized for accelerating small ImageNet class CNNs, such as SqueezeNet v1.1, on low-end lowcost FPGA SoC devices, it can also be used for the acceleration of larger CNNs, such as the VGG16. Evaluation of our accelerator reveals better or comparable performance with that triggered by the current state-of-the-art similar tools and systems.

This paper introduces the use of a diode-connected MOSFET as a temperature controlled switch for trapped charge cancellation of ISFET sensors. The current flowing through the reverse-biased diodes of 2.7 aA is negligible at low temperature but reaches 23 fA when heated to 100°C, which allows for low temperature readout and high temperature compensation of trapped charge. The diode-connected device is tied to the floating gate of the ISFET which is integrated as part of a source-follower readout. The in-pixel feedback loop uses a comparator to turn off the polysilicon heaters once the offset has been cancelled, triggering the readout by switching the op amp into a buffer configuration. Simulations show that the system is calibrated in 35s and the output sensitivity reaches 27.74 mV/pH. The pixel output then tracks any ionic change at its surface without sensor offset.

Metamaterials and metasurfaces have given possibilities for manipulating electromagnetic (EM) waves that in the past would have seemed impossible. The majority of metasurface designs are suitable for a particular frequency and angle of incidence. One long-sought objective is the design of programmable metasurfaces to dynamically manipulate a variety of incoming EM frequencies and angles. In order to do this, a large-scale mesh of networked chips are required below the metasurface, which apart from adapting electrical impedance properties, also communicate with each other, thus relaying information about meta-atom settings, as well as forwarding possible distributed measurements taken. This paper describes why an asynchronous mixed-signal ASIC is advantageous for the control of scalable, EM absorbing, metasurfaces.

In this paper, we examine the use of ensemble methods in a multirobot task allocation environment. The aim is to enable a robot that needs to estimate the required resources to complete a task, to utilize information coming from other robots of the same type. To our knowledge, it is the first attempt made, to use such methods, to combine data of the same type, coming from data sets of different agents, to form a prediction. Knowledge exchange is not continuous, but only ad hoc. To merge data, we use ensemble models. This keeps communication needs to a minimum, as only the models themselves—and no actual data— need to be exchanged. To further reduce communication costs, the number of robots that contribute information is being limited. Finally, we make an attempt to see how well the concept we use would perform in other domains. This is to examine whether the approach could yield the same results in other domains, or it is limited to the task allocation problem, as formulated in Tolmidis and Petrou (Eng. Appl. Artif. Intell., 2013;26(5–6):1458–1468) . For this, we selected two additional, different, publicly available data sets.

Pose estimation is a major requirement for any augmented reality (AR) application. Cameras and inertial measurement units (IMUs) have been used for pose estimation not only in AR but also in many other fields. The level of accuracy and pose update required in an AR application is more demanding than in any other field. In certain AR applications, (maintenance for example) a small change in pose can cause a huge deviation in the rendering of the virtual content. This misleads the user in terms of an object location and can display incorrect information. Further, the huge amount of processing power required for the camera based pose estimation results in a bulky system. This reduces the mobility and ergonomics of the system. This demonstration shows a fast pose estimation using a camera and an IMU on a mobile platform for augmented reality in a maintenance application.

A technique is proposed for integrating a probabilistic graph construction algorithm with an evolutionary multiobjective optimizer. A hybrid planner (EvoVBPR) for nonholonic robotic vehicle is presented. It integrates a probabilistic roadmap construction method (VBPR) with the SPEA2 evolutionary multiobjective algorithm and an additional deterministic graph pruning step. The result is a Pareto set of roadmaps that represent different tradeoffs between length of path and obstacle clearance.

This paper presents a robot system incorporating vision and force/torque sensing for handling of flat textile materials. Experimentation is used to draw conclusions concerning the performance of standard arms and sensing techniques. Also requirements of such systems are discussed.

A model for an index sequential file employing multiple overflow chains per bucket is developed. This model is used to analyse the effects of insertions and deletions on the cost of successful and unsuccessful search in terms of block accesses. Numerical results are obtained illustrating the performance. The performance is also compared with that of an ISAM file using only one overflow chain per bucket.