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Xiaogang Qiu

dblp:54/1771 · DBLP profile ↗
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22ranked-venue papers
6as first author
4since 2021 · last 2023
0000-0001-7757-3374ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 7 · 6 first-authorArtificial intelligence and machine learning · 6 · 2 since 2021Human-computer interaction and ubiquitous computing · 5Applied, interdisciplinary, general and emerging computing · 5 · 1 since 2021Software engineering, systems software and programming languages · 2 · 2 first-authorDatabases, data management, data science and information retrieval · 2 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
6 papers
Memory systems · 89% Processor architecture and microarchitecture · 9% Performance modeling and evaluation · 2%

Topics — the 16 heaviest of 16, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › memory management
virtual memory
0.252008
The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches · IEEE Trans. Computers 2008
Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors · IEEE Trans. Parallel Distributed Syst. 2005
Tolerating Late Memory Traps in Dynamically Scheduled Processors · IEEE Trans. Computers 2004
Memory systems › memory management › virtual memory
address translation
0.232008
The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches · IEEE Trans. Computers 2008
Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors · IEEE Trans. Parallel Distributed Syst. 2005
Options for Dynamic Address Translation in COMAs · ISCA 1998
Memory systems › memory hierarchy
cache hierarchy
0.122008
The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches · IEEE Trans. Computers 2008
Towards Virtually-Addressed Memory Hierarchies · HPCA 2001
Memory systems › cache › cache organization
virtual cache
0.112008
The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches · IEEE Trans. Computers 2008
Processor architecture and microarchitecture
out-of-order execution
0.012004
Tolerating Late Memory Traps in Dynamically Scheduled Processors · IEEE Trans. Computers 2004
Memory systems › cache design
virtually-indexed cache
0.012001
Towards Virtually-Addressed Memory Hierarchies · HPCA 2001
Memory systems › memory management › virtual memory › address translation
TLB
0.012008
The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches · IEEE Trans. Computers 2008
Processor architecture and microarchitecture
instruction-level parallelism
0.011999
Tolerating Late Memory Traps in ILP Processors · ISCA 1999
Memory systems
memory hierarchy
0.011999
Tolerating Late Memory Traps in ILP Processors · ISCA 1999
Memory systems › memory architecture
cache-only memory architecture
0.011998
Options for Dynamic Address Translation in COMAs · ISCA 1998
Memory systems › memory management › virtual memory › address translation › TLB
TLB design
0.011998
Options for Dynamic Address Translation in COMAs · ISCA 1998
Memory systems › non-uniform memory access
CC-NUMA
0.012005
Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors · IEEE Trans. Parallel Distributed Syst. 2005
Performance modeling and evaluation › simulation
simulation-based evaluation
0.012004
Tolerating Late Memory Traps in Dynamically Scheduled Processors · IEEE Trans. Computers 2004
Memory systems
processing-in-memory
0.012001
Towards Virtually-Addressed Memory Hierarchies · HPCA 2001
Processor architecture and microarchitecture › pipelining
pipeline performance
0.011999
Tolerating Late Memory Traps in ILP Processors · ISCA 1999
Memory systems › memory architecture
multiprocessor memory system
0.011998
Options for Dynamic Address Translation in COMAs · ISCA 1998

Methods — techniques the papers use, named apart from their topics

simulation · 0.2architecture comparison · 0.1synonym lookaside buffer · 0.0TLB replacement · 0.0tagged store buffer · 0.0hardware prefetching · 0.0deferred traps · 0.0design space exploration · 0.0
YearPublicationVenuePosition
2023 Text Detection Model for Historical Documents Using CNN and MSER
abstract
This article introduces a text detection model for historical documents images. The handwritten characters in historical documents are always difficult to detect because they contain fuzzy or missing ink, or weathering features and stains; these features will seriously affect the detection accuracy. In order to reduce the influence mentioned above, an effective ATD model is proposed to detect the textbox of characters in historical documents image, and ATD model includes a CNN-based text-box generation network and an NMS-based MSER text-box generation model. As a post-processing method, a text merging algorithm is proposed to achieve higher detection accuracy. The test results on historical document datasets such as Yi, English, Latin, and Italian datasets show that the method in this paper has good accuracy, and it has taken a solid step for the detection of historical documents.
Rankang Li, Shanxiong Chen, Fujia Zhao, Xiaogang Qiu
J. Database Manag.4
2023 Understanding the Necessity and Economic Benefits of Lockdown Measures to Contain COVID-19
abstract
Since the outbreak of the coronavirus disease 2019 (COVID-19), the issue of how to maintain economic development while containing the epidemic has become a significant concern for decision-makers. Though lockdown measures are verified to be very effective in containing the epidemic, its economic costs and other influences have not been fully explored. As a result, decision-makers in many countries are still hesitant to include the lockdown measure in an intervention strategy in response to COVID-19. To address this issue, we propose a universal computational experiment approach for policy evaluation and adjustment based on the Artificial societies, Computational experiments, Parallel execution (ACP) concept. First, we innovatively construct a model via observable CO2 emissions, which is able to estimate the economic costs affected by nonpharmaceutical interventions. Furthermore, based on the population movement data, a risk source model is proposed to estimate the local transmission risk for any prefectures outside the epicenter. Finally, we integrate the data models in a high-resolution agent-based artificial society and carry out large-scale computational experiments supported by the Tianhe supercomputer. Policy adjustments and evaluations are carried out in four cities: Wenzhou, Guangzhou, Beijing, and Wuhan. Our research findings show important implications for policy-making: 1) the local transmission of a city can be almost contained if lockdowns are adopted immediately when the risk index is larger than 1.645, 1.960, or 2.576 at the 90%, 95%, or 99% confidence interval, respectively; 2) if lockdowns are required, in-advance lockdown measures facilitate mitigation efficacy and reduce economic loss; and 3) lockdowns lasting for 7–14 days in a prefecture would be effective in controlling the spread of the epidemic. The duration of the measure should be prolonged with the increment of the initial transmission risk.
Zhengqiu Zhu, Chuan Ai, Bin Chen 0003, Wei Duan 0002, Xiaogang Qiu, Xin Lu 0002, Zhiming Zhao, Zhong Liu 0002
IEEE Trans. Comput. Soc. Syst.6
2022 Radical-based extract and recognition networks for Oracle character recognition
Shanxiong Chen, Fujia Zhao, Xiaogang Qiu
Int. J. Document Anal. Recognit.4
2022 Correction to: Radical-based extract and recognition networks for Oracle character recognition
Shanxiong Chen, Fujia Zhao, Xiaogang Qiu
Int. J. Document Anal. Recognit.4
2018 The national geographic characteristics of online public opinion propagation in China based on WeChat network
Chuan Ai, Bin Chen 0003, Lingnan He, Kaisheng Lai, Xiaogang Qiu
GeoInformatica5
2017 QoS-aware parallel job scheduling framework for simulation execution as a service
abstract
Cloud computing is attracting an increased number of researches in delivering modeling and simulation abilities as a service. Among which, simulation execution as a service (EaaS) is a hot spot. It aims at releasing users from complex running configurations and meanwhile guaranteeing the QoS requirements. Under the motivation, focusing on EaaS for parallel and distributed simulation (PADS) application, the paper proposes a QoS-aware job scheduling framework in two-tier virtualization-based private cloud data center. In PADS EaaS, an adaptive job size adjustment component is designed to realize intelligent and adaptive job size setting for PADS instead of assigning by users. Furthermore, an adaptive deadline-aware job size adjustment algorithm, named ADaSA, is designed in the adjustment component to realize efficient job scheduling with high job responsiveness. ADaSA algorithm firstly computes a minimum processor requested that leads to maximum runtime stretch. It makes sure that more jobs can be scheduled at the same time while satisfying current job's deadline requirements. On other hand, ADaSA tries to pick up all possible idle CPU time in background virtual machines and reserved ones for other jobs. Through that way, more chances are generated to response more jobs in waiting queue. Finally, we conduct extensive experiments with trace-driven simulation. The results show that ADaSA outperforms both cloud-based job scheduling algorithm KCEASY and traditional EASY in terms of response time (up to 90%) and bounded slow down (up to 95%), and at the same time guarantees approximately equivalent deadline-missed rate. ADaSA also outperforms two representative moldable scheduling algorithms in terms of deadline-missed rate (up to 60%).
Zhen Li 0009, Bin Chen 0003, Xiaocheng Liu, Dandan Ning, Wei Duan 0002, Xiaogang Qiu, Chengda Xu
DS-RT6
2017 Real-time data driven simulation of air contaminant dispersion using particle filter and UAV sensory system
abstract
Real-time prediction of the air contaminant dispersion is an important issue in hazard assessment and emergency management of air pollution. The conventional atmospheric simulation can seldom give the precise prediction results due to inaccurate input parameters. To improve the accuracy of the prediction of atmospheric model, a real-time data driven atmospheric dispersion simulation based on data assimilation is proposed by applying particle filer to the Gaussian puff based model. The coefficients of dispersion in this model are selected as the system state variables and updated by assimilating observed data into the model in real time. To obtain high-quality observed data, a UAV-based air contaminant sensory system is developed. Two experiments are designed and implemented to verify the performance of the method. The results show that the method proposed can update the model parameters and improve the accuracy of prediction results effectively.
Rongxiao Wang, Bin Chen 0003, Sihang Qiu, Zhengqiu Zhu, Xiaogang Qiu, Wei Duan 0002
DS-RT6
2017 Online robot identification by differentiating abnormal behaviors of WeChat users
abstract
The identification of online robot is important for managing the internet order, such as forbidding spam, fictitious information, and inductive words published by online robot to mislead the public. We studied the behaviors of the WeChat users to identify online robot, including turning pages, scanning the web, and forwarding posts. In fact, the amount and time interval of information forwarding were applied to differentiate the abnormal behaviors of WeChat users. Furthermore, we employed information entropy to measure the amount and time interval of information forwarding of WeChat users. The results indicate that the amount of online robot is much less than normal users. What's more, online robots' behavior is abnormal apparently and this identification method is effective.
Jian Dong 0002, Wei Duan 0002, Bin Chen 0003, Xiaogang Qiu
SMC4
2015 Accelerating Large Scale Artificial Society Simulation with CPU/GPU Based Heterogeneous Parallel Method
abstract
Artificial society is an effective way for social science research. However, in order to meet real-time and super real-time requirement of computational experiment, the execution efficiency of large-scale artificial society then becomes the burning question. The emergence of heterogeneous parallel system offers opportunities and challenges for accelerating large scale artificial society simulation. How to fully utilize heterogeneous computational resources in large scale agent based simulation becomes the key issue. The paper proposes a CPU/GPU-based accelerating computational method, in which GPU is fully utilized in two different ways at the same time. Firstly GPU is treated as host processor, and a GPU based simulation kernel is designed to execute the models collaboratively with CPU simulation kernel. Secondly, in order to accelerate the domain-specific models, a specific domain-oriented GPU simulation computational service component is proposed, and GPU is used as a co-processor to offer domain-specific parallel optimization. A SPMT (Single Process Multi Threads) based conservative parallel simulation framework is proposed to integrate the GPU simulation kernel and computational service component. At last, an experiment is designed to test the efficiency of GPU based simulation kernel, and argues about the application mode of GPU.
Zhen Li 0009, Bin Chen 0003, Xiaogang Qiu
DS-RT4
2015 Agent-based Modeling of Large-scale Complex Social Interactions
abstract
Modeling complex human social interactions is an important part in agent-based social simulation research. For example, results of interactions (negotiations) for scheduling joint social activities could influence the future plans of the involved individuals, which has a great impact on the researches such as activity-based travel demand analysis and agent-based epidemic models. To describe these interactions is a rather difficult task than it may seem, in particular when the system has a very large scale (millions of individuals). Current research efforts ignore or simplify the negotiation/coordination part of the social interactions in order to reduce complexity, either by using fixed and predefined human daily schedules as input or by constraining the joint social activities (interaction purposes) into several specific types (e.g. eating out). In this paper, we describe an agent-based approach to model large-scale complex social interactions, by which individuals can discuss the duration and location of the coming social activities and make decisions about their attendance. We conducted a simulation experiment including nearly 20 million agents with complex social interactions on the basis of dynamic generation of friendship networks to realize this approach, and the simulation results comply with some social interaction phenomena.
Mingxin Zhang 0003, Alexander Verbraeck, Rongqing Meng, Xiaogang Qiu
SIGSIM-PADS4
2015 Mathematical and computational approaches to epidemic modeling: a comprehensive review
Wei Duan 0002, Zongchen Fan, Xiaogang Qiu
Frontiers Comput. Sci.5
2014 Individual Decision Making Can Drive Epidemics: A Fuzzy Cognitive Map Study
abstract
Existing studies on the propagation of infectious diseases have not sufficiently considered the uncertainties that are related to individual behavior and its influence on individual decision making to prevent infections, even though it is well known that changes in behavior can lead to variations in the macrodynamics of the spread of infectious diseases. These influencing factors can be categorized into emotion-related and cognition-related components. We present a fuzzy cognitive map (FCM) denotative model to describe how the factors of individual emotions and cognition influence each other. We adjust the weight matrix of causal relationships between these factors by using a so-called nonlinear Hebbian learning method. Based on this FCM model, we can implement individual decision rules against possible infections for disease propagation studies. We take the simulation of influenza A [H1N1] spreading on a campus as an example. We find that individual decision making against infections (frequent washing, respirator usage, and crowd contact avoidance) can significantly decrease the at-peak number of infected patients, even when common policies, such as isolation and vaccination, are not deployed.
Shan Mei, Yifan Zhu 0013, Xiaogang Qiu, Zhenghu Zu, Alexander Boukhanovsky, Peter M. A. Sloot
IEEE Trans. Fuzzy Syst.3
2013 An ACP Approach to Public Health Emergency Management: Using a Campus Outbreak of H1N1 Influenza as a Case Study
abstract
In order to tackle the infeasibility of building mathematical models and conducting physical experiments for public health emergencies in the real world, we apply the Artificial societies, Computational experiments, and Parallel execution (ACP) approach to public health emergency management. We use the largest collective outbreak of H1N1 influenza at a Chinese university in 2009 as a case study. We build an artificial society to simulate the outbreak at the university. In computational experiments, aiming to obtain comparable results with the real data, we apply the same intervention strategy as that was used during the real outbreak. Then, we compare experiment results with real data to verify our models, including spatial models, population distribution, weighted social networks, contact patterns, students' behaviors, and models of H1N1 influenza disease, in the artificial society. In the phase of parallel execution, alternative intervention strategies are proposed to control the outbreak of H1N1 influenza more effectively. Our models and their application to intervention strategy improvement show that the ACP approach is useful for public health emergency management.
Wei Duan 0002, Zhidong Cao, Youzhong Wang, Bin Zhu 0007, Daniel Dajun Zeng, Fei-Yue Wang 0001, Xiaogang Qiu, Hongbin Song
IEEE Trans. Syst. Man Cybern. Syst.7
2012 Backfilling under Two-tier Virtual Machines
abstract
The cloud computing paradigm attracts increasing amount of efforts to move high performance parallel applications to run in remote data centres. How to balance the performance requirements of parallel applications and the data centre utilization is essential to the move. Existing parallel scheduling mechanisms normally do not consider workload consolidation for improving server utilization. In this paper, we propose a two-tier architecture to organize virtual machines for workload consolidation. The two-tier virtual machines have different CPU priorities. We give a parallel job scheduling algorithm called Two EASY, which extends EASY algorithm, to take care of the job responsiveness in such an architecture. Our extensive experiments show that TwoEASY significantly outperforms the commonly used EASY algorithm in a datacentre setting. The method is practical and effective for consolidating parallel workload in datacentres.
Xiaocheng Liu, Chen Wang 0008, Xiaogang Qiu, Bing Bing Zhou, Bin Chen 0003, Albert Y. Zomaya
CLUSTER3
2012 Fostering artificial societies using social learning and social control in parallel emergency management systems
Wei Duan 0002, Xiaogang Qiu
Frontiers Comput. Sci.2
2011 A Game-Engine-Based Platform for Modeling and Computing Artificial Transportation Systems
abstract
A game-engine-based modeling and computing platform for artificial transportation systems (ATSs) is introduced. As an important feature, the artificial-population module (APM) is described in both its macroscopic and microcosmic aspects. In this module, each person is designed similarly to the actors in games. The traffic-simulation module (TSM) is another important module, which takes advantage of Delta3D to construct a 3-D simulation environment. All mobile actors are also managed by this module with the help of the dynamic-actor-layer (DAL) mechanism that is offered by Delta3D. The platform is designed as agent-oriented, modularized, and distributed. Both modules, together with components that are responsible for message processing, rules, network, and interactions, are organized by the game manager (GM) in a flexible architecture. With the help of the network component, the platform can be constructed to implement a distributed simulation. Finally, four experiments are introduced to show functions and features of the platform.
Qinghai Miao, Fenghua Zhu, Changjian Cheng, Xiaogang Qiu
IEEE Trans. Intell. Transp. Syst.6
2008 The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches
abstract
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this current approach faces mounting problems. This paper introduces new ideas to enable the use of virtual addresses in the cache hierarchy. The major idea is the replacement of the on-chip TLB by a synonym lookaside buffer (SLB). The SLB translates synonyms into a primary virtual address, which is a unique identifier resolving all ambiguities due to synonyms in the memory system. We introduce various system configurations with SLBs and discuss all functional issues associated with them. An SLB is much more scalable than a regular TLB. It scales with memory data set sizes, physical memory sizes and number of cores in a multiprocessor. Moreover SLB entry flushes and shootdowns due to physical memory management are eliminated. We show performance data resulting from the simulation of several applications as diverse as scientific computing, database, and JAVA virtual machines. These evaluations target SLB miss rates and flushes as well as the impact of the SLB on cache miss rates. They show that small SLBs of 8-16 entries are sufficient to solve the synonym problem in virtual caches and that their performance overhead is negligible.
Xiaogang Qiu, Michel Dubois 0001
IEEE Trans. Computers1
2005 Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors
abstract
To support a global virtual memory space, an architecture must translate virtual addresses dynamically. In current processors, the translation is done in a TLB (translation lookaside buffer), before or in parallel with the first-level cache access. As processor technology improves at a rapid pace and the working sets of new applications grow insatiably, the latency and bandwidth demands on the TLB are difficult to meet, especially in multiprocessor systems, which run larger applications and are plagued by the TLB consistency problem. We describe and compare five options for virtual address translation in the context of distributed shared memory (DSM) multiprocessors, including CC-NUMAs (cache-coherent non-uniform memory access architectures) and COMAs (cache only memory access architectures). In CC-NUMAs, moving the TLB to shared memory is a bad idea because page placement, migration, and replication are all constrained by the virtual page address, which greatly affects processor node access locality. In the context of COMAs, the allocation of pages to processor nodes is not as critical because memory blocks can dynamically migrate and replicate freely among nodes. As the address translation is done deeper in the memory hierarchy, the frequency of translations drops because of the filtering effect. We also observe that the TLB is very effective when it is merged with the shared-memory, because of the sharing and prefetching effects and because there is no need to maintain TLB consistency. Even if the effectiveness of the TLB merged with the shared memory is very high, we also show that the TLB can be removed in a system with address translation done in memory because the frequency of translations is very low.
Xiaogang Qiu, Michel Dubois 0001
IEEE Trans. Parallel Distributed Syst.1
2004 Tolerating Late Memory Traps in Dynamically Scheduled Processors
abstract
In the past few years, exception support for memory functions such as virtual memory, informing memory operations, software assist for shared memory protocols, or interactions with processors in memory has been advocated in various research papers. These memory traps may occur on a miss in the cache hierarchy or on a local or remote memory access. However, contemporary, dynamically scheduled processors only support memory exceptions detected in the TLB associated with the first-level cache. They do not support memory exceptions taken deep in the memory hierarchy. In this case, memory traps may be late, in the sense that the exception condition may still be undecided when a long-latency memory instruction reaches the retirement stage. In this paper we evaluate through simulation the overhead of memory traps in dynamically scheduled processors, focusing on the added overhead incurred when a memory trap is late. We also propose some simple mechanisms to reduce this added overhead while preserving the memory consistency model. With more aggressive memory access mechanisms in the processor we observe that the overhead of all memory traps - either early or late - is increased while the lateness of a trap becomes largely tolerated so that the performance gap between early and late memory traps is greatly reduced. Additionally, because of caching effects in the memory hierarchy, the frequency of memory traps usually decreases as they are taken deeper in the memory hierarchy and their overall impact on execution times becomes negligible. We conclude that support for memory traps taken throughout the memory hierarchy could be added to dynamically scheduled processors at low hardware cost and little performance degradation.
Xiaogang Qiu, Michel Dubois 0001
IEEE Trans. Computers1
2001 Towards Virtually-Addressed Memory Hierarchies
abstract
Current cache hierarchies are indexed in parallel with a TLB but their tags are part of the physical address so that the memory hierarchy is physically addressed. This design faces problems as more concurrency is exploited in the processor core and as the memory demand of emerging applications is growing fast. The traditional TLB does not scale well inside the processor core and its hit rate call be poor for data-intensive applications or scientific applications without much locality. At the same time, given current trends towards computing in memory and in communication interfaces, virtual addresses are needed not just inside the processor but throughout the memory hierarchy. These observations have prompted us to result the problem of moving virtual address translation away from the processor. This paper introduces new ideas to enable the use of virtual addresses throughout the memory hierarchy. The major idea is the replacement of the TLB with a small Synonym Lookaside Buffer (SLB), which scales well because its size depends on the number of addresses, and not on the size of the application or of the physical memory. We also characterize synonym usage, evaluate the amount of cache and SLB flushing due to remapping of addresses, and compare the miss rate of various virtual physical cache organizations for several application domains. These evaluations show that virtually addressed memory hierarchies overall have better performance behavior than physically-addressed memory hierarchies. Finally, we also show how virtually-addressed memory hierarchies facilitate natural, scalable multiprocessor extensions, as well as computing-in-memory in the context of general-purpose computers.
Xiaogang Qiu, Michel Dubois 0001
HPCA1
1999 Tolerating Late Memory Traps in ILP Processors
abstract
ILP processors can execute a large number of instructions at the same time. Thus it becomes more and more difficult to support traps efficiently. On the other hand a current trend in architecture is to support various memory functions in software rather than hardware, usually by trapping the execution processor on a cache miss, TLB miss or a failed access to a local or remote memory. These late memory traps block the faulty instruction at the top of the active list, backing up the pipeline. Moreover the support for late memory traps may affect the performance of non-faulting memory instructions as well. In this paper we analyze the overhead caused by late memory traps in ILP processors and define several measures for this overhead. In order to tolerate late memory traps, we propose hardware prefetching of exception conditions and a tagged store buffer to implement deferred traps on stores. We show that, with these hardware optimizations, the overhead added by the lateness of traps is significantly reduced relative to the overhead of early traps. Because of caching effects the frequency of late memory traps usually decreases as they are taken deeper in the memory hierarchy and their overall impact on the execution time becomes negligible.
Xiaogang Qiu, Michel Dubois 0001
ISCA1
1998 Options for Dynamic Address Translation in COMAs
abstract
In modern processors, the dynamic translation of virtual addresses to support virtual memory is done before or in parallel with the first-level cache access. As processor technology improves at a rapid pace and the working sets of new applications grow insatiably the latency and bandwidth demands on the TLB (Translation Lookaside Buffer) are getting more and more difficult to meet. The situation is worse in multiprocessor systems, which run larger applications and are plagued by the TLB consistency problem. We evaluate and compare five options for virtual address translation in the context of COMAs (Cache Only Memory Architectures). The dynamic address translation mechanism can be located after the cache access provided the cache is virtual. In a particular design, which we call V-COMA for Virtual COMA, the physical address concept and the traditional TLB are eliminated. While still supporting virtual memory, V-COMA reduces the address translation overhead to a minimum. V-COMA scales well and works better in systems with large number of processors. As a machine running on virtual addresses, V-COMA provides a simple and consistent hardware model to the operating system and the compiler, in which further optimization opportunities are possible.
Xiaogang Qiu, Michel Dubois 0001
ISCA1