Demo Data from EDBT 2026 / reviewers in the wild / expert
K. G. Shin
dblp:54/180
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1992
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Reconfigurable computing and FPGAs · 33% Hardware reliability and fault tolerance · 33% Integrated circuit design · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware reliability and fault tolerance › reconfiguration
fault-tolerant reconfiguration |
0.0 | 1 | 1992 | Restructuring WSI hexagonal processor arrays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992 |
Reconfigurable computing and FPGAs › reconfigurable architecture
reconfigurable arrays |
0.0 | 1 | 1992 | Restructuring WSI hexagonal processor arrays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992 |
Integrated circuit design › VLSI design
wafer-scale integration |
0.0 | 1 | 1992 | Restructuring WSI hexagonal processor arrays · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992 |
Methods — techniques the papers use, named apart from their topics
spare cell allocation · 0.0reconfiguration algorithms · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1992 | Restructuring WSI hexagonal processor arraysabstractA host-driven reconfiguration scheme, called HEX-REPAIR, is proposed for hexagonal processor arrays characterized by a large number of relatively simple cells. Such arrays have been shown to be the most efficient for many digital signal processing applications, such as matrix multiplication, and for some classes of filtering operations. Reconfiguration for these arrays is made difficult by the asymmetric nature of the interconnection network and the need for keeping the switching overheads at a minimum. The algorithm presented meets these requirements. In addition, it has excellent fault-coverage characteristics, even in the presence of multiple faults, and can accommodate multiple rows/columns of spare cells. The restructured array is transparent to users and no modification is required in any application program using the array.> Raja Venkateswaran, Pinaki Mazumder, K. G. Shin |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |