Demo Data from EDBT 2026 / reviewers in the wild / expert
Haiyan Lin
dblp:54/1817
· DBLP profile ↗
2ranked-venue papers
2as first author
1since 2021 · last 2026
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 1 · 1 first-author · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Interdisciplinary, comprehensive, and emerging computing
1 paper |
Bioinformatics and computational biology · 100% | |
| Artificial intelligence
1 paper |
Efficient and distributed learning · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Bioinformatics and computational biology
DNA storage |
1.0 | 1 | 2026 | FedDNA: DNA Sequence Reconstruction via Deep Evidential Learning and Personalized Federated Aggregation · AAAI 2026 |
Bioinformatics and computational biology › sequence analysis
sequence reconstruction |
1.0 | 1 | 2026 | FedDNA: DNA Sequence Reconstruction via Deep Evidential Learning and Personalized Federated Aggregation · AAAI 2026 |
Machine learning › Efficient and distributed learning
federated learning |
0.3 | 1 | 2026 | FedDNA: DNA Sequence Reconstruction via Deep Evidential Learning and Personalized Federated Aggregation · AAAI 2026 |
Machine learning › Efficient and distributed learning › federated learning
personalized federated learning |
0.3 | 1 | 2026 | FedDNA: DNA Sequence Reconstruction via Deep Evidential Learning and Personalized Federated Aggregation · AAAI 2026 |
Hardware accelerators and domain-specific architectures
systolic array |
0.0 | 1 | 1985 | VLSI Systolic Array Architecture for Real-Time Digital Signal Processing · RTSS 1985 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1985 | VLSI Systolic Array Architecture for Real-Time Digital Signal Processing · RTSS 1985 |
Methods — techniques the papers use, named apart from their topics
uncertainty decomposition · 2.0mamba · 2.0evidential deep learning · 2.0LSTM · 2.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | FedDNA: DNA Sequence Reconstruction via Deep Evidential Learning and Personalized Federated AggregationabstractDNA-based data storage offers an attractive alternative to traditional media due to its exceptional density, durability, and sustainability. However, errors introduced across the DNA storage pipeline critically impede accurate sequence reconstruction from noisy sequencing reads. This paper addresses the DNA sequence reconstruction problem by proposing FedDNA, a novel Personalized Federated Learning (PFL) framework based on Evidential Deep Learning (DEL), designed for DNA storage environments. FedDNA quantifies robust predictive uncertainty through a novel evidence fusion mechanism that aggregates evidence from each noisy read in a cluster, thereby enhancing client-level prediction reliability. For efficient sequence modeling and reconstruction from these noisy clusters, its architecture employs a convolution-enhanced Mamba encoder and an LSTM decoder. To address prohibitive centralized training costs, privacy concerns, and data heterogeneity across diverse DNA storage data, FedDNA integrates PFL and designs an innovative uncertainty-driven personalized aggregation strategy based on epistemic and aleatoric decomposition, for which we also provide rigorous theoretical generalization bounds. Experimental results demonstrate FedDNA achieves superior reconstruction performance on DNA storage data with heterogeneity, highlighting its potential for secure and efficient DNA storage systems. Haiyan Lin, Zixuan Qin, Yuping Duan |
AAAI | 1 |
| 1985 | VLSI Systolic Array Architecture for Real-Time Digital Signal Processing
Haiyan Lin, Wei Yueming |
RTSS | 1 |