An overview of test generation approaches to maximize power supply noise is provided and issues related to and research directions for generation of test vectors with representative power are discussed. In particular, to facilitate the early design and validation of the power delivery network (PDN), the need for automatic high-level test generation to create functionally representative vectors that cause worst-case power events, which stress the power grid, is described.

Recently, assertion based verification or property checking has become of great interest to the industry. Property checkers attempt either to prove that a specified property, which stipulates expected design behavior, holds or, if the property does not hold, to generate a counter-example that demonstrates a violation of the property. This is another area where there have been some promising successes in recent years, with sequential ATPG techniques finding their way into commercial property checking tools.

This paper describes a novel method that can be used to reduce test cycle count in a parallel access scan based built-in-self-test (BIST) environment. An algorithm that allows the efficient application of deterministically generated patterns is proposed. This approach allows BIST fault coverage to be increased using deterministic vectors, while minimizing the cost, in terms of test cycles, of applying the vectors.

To meet the challenges involved in designing systems on silicon, IC designers are increasingly adopting a design re-use methodology, in which pre-designed logic modules, often called virtual components (VC) or intellectual property (IP) cores, are integrated together to construct system chips. Testing such increasingly complex systems comprising components that may be “black-boxes” is a major problem. The panel will discuss the challenges associated with testing system chips containing a diverse range of pre-designed VCs and will address the question of whether there are viable solutions today. It will discuss the impact of design re-use on test methodologies and will discuss whether the time to market gains offered by design re-use will be realized without test re-use. It will examine the role of scan, BIST, at-speed testing etc. as virtual component test techniques, and will discuss the issues involved in providing test access to facilitate test re-use. It will debate the impact of the SIA road-map on test requirements and will discuss the limitations in ATE that will have to be overcome and the issues in performance testing that will have to be addressed to test tomorrow's system chips. In addition, it will look at the role of standards (such as those being proposed by VSIA and IEEE) and discuss whether standardization is possible.

A system chip is defined as a complete system implemented on a single IC such that no peripheral chips are required. Thus, a system chip typically contains embedded core logic, embedded memory and analog components. A key enabling component of system chips is the re-use of existing design components sometimes called intellectual property cores or virtual components. Design re-use is narrowing the system chip design productivity gap but test and verification are now becoming the bottleneck. The key issues in testing core based system chips are how to optimally provide test access and test isolation to allow test methods and test vectors to be re-used for an embedded core, while ensuring that area, performance, test time and at-speed test requirements are met. While we are still in the early stages of developing a core test methodology that is widely accepted, two promising test re-use techniques are emerging: the test bus and test rail methods. Both approaches address the test bandwidth problem by allowing expandible test data access.

This paper describes a structured test re-use methodology and infrastructure for core-based system chips. The methodology is based on the use of a structured test bus framework that provides access to virtual components in a system chip allowing the test methodologies and test vectors for these components to be re-used. It addresses the test access, isolation, interconnect and shadow logic test problems without requiring modifications to the components, even for cores with more ports than chip pins. The test area overhead required, including test bus routing, to implement this methodology can be less than 1%.

In this paper test compaction techniques suitable for circuits designed using a novel parallel access scan methodology are proposed. In this methodology, groups of scan elements are addressed in parallel and the scan-in and scan-out operations are performed separately. The compaction techniques presented reduce the number of scan-in/out operations required by skipping scan operations that do not have an affect on fault coverage. The techniques allow the number of test cycles required to be reduced by up to 45% of that achieved using regular dynamic compaction techniques alone, and by up to 98% over that achieved using a single serial scan chain methodology. In addition, the techniques are suitable for both synchronous and asynchronous circuits.

A novel direct access test methodology that unifies the testing of pre-designed intellectual property blocks and custom user designed logic is proposed. This methodology allows the test logic and wiring used for testing custom logic to be shared for testing intellectual property using pre-computed test vectors. It provides parallel access to storage elements and so alleviates some of the issues found in serial access scan techniques. It also provides a novel solution to the non-scan element state retention problem found in single edge-triggered clock based serial scan approaches.

The competitive drive to reduce product development costs has led to a surge of interest in test methods that attempt to reduce costs. However, reducing test costs may not always result in the lowest product costs. Rather than attempting to reduce test costs as much as possible, the goal should be to maximize product profitability by finding the optimum test strategy that results in the quality levels desired for the lowest product cost and the highest product revenues.

This paper discusses delay fault test generation methodologies that avoid the area and performance overhead of enhanced scan elements by the use of scan and functional justification techniques. Issues with the use of scan justification and functional justification in a standard edge-triggered single clock scan environment are discussed. A functional justification based path delay test generator for circuits designed using standard scan elements is described. This test generator uses a calculus that allows circuits containing internal tri-state elements and bi-directional ports to be supported. Clock suppression techniques are employed to minimize state justification requirements.

Reducing "time to market" is one of the keys to success in an increasingly competitive business environment. Even a small delay in getting a product to market can have a significant negative impact on its profitability. A large proportion of the total design time for complex ASICs can be spent on test development. Therefore, test automation is becoming essential.>

This paper discusses a delay test methodology that avoids the area and performance overhead of enhanced scan elements by using a matrix of accessible storage elements. Delay test generation is performed for circuits, which may contain internal tri-state elements, bi-directional ports, asynchronous sets/resets and clock gating, using an automatic test pattern generator that is based on an extended 16 valued calculus.>

Discusses automatic test pattern generation (ATPG) for path delay faults in application specific integrated circuits (ASICs). An ATPG that uses a modified FAN algorithm to generate tests for critical paths derived using static timing analysis is described. The test generation procedure is optimised through the use of path constrainment and the concept of mandatory assignments.>

A symbolic simulation methodology that can be used to verify a set of standard scan-path-based, ad hoc, and boundary-scan design-for-testability (DFT) rules is proposed, and a DFT rule checker, TDRC (testability design rule checker), that uses this methodology is described. In this methodology, symbolic tokens are used to represent the types of signals applied to the primary inputs of the circuit, and, in a process analogous to simulation, these tokens are propagated through the circuit using a set of simulation rules. A check is then made to verify that the required tokens have been propagated to each scan element and that only allowed tokens have reached particular element and circuit ports. The proposed simulation methodology differs from previous path-tracing approaches in that symbolic tokens are propagated to the output of an object, possibly in modified form, depending on the other tokens reaching both the inputs and the logical function of the object. TDRC has been successfully used to identify real problems in real ASIC (application-specific integrated-circuit designs).>

This paper describes a Fast Signature Simulator (FSS) tool for Built-In Self-Testing (BIST) circuits. The FSS consists of a simulator generator and a compiled code simulator. The simulator generator comprises a controlling program called the EXECUTIVE and translation software called SIM-GEN. SIM-GEN accepts a Hardware Description Language (HDL) representation of the circuit-under-test as its input and produces C code simulation modules comprising Boolean relations that represent the structure of the circuit. These C code modules are then compiled and linked together to form the basis of the compiled code simulator. Simulation is invoked by executing the compiled C code description of the circuit. The simulation time is minimised by the use of parallel simulation techniques in conjunction with efficient functional models and novel mapping techniques for the LFSRs. Performances approaching 5 Million Gate Evaluations Per Second (GEPS) have been achieved using the FSS.