Resistive random-access memory (ReRAM)-basedprocessing-in-memory(PIM) accelerator is a promising platform for processing massively memory intensive matrix-vector multiplications of neural networks in parallel domain, due to its capability of analog computation, ultra-high density, near-zero leakage current, and nonvolatility. Despite many advantages, ReRAM-based accelerators are highly error-prone due to limitations of technology fabrication that lead to process variations and defects. These limitations degrade the accuracy of deep convolutional neural networks (CNNs) (Deep CNNs) running on PIM accelerators. While these CNNs accelerators are widely deployed in safety-critical systems, their vulnerability to fault is not well explored. In this article, we have developed a fault-injection framework to investigate the vulnerability of large-scale CNNs at both software- and hardware-level of inference phases. Faulty ReRAM devices are another reliability challenges due to significant degradation of classification accuracy when CNN parameters are mapped to the accelerators. To investigate this challenge, we map the CNN learning parameter to the ReRAM crossbar and inject faults into crossbar arrays. The proposed framework analyzes the impact ofstuck-at high(SaH) andstuck-at low(SaL) fault models on different layers and locations of CNN learning parameters. By performing extensive fault injections, we illustrate that the vulnerability behavior of ReRAM-based PIM accelerator for CNNs is greatly impressible to the types and depth of layers, the location of the learning parameter in every layer, and the value and types of faults. Our observations show that different models have different vulnerabilities to faults. Specifically, we show that SaL further reduces classification accuracy than SaH.

This paper proposes an efficient hardware framework that utilizes approximate computing units to mitigate the fault tree (FT) simulation time while considering accuracy and energy. To do so, first, we introduce two hybrid-precision computational units, which can operate in either accurate or approximate modes. Then, we utilize these computational units and an accuracy propagation technique to evaluate the desired accuracy level of each computational part. Finally, EARL, the proposed framework, by taking into account determined accuracy levels, in an offline stage through machine learning technique, predicts the best hardware platform (i.e., CPU, FPGA, or GPU) for executing each benchmark and provides a trade-off among simulation time, accuracy, and energy consumption. To demonstrate EARL's efficiency, we study the case of reliability calculation through fault tree analysis. However, EARL is useful in top-down structured computational problems. Our evaluations show that the proposed framework improves the simulation time and energy consumption of fault tree analysis on average by 78.1%, and 72.6%, respectively, with a negligible accuracy loss.

We investigate multi-criteria optimization and Pareto front generation. Given an application modeled as a Directed Acyclic Graph (DAG) of tasks and a multicore architecture, we produce a set of non-dominated (in the Pareto sense) static schedules of this DAG onto this multicore. The criteria we address are the execution time, reliability, power consumption, and peak temperature. These criteria exhibit complex antagonistic relations, which make the problem challenging. For instance, improving the reliability requires adding some redundancy in the schedule, which penalizes the execution time. To produce Pareto fronts in this 4-dimension space, we transform three of the four criteria into constraints (the reliability, the power consumption, and the peak temperature), and we minimize the fourth one (the execution time of the schedule) under these three constraints. By varying the thresholds used for the three constraints, we are able to produce a Pareto front of non-dominated solutions. We propose two algorithms to compute static schedules. The first is a ready list scheduling heuristic called Execution time, Reliability, POwer consumption and Temperature (ERPOT). ERPOT actively replicates the tasks to increase the reliability, uses Dynamic Voltage and Frequency Scaling to decrease the power consumption, and inserts cooling times to control the peak temperature. The second algorithm uses an Integer Linear Programming (ILP) program to compute an optimal schedule. However, because our multi-criteria scheduling problem is NP-complete, the ILP algorithm is limited to very small problem instances. Comparisons showed that the schedules produced by ERPOT are on average only 10 percent worse than the optimal schedules computed by the ILP program, and that ERPOT outperforms the PowerPerf-PET heuristic from the literature on average by 33 percent.

To overcome CMOS challenges including leakage power, volatility, scalability, and soft error vulnerability, Spin Transfer Torque Random Access Memory (STT-RAM) as a non-volatile memory has been utilized. Write error occurring because of variation in the fabrication process is one of the disadvantages of STT-RAM just like other devices. Given the fact that different current densities are required to write '1' and '0', in this paper, two different methods based on modification in write circuit are proposed: 1) dual source write circuit is proposed to decrease parallel write energy that leads to a noticeable decrement in power consumption, 2) the threshold voltage of active transistors in anti-parallel writing process is decreased to raise the temperature of the memory cell. This increment in Magnetic Tunneling Junction (MTJ) temperature leads to Write Error Rate (WER) reduction. In order to validate our results, functional simulations are performed and compared with the related works. Results approved power gain, performance improvement, and WER reduction by optimizing VDD and Vth values. We achieve 11.38% decrement in overall write time without any area or total power overhead.

By decreasing transistors feature size in nanoscale technology, the effect of soft error on combinational circuits has become a challenging problem as the particle strikes may lead to not only single event transients (SETs) but also multiple event transients (METs). In this paper, a cross-layer method is employed in order to achieve an effective way to reduce the occurrence rate of METs in combinational circuits. In the proposed method, at first, the desired circuit is synthesized and the sensitivity of each pair of cells with respect to METs is investigated through simulating and taking into account all three masking effects (electrical, logical, and temporal effects) at the gate level. Then, the circuit is placed and routed with the use of commercial CAD tools. Afterward, a cross-layer method is presented to estimate the soft error rate with respect to layout effect. Finally, by introducing a linear optimization problem, the unused space available on each row of the layout is distributed in the best way from the METs point of view. As a result, the multiple fault rate has been reduced 42.9% on average without having any area or performance overhead.

Although RRAM as an emerging non-volatile memory has solved many dr awbacks of conventional memor ies, it has deficiencies needed to be maintained. The objective of this paper is to suppress the soft er ror susceptibility of CMOSbased peripheral read circuits for both SLC and MLC crosspoint RRAM arrays thr ough sizing of tr ansistor s with regard to area, power, and delay constr aints. The results revealed that the soft err or r ate (SER) has improved around 18.4 and 53.7 times mor e than the default sizing in case of fully-robust sizing besides minor area overhead for both SLC and MLC RRAM ar r ays, respectively. However, the static power and delay of MLC ar r ay are the overheads.

MTJ-based logic-in-memory architecture, where MTJ memory elements with spin-injection write capability are distributed over a logic-circuit plane, is attractive design template to realize ultra-low-power and reduced interconnection delay. Moreover, because of advantages of MTJ cells i.e., large resistance ratio, virtually unlimited endurance, fast read/write accessibility, scalability, CMOS-process compatibility, non-volatility and robustness to soft errors, this architecture is expected to realize soft error robustness. In this paper, a robust logic-in-memory full adder architecture is designed based on susceptibility analyses which is done in previous papers.

This paper demonstrates on speeding up an accurate analysis of fault trees using stochastic logic through GPGPUs. Actually, probability models of dynamic gates and new accurate models for different combinations of cold spare gate e.g., two cold spare gates with a share spare and a cold spare gate with more than one spare inputs are developed in this paper. Experimental results show that on average, the proposed analysis method is 235 times faster than CPU simulation time. Moreover, proposing new stochastic models results accuracy and simplicity as additional advantages of the proposed method.

This paper presents a method to mitigate Negative Bias Temperature Instability (NBTI) in digital circuits. Since effect of NBTI strongly depends on digital logic value of internal nodes, this method uses internal nodes control (INC) method to reduce NBTI-critical transistors. There are some internal nodes in digital circuits that are under severe NBTI. This method at first, identifies NBTI-critical internal nodes in critical and non-critical paths by calculating probability of being under NBTI stress. Second, it eliminates these internal nodes by combining NBTI-sensitive gates and their driver gates, generating a new complex gate. These complex gates have the same logic and remove any NBTI-critical transistors. The proposed method reduces NBTI in combinational and sequential CMOS circuits and increases their lifetime. Experimental results on ISCAS'89 benchmark circuits show that NBTI-critical transistors, NBTI-induced delay degradation and the number of circuit's transistors are decreased about 86.1%, 15.12% and 4.3%, respectively. However, this method imposes area overhead of 0.2% for the investigated circuits.

This paper presents a method to detect and correct anomalies in embedded systems. The proposed method consists of three phases: 1) Training, 2) Anomaly detection, and 3) Anomaly Correction. In the training phase, the method constructs different clusters so that each cluster has a number of similar members, similarity values of the members for a cluster to each others are not less than a predefined similarity threshold. The similarity values are calculated by various similarity functions. During detection phase, if an event in testing data does not belong to any cluster, an anomaly is detected. In correction phase, some similarity functions are used which select a suitable sequence that meets the required constrains to be a normal sequence. Evaluation of the proposed method has been done based on correction coverage and hardware overheads such as power consumption, area, and delay overhead. The window size of corrector and the number of injected anomalies varied between 3 and 5, 1 and 7, respectively. The results of experiments on 7000 benchmarks show that this correction method can correct 70.36% of anomalies on the average. Power consumption, area, and delay overhead in cluster-based method are on average 318.47μw, 2.98μm2, and 0.09 ns, respectively.

The fully adaptive routing algorithms for Networks-On-Chip (NoC) based on number of packets held in a virtual channel (VC), can be classified into two main groups: 1) Traditional fully adaptive routing algorithms which only one packet reside in a VC at the same time. 2) Whole packet forwarding (WPF) which multiple packets can be resided in a VC. Based on an analysis, the WPF as regards multiple packets can be held in a VC, suffers from the full output buffer problem. This problem increases the overall input packet latency. In this paper, a fully adaptive routing algorithm is presented (MWPF). Compared with TFA and WPF, our design achieves an average 65.3% and 35.4% latency improvement, respectively. 38.4% and 24.3% saturation throughput improvement in the standard synthetic traffic pattern. Compared with WPF an average 26% and 61% maximum latency reduction on SPLASH-2 benchmarks running on a 49-core CMP. Our design also offers higher performance than partially adaptive and deterministic routing algorithms.

In this paper, a throughput-aware transient fault detection method is presented with respect to the features of server processors. The proposed method takes the advantages of combination of reconfigurable redundant execution-based fault detection and speculative fault detection. The reconfigurable redundant execution-based fault detection method by using configuration manager module couples two free adjacent cores on which a thread will be executed, and decouples them when resources are limited for normal execution. This method exploits unused resources in the multi-core processors to ensure high throughput reliable execution. The speculative fault detection method uses a history of block addresses requested form L1 cache to L2 cache during thread execution to find abnormal execution behavior. In order to evaluate the proposed method, the alpha processor model is utilized in the context of Gem5 simulator. The experimental results showed that 70% of injected faults can be detected with negligible hardware overhead.

This paper proposes a reliability-aware mapping technique for multi applications in networks-on-chip. The proposed technique consists of three main steps: 1) Generating a new core graph enriched by spares, based on a given application core graph, 2) Finding smallest rectangular region to place the given application using a heuristic algorithm, and 3) Searching the specified region into whole NoC, and selecting a region which results minimum overall performance and communication energy. Spare cores are connected to all vertices of application core graph and their edges are weighted by failure probability of processing cores assigned to the application and will be updated during mapping process. Many application core graphs are used to evaluate the proposed technique. The results of 100,000 fault injection experiments show communication energy reduction and performance improvement compared to well-known related techniques in both faulty and fault-free modes.

This paper presents a method based on stochastic logic to analyse fault trees. This method supports both static and dynamic gates, and can be applied to any type of fault trees. In this paper, static and dynamic gates would be translated into stochastic logic templates, and a hardware implementation for each gate would be achieved. Based on these hardware templates, it is possible to implement the whole logic on a Field-Programmable Gate Array (FPGA). Utilizing the stochastic logic for implementing a given fault tree on FPGA, the analysis would outperform the following parameters compared to traditional methods: 1) Speed-up, 2) Simplicity, 3) Reliability, and 4) Accuracy. Experimental results illustrate that using stochastic logic for modeling fault trees results in fast convergence of Monte Carlo simulation. Moreover, on average, our FPGA approach takes 50% of the time required by previous emulation approaches. Simplicity is an additional advantage of the proposed approach, achieved because of simplicity behind stochastic logic. Also, the stochastic logic is more reliable compared to traditional logic because any faults like SEUs in stochastic logic have less impact on the whole results compared to traditional arithmetic logic. To evaluate the proposed technique, the analysis is performed on several standard benchmarks composed of static and dynamic gates. The results obtained using this approach agree with those obtained from an analytical approach, which proves that the method is an accurate tool for system reliability modeling.

This paper presents a software-based error detection technique through monitoring flow of the programs in multithreaded architectures. This technique is based on the analysis of two key ideas: 1) Modifying the structure of traditional control-flow graphs used by control-flow checking methods so that they can be applied on multi-core and multi-threaded architectures. These achievements in designing control-flow error detectors lead to increase their applicability in current architectures. 2) Adjusting the locations of additional checking assertions in a given program in order to increase the ability of detecting possible control-flow errors along with significant reduction in overheads. The experimental results, through taking into account both detection coverage and overheads, demonstrate that on average about 94% of the control-flow errors can be detected by the proposed technique, more efficient compared to previous works.

This paper presents a software-based technique to recover control-flow errors using inherent redundancy in commodity multi-core processors. The proposed recovery technique is composed of two phases of control-flow error detection and control-flow error recovery. Previous research shows that modern superscalar microprocessors already contain significant amounts of redundancy. CFEs can be tolerated by leveraging existing microprocessors redundancy. Therefore, the cost of adding extra redundancy for fault tolerance is eliminated.

In this paper, First an analysis of the effects of transient faults using simulation-based fault injection is presented in System-on-Chip Wire (SoCWire) and then a fault-tolerant infrastructure is mentioned and results is reported. Different fault models such as dead clause, stuck then, micro-operation, crosstalk, dead process and SET (Single Event Transient) have been used to evaluate the transient faults' effects on SoCWire which is described in VHDL language. Besides, reported results in SoCWire show that about 47.67% of injected faults are latent; 41.71% of faults are recovered during simulation time and the remainders 10.61% of faults are effective that cause failure. The average of fault latency is 34. As it is illustrated later the percentage of failure is decreased in fault tolerant SoCWire.

In this paper, we present an adaptive SEU-tolerance method based on redundancy for implementing circuits in SRAM-based FPGAs to tolerate soft error effects. This method uses unused resources for partial redundancy based on a property of nets called System Failure Rate (SFR). SFR of a given net is the probability of system failure when the net is faulty. The redundancy is performed based on available resources, adaptively, so that system failure rate of circuit implemented in SRAM-based FPGAs decreases. We have investigated the effect of partial redundancy on several MCNC benchmarks. The results show that if maximum tolerable overall overhead is 20%, SFR increases up to 13%.

This paper presents a simulation-based fault injection analysis of a MIPS-based dual-core processor. In order to fulfill the requirement of this analysis, 114 different fault targets are used in various points of main components which are described in VHDL language; each experiment was repeated 50 times, resulting in 5700 transient faults in this simulation model. The experimental results demonstrate that, depending on the fault injection targets and the benchmark characteristics, fault effects vary significantly. On average, up to 35.2% of injected faults are recovered in simulation time, while 52.6% of faults lead to system failure, and the remaining 12.2%, treat as latent errors. Different benchmarks show different vulnerability for various components; but on average, Arbiter and Message passing interface are the most vulnerable components outside the tiles, while PC and Bus Handler have highest failure rate among in-tile components. Fault injection on each region has noticeable impact on the result of the other core. In general, fault injection in Shared regions has highest contribution in system failure.

This paper proposes a new switch box architecture in SRAM-based FPGAs to mitigate soft error effects. In this switch box architecture, the number of SRAM bits required for programming switch box is reduced to 67% without any impact on routing capability of the switch box. This architecture does not require any modification of the existing placement and routing algorithms. The architecture was evaluated based on several MCNC benchmarks using VPR tool. The experimental results show that this architecture decreases the susceptibility of switch boxes to SEUs about 20% on average compared to the traditional ones.

This paper presents Investigation of Transient Fault Effects in an asynchronous NoC router. The experiment is based on simulation-based fault injection method to assess the fault-tolerant behavior of the asynchronous router. The effort has been accomplished by employing fault injector signal (FIS) in 136 targets. 13600 transient and permanent faults have been injected into the CSP-Verilog model of NoC router. Different fault models such as glitch, cross-talk, SEU, and SET have been applied in this effort to evaluate asynchronous NoC Router. The experimental results have been considered in different aspects to estimate the NoC router's robustness. Although asynchronous designs seem inherently fault-tolerant due to applying handshaking signals, up to 56% of the injected faults result in failure, and about 43% of injected faults are overwritten before turning into errors. Less than 1% of injected faults treat as latent error. Moreover, the failure rate of token generation consumption is higher than token consumption effects.

This paper proposes two efficient software techniques, Control-flow and Data Errors Correction using Data-flow Graph Consideration (CDCC) and Miniaturized Check-Pointing (MCP), to detect and correct control-flow errors. These techniques have been implemented based on addition of redundant codes in a given program. The creativity applied in the methods for online detection and correction of the control-flow errors is using data-flow graph alongside of using control-flow graph. These techniques can detect most of the control-flow errors in the program firstly, and next can correct them, automatically. Therefore, both errors in the control-flow and program data which is caused by control-flow errors can be corrected, efficiently. In order to evaluate the proposed techniques, a post compiler is used, so that the techniques can be applied to every 80×86 binaries, transparently. Three benchmarks quick sort, matrix multiplication and linked list are used, and a total of 5000 transient faults are injected on several executable points in each program. The experimental results demonstrate that at least 93% and 89% of the control-flow errors can be detected and corrected without any data error generation by the CDCC and MCP, respectively. Moreover, the strength of these techniques is significant reduction in the performance and memory overheads in compare to traditional methods, for as much as remarkable correction abilities.

This paper presents an analysis of the effects and propagations of transient faults by simulation-based fault injection into the AVR microcontroller. This analysis is done by injecting 20000 transient faults into main components of the AVR microcontroller that is described in VHDL language. The sensitivity level of various points of the AVR microcontroller such as ALU, Instruction-Register, Program-Counter, Register-file and Flag Registers against fault manifestation is considered and evaluated. The behavior of AVR microcontroller against injected faults is reported and shown that about 41.46% of faults are recovered in simulation time, 53.84% of faults are effective faults and reminding 4.70% of faults are latent faults; moreover a comparison of the behavior of AVR microcontroller in fault injection experiments against some common microprocessors is done. Results of fault analyzing will be used in the future research to propose the fault-tolerant AVR microcontroller.

This paper evaluates fault-tolerant behavior of an NoC router through simulation-based method. A structural-level VHDL environment has been employed to estimate fault injector signal’s (FIS) effects. Different fault models such as dead clause, stuck-then, micro-operation, crosstalk, and SEU have been injected to evaluate the transient faults ’ effects. According to the results, up to 48 % of the injected faults cause system failure and also about 51 % are overwritten before turning into errors. Less than 1 % of injected faults treat as latent errors. The average of fault latency has been investigated as 194ns. Almost 70%, 31%, and 35 % of injected faults are overwritten in buffer, routing unit, and switch components, respectively. Routing unit is also recognized as the most tenuous component. 1.

FPGAs are an appealing solution for the space-based remote sensing applications. However, in a low-earth orbit, configuration bits of SRAM-based FPGAs are susceptible to single-event upsets (SEUs). In this paper, a new protected CLB and FPGA architecture are proposed which utilize error detection and correction codes to correct SEUs occurred in LUTs of the FPGA. The fault detection and correction is achieved using online or offline fast detection and correction cycles. In the latter, detection and correction is performed in predefined error-correction intervals. In both of them error detections and corrections of k-input LUTs are performed with a latency of 2kclock cycle without any required reconfiguration and significant area overhead. The power and area analysis of the proposed techniques show that these methods are more efficient than the traditional schemes such as duplication with comparison and TMR circuit design in the FPGAs.

This paper presents a high level method called matrix code to protect SRAM-based memories against multiple bit upsets. The proposed method combines hamming code and parity code to assure the reliability of memory in presence of multiple bit-upsets with low area and performance overhead. The method is evaluated using one million multiple-fault injection experiments; next reliability and MTTF of the protected memories are estimated based on fault injection experiments and several equations. The fault detection/correction coverage are also calculated and compared with previous methods i.e., Reed-Muller and hamming code. The results reveal that the proposed method behaves better than these methods in terms of fault detection and correction of multiple faults regarding to the area overhead.

This paper presents a bit-flip tolerance in SRAM-based FPGAs which suffers from high energy particles, alpha and neutrons in the atmosphere. For each of protections, the applicability, efficiency and implementation issues are discussed. Moreover, the area, the power and the protection capability of the methods are mentioned and compared with previous work. Based on the results of experiments and their analysis, one method is selected as best one. The selected method is much better than previous work e.g., duplication with comparison, triple modular redundancy which impose two and three area and power overheads, respectively.

In this paper, we propose two techniques to mitigate soft error effects on the switch modules of SRAM-based FPGAs: 1) The first technique tolerates SEU-caused open errors based on a new programming method for SRAM-bits of switch modules, and 2) The second technique mitigates SEU-cause short errors in the switch modules based on a mixed programmable and hard-wired switch module structure in the FPGAs. The effects of these two techniques on the delay, area and power consumption for 20 MCNC benchmark circuits are achieved using a minor modification in VPR and T-VPack FPGA CAD tools. The experimental results show that the first technique increase reliability of connections of switch module up to 30% while the second technique decreases the susceptibility of switch modules to SEUs about 50% compared to the traditional ones

This paper presents a SEU-mitigative placement and route of circuits in the FPGAs which is based on the popular placement and route tool. The tool is modified so that during placement and routing, decisions are taken with awareness of SEU-mitigation and no redundancies during the placement and routing are used but the algorithms are based on the SEU avoidance. We have investigated the effect of this tool on several MCNC benchmarks and the results of the placement and routing have been compared to the traditional one. The evaluations of results show that placement and routing can decrease the SEU rate of circuits implemented on FPGAs about 22%. However, it increases critical path delay and power consumptions of the circuits.

The technology of SRAM-based devices is sensible to single event upsets (SEUs) that may be induced mainly by high energy heavy ions and neutrons. We present a framework for the evaluation of fault-tolerant designs implemented on SRAM-based FPGAs using emulated SEUs. The SEU injection process is performed by inserting emulated SEUs in the device using its configuration bitstream file. An Altera FPGA, i.e. the Flex10K200, and the ITC'99 benchmark circuits are used to experimentally evaluate the method. The results show that between 32 to 45 percent of SEUs injected to the device propagate to the output terminals of the device.

This paper presents a new fault injection approach, which is based on a co-operation between a simulator and an emulator. This hybrid approach utilizes the advantages of both simulation-based fault injection as well as physical fault injection to provide a good controllability, observability and also a high speed in the fault injection experiments. To do this, parts of a circuit are simulated while the rest parts of the circuit are emulated. A fault injection tool called FITSEC (Fault Injection Tool based on Simulation and Emulation Cooperation) is developed, which supports the entire process of a system design. This is based on both Verilog and VHDL languages and can be used to inject faults at different levels of abstraction. The experimental results show that this approach can significantly reduce the time needed for executing fault injection campaigns.

SRAM-based FPGAs are currently utilized in applications such as industrial and space applications where high availability and reliability and low cost are important constraints. The technology of such devices is sensible to Single Event Upsets (SEUs) that may be originated mainly from heavy ion radiation. This paper presents a fault injection method that is based on emulated SEU on the configuration bitstream file of commercial SRAM-based FPGA devices to study the error propagation in these devices. To demonstrate the method, an Altera FPGA, i.e. the Flex10K200, and the ITC'99 benchmark circuits are used. A fault injection tool is developed to inject emulated SEU faults into the circuits. The results show that between 33 to 45 percent of the SEUs injected to the FPGA device have propagated to the output terminals of the device.

This paper presents transient and permanent fault injection into Verilog models of digital systems during the design phase by a developed simulation-based fault injection tool called INJECT. With this fault injection tool, it is possible to inject crucial fault models in all abstraction levels (such as swith-level) supported by Verilog HDL. Several fault models for injecting into Verilog models are specified and described. Analyzing the results obtained from the fault injections, using INJECT enables system designers to inform from dependable parameters, such as fault latency, propagation and coverage. As a case study, a 32-bit processor, namely DP32, has been evaluated and effects of faults on some important observation points have been presented. In this study, recovered errors are distinguished from those that affected the system behavior. The errors that lead to wrong results are separated from those that do not affect the correct results.