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Erik L. Dagless

dblp:54/2840 · DBLP profile ↗
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13ranked-venue papers
2as first author
0since 2021 · last 1996
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 8 · 2 first-authorArtificial intelligence and machine learning · 4Graphics, computer vision, multimedia, augmented reality and games · 3

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Integrated circuit design · 79% Hardware accelerators and domain-specific architectures · 10% GPUs and heterogeneous computing · 10%
Artificial intelligence
1 paper
Robot navigation and mapping · 77% 3D vision · 23%

Topics — the 6 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › digital circuit design
arithmetic circuit design
0.011996
A New Approach to Fixed-Coefficient Inner Product Computation Over Finite Rings · IEEE Trans. Computers 1996
Integrated circuit design › digital circuit design › arithmetic circuit design
inner product computation
0.011996
A New Approach to Fixed-Coefficient Inner Product Computation Over Finite Rings · IEEE Trans. Computers 1996
Integrated circuit design
residue number system arithmetic
0.011996
A New Approach to Fixed-Coefficient Inner Product Computation Over Finite Rings · IEEE Trans. Computers 1996
Robotics › Robot navigation and mapping › mobile robot navigation › ground vehicle navigation
road following
0.011990
Road Following Algorithm Using A Panned Plan-View Transformation · ECCV 1990
GPUs and heterogeneous computing
vision processing
0.011990
A Heterogeneous Vision Architecture · ECCV 1990
Integrated circuit design
digital signal processing circuits
0.011996
A New Approach to Fixed-Coefficient Inner Product Computation Over Finite Rings · IEEE Trans. Computers 1996

Methods — techniques the papers use, named apart from their topics

residue number system · 0.0number theory · 0.0abstract algebra · 0.0vision accelerators · 0.0panned plan-view transformation · 0.0heterogeneous computing · 0.0
YearPublicationVenuePosition
1996 A New Approach to Fixed-Coefficient Inner Product Computation Over Finite Rings
abstract
Inherently parallel arithmetic based on the residue number system (RNS) lends itself very well to implementation of high-speed digital signal processing (DSP) hardware. In most cases, DSP computations can be decomposed to the inner product form Y=/spl Sigma//sub i=0//sup N-1/C/sub i/X/sub i/. Therefore, implementation of the inner product computation over finite rings is of paramount importance for RNS-based DSP hardware. Recently, periodic properties of residues of powers of 2 have been found useful in designing residue arithmetic circuits. This paper presents a deeper insight to the periodicity concepts by applying abstract algebra and number theory methods. Advantage is taken of the fact that the set Z/sub m//sup +/={1, 2, ..., m-1} splits completely, with respect to some g/spl isin/Z/sub m//sup +/, into sets which are closed under multiplication by g modulo m. Properties of such a decomposition of Z/sub m//sup +/ are investigated and the theory is applied to develop new fixed-coefficient inner product circuits for finite-ring arithmetic. The new designs are almost exclusively composed of full adders and they can easily be pipelined to achieve very high throughput. A VLSI implementation study of the new inner product circuits is presented. It shows that, compared with the best method known to date, both smaller area requirements and higher throughput are achieved.
Artur Wrzyszcz, David Milford, Erik L. Dagless
IEEE Trans. Computers3
1995 An enhanced algorithm for the minimization of exclusive-OR sum-of-products for incompletely specified functions
abstract
Most of the current exclusive-OR sum-of-products minimization algorithms use rule-based heuristics to transform an initial circuit description into a possibly compact form. This paper presents an enhanced minimization algorithm, MINT, introducing new transformations including rules operating on three product terms at a time. These multiple-product-term transformations prove to be an efficient extension of previously defined two-product-term operating rules. Additionally, new efficient procedures for the optimization based on the use of don't cares are introduced. The algorithm can simplify multiple-valued input two-valued multiple-output incompletely specified functions.
Tomasz Kozlowski, Erik L. Dagless, Jonathan Saul
ICCD2
1995 DART: delay and routability driven technology mapping for LUT based FPGAs
abstract
A two-phased approach for routability directed delay-optimal mapping of LUT based FPGAs is presented based on the results of stochastic routability analysis. First, delay-optimal mapping is performed which simultaneously minimizes area and delay. Then, the mapped circuits are restructured to alleviate the potential routing congestions. Experimental results indicate that the first phase creates designs which require 17% fewer levels and 40% fewer LUTs than MIS-pga (delay), 11% fewer levels and 37% fewer LUTs than FlowMap-r, and 5% fewer levels and 39% fewer LUTs than TechMap-D. The success of the second phase is confirmed by running a vendor's layout tool APR. It is observed that they are more routable and have less final delays than those produced by other mappers if they are placed and routed.
Aiguo Lu, Erik L. Dagless, Jonathan M. Saul
ICCD2
1994 Architecture Oriented Logic Optimization for Lookup Table Based FPGAs
abstract
A logic optimization criterion for lookup-table based field programmable gate arrays (FPGAs) is presented. Based on this criterion, several key operations of logic optimization, such as extraction, decomposition, resubstitution and simplification, are discussed, so as to make them evaluate the circuit cost in accordance with the target technology. Using our approaches to do logic optimization for lookup-table based FPGAs, we obtain a good starting point for technology mapping. On the basis of 25 benchmark examples, our optimized circuits require 14% fewer configurable logic blocks (CLBs) than the circuits optimized by MIS-II if both are subsequently mapped using MIS-pga. Moreover, the number of circuit levels is also slightly improved.>
Aiguo Lu, Jonathan Saul, Erik L. Dagless
ICCD3
1993 A Temporal Smoothing Technique for Real-Time Motion Detection
J. Bulas-Cruz, A. T. Ali, Erik L. Dagless
CAIP3
1991 A visual tracking system for the measurement of dynamic structural displacements
abstract
Abstract A transputer‐based system has been developed for the measurement of dynamic displacements in real time by visually tracking moving objects from a video Input. Parallel processing techniques have been used to track multiple objects at frame rate, and various predictive tracking algorithms have been assessed and implemented on the transputer network. The system is primarily intended for applications such as the monitoring or testing of large physical structures where actual displacements may not easily be otherwise determined. Results from the monitoring of the behaviour of the Humber Bridge at the centre of its span are presented.
G. A. Stephen, Erik L. Dagless, C. A. Taylor
Concurr. Pract. Exp.2
1990 A Heterogeneous Vision Architecture
Andrew W. G. Duller, Richard H. Storer, Andrew R. Thomson, Mike R. Pout, Erik L. Dagless
ECCV5
1990 Road Following Algorithm Using A Panned Plan-View Transformation
Roberto A. Lotufo, Barry T. Thomas, Erik L. Dagless
ECCV3
1990 Road edge tracking for robot road following: a real-time implementation
A. D. Morgan, Erik L. Dagless, David Milford, Barry T. Thomas
Image Vis. Comput.2
1989 An associative processor array for image processing
Andrew W. G. Duller, Richard H. Storer, Andrew R. Thomson, Erik L. Dagless
Image Vis. Comput.4
1978 A keyboard-oriented microprogram emulator and tester
Erik L. Dagless, B. G. Davies, Martyn Edwards 0001
Euromicro Newsletter1
1977 Comparison of microprocessors: a graphical approach
David Aspinall 0002, Michael Barton 0001, Erik L. Dagless
Euromicro Newsletter3
1977 Teaching microprocessors at university
Erik L. Dagless, John S. D. Mason
Euromicro Newsletter1